Int. J. Electron. Commun.

(AEÜ) 91 (2018) 91–102

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Int. J. Electron. Commun. (AEÜ)

journal homepage: www.elsevier.com/locate/aeue

Regular paper

Memristor augmented approximate adders and subtractors for image T

processing applications: An approach
⁎
S. Muthulakshmi, Chandra Sekhar Dash, S.R.S. Prabaharan
School of Electronics Engineering, Vellore Institute of Technology, Vandalur-Kelambakkam Road, Chennai 600127, India

A R T I C LE I N FO A B S T R A C T

Keywords: Approximate computing aims at reducing circuit complexity and delay, by allowing leverages in the output for a
Memristors certain combination of inputs. The reduction in circuit complexity is achieved by minimizing the number of
Adder components in the circuit. This paper proposes a plausible approach towards approximate computing with
Approximate adder memristors for designing memristor based approximate full adder and subtractor with logic minimization
Approximate computing
technique. The validation of our proposed approximate adder is verified by designing an 8-bit Ripple Carry
Image processing
Adder (RCA) to perform bitwise pixel addition of two gray scale images of the same size and compare the design
with images obtained by exact addition method. Similarly, we have affirmed that the designed 8-bit Ripple
Borrow Subtractor (RBS) is verified on foreground detection. Furthermore, to corroborate the above observation,
performance metrics like Mean Square Error (MSE), Peak Signal to Noise Ratio (PSNR), Structural Content (SC),
Mean Absolute Error (MAE), Average Distance (AD), Mean Average Distance (MAD) and Normalized Absolute
Error (NAE) are deduced in MATLAB®. Owing to the logic minimization technique, for a certain combination of
inputs, the MSE has been found to be predominant and its impact on PSNR is studied.

1. Introduction as approximate computing [2]. Thus, the approximate computing can be

Modern computing world is moving towards energy efficient design
techniques rather than performance driven, to justify the gap between
the scalability issues with CMOS technology and the challenges cen-
tered on big data handling. Most of the portable hand held devices are
predominantly power hungers operated in battery power, which de-
mands less hardware area and less energy consumption per operation
[1]. Moreover, Hewlett Packard envisaged that, by 2025, around 3
billion connected devices will produce 1030 geopbyte of data, which
cannot be handled by the existing legacy computers. Furthermore, ex-
isting computing systems are designed to produce exact results at the
cost of relatively high energy consumption.
On the other hand, the exploration of new data produced by low
power devices emanated from different types devices such as sensor and
interfaces costs high in terms of energy consumption and data acqui-
sition when processed through conventional computers, by accessing
the gathered data from memory. When these new types of data are
processed by low power and less expensive circuits, they are not ex-
pected to produce high precision results while the tradeoff being the
less energy consumption. At the same time, when these energy efficient
circuits are used in high throughput mode, it produces highly un-
predictable performance and inaccurate results. Therefore, it is termed
defined as producing acceptable quality of results by less hardware
circuit elements as well as less power consumption with minimum
delay in operation.
Nevertheless, accurate result is not necessary for applications like
media processing, search engines, mining, embedded systems applica-
tions handling real time sensors data (noisy input) etc. These kinds of
inherent error resilient applications are found to be more suitable for
approximate computing technique, where approximate results are suf-
fice. Such applications are useful, owing to its intrinsic inability of
human senses to interpret degradation in the quality of audio and visual
information, presence of redundancy in the inputs and non-existence of
accurate results [2,5]. Since approximate computing is one of the
promising energy efficient techniques, the latter technique can be em-
ployed for inherent error resilient applications [1–6].
Approximation can be introduced either in hardware level by de-
signing approximate hardware circuits, which can be integrated to
build approximate architecture or in software level by skipping algo-
rithms and intermediate modules. To elaborate on the hardware level
approximation, approximate computing is attained by redesigning the
accurate digital logic circuits into an approximate version by lowering
the number of circuit components such as transistors, CNTFET etc. [1],
which diminish the signal propagation path from input to output. This

⁎
Corresponding author.
E-mail addresses: prabaharan.srs@vit.ac.in, srsprabaharan1611@gmail.com (S.R.S. Prabaharan).

https://doi.org/10.1016/j.aeue.2018.05.003
Received 26 January 2018; Accepted 3 May 2018
1434-8411/ © 2018 Elsevier GmbH. All rights reserved.
S. Muthulakshmi et al. Int. J. Electron. Commun. (AEÜ) 91 (2018) 91–102

Fig. 1. The VTEAM model perturbed with a sinusoidal signal of amplitude 1 V and frequency = 50 MHz. Fitting parameters that are used during simulation are
Voff = 0.02 V , Von = −0.2 V K off = 5 × 10−4 m/s, K on = −10 m/s , αon = 3 and αoff = 1 woff = 3 nm and won = 0 Ron = 50 Ω and Roff = 1000 Ω winit = 0.5. (a) Mathematical
model of TiO2 based Memristor where woff and won are the width of the undoped and doped region respectively and w is the length of the active region. (b) Pinched
Hysteresis of memristor Voff = 0.02 V, Von = −0.2V defining the set/Reset mechanism where with Vreset = 0.02 V, and Vset = −0.2 V. [Data independently verified using
Cadence virtuoso by using Verilog-A SPICE model]. The mark “I” increases/decreases corresponds to the overall increase/decrease in the value of resistance of the
memristor (M(q)).

in turn produces accurate output for maximum number of input com-
binations and errored result for certain input combinations. Moreover,
with an emergence of Internet of Things (IoT), there is a huge growth of
digital data which demands fast memory access and high density sto-
rage technologies. Hence, to handle these kinds of data intensive ap-
plications, the processor is tied down with memory for a long time to
access data from memory for processing. Though the computational
speed is attained by the present day digital computers, the speed and
bandwidth of memory is the critical issue, to support it. This problem is
known as memory wall problem [7]. Since memristors can be employed
as both memory and logic element, they provide a scope to go beyond
Von Neumann architecture, which is one of the plausible techniques to
address the memory wall problem.
Memristor is fabricated between two layers of noble metal acting as
ion blocking electrodes above the CMOS substrate; therefore on the
same piece of die, ample amount of logical computations can be per-
formed and integrated with memory [8,9]. Moreover, memristor is
widely used in applications viz., analog, neuromorphic computing
[10–12], hyper-chaotic system [13–16] etc. Recently, Jang et al. have
fabricated memristor aided logic architecture using pV3D3 [poly (1,3,5-
trivinyl1-1,3,5-trimethyl cyclotrisiloxane] within a crossbar array and
observed 0 W static power consumption on a flexible PES (poly-
ethersulfone) substrate [17], which was theoretically proposed by
Kvatinsky et al. [18]. With this background, we suggest an approach
towards approximate computing technique with memristors, where the
logic state of the device is controlled by change in resistance of the
memristor. Recently, Ghofrani et al. designed energy efficient associa-
tive memory architecture in the form of look-up tables enabling com-
putation within memory. They further employed approximate
computing by taking aid of application-level resilience to errors, which
reduced the energy consumption of associative memristive memory
architecture [19].
As stated earlier, arithmetic circuits are well suited for approximate
computing; besides full adder and subtractor are mainly considered by
researchers because about 80% of the computer operations are carried
out only through these two arithmetic circuits; its performance sig-
nificantly contributes to the performance of the larger blocks like
multiplier and divider [1,20,21]. Since full adders are the integral part
of Computation-In-Memory architecture, there is plethora of reports on
memristor based adders [22–26].
In this context, we propose memristor based approximate full adder
and subtractor for the first time and the capacity of the proposed adder
and subtractor architecture is verified in image addition and foreground
detection respectively. Although other plausible applications such as
filtering and edge detection are available, we choose to adapt addition
and subtraction as examples of image processing applications because
the performances of higher order blocks are dominated by the funda-
mental unit of the architecture.
2. Memristor fundamentals
The term memristor (memory + resistor) was proposed in 1971 and
was connected to the resistive switching phenomenon in 2008 [8,27]. It
is basically composed of one stoichiometric TiO2 layer over which a
non-stoichiometric TiO2-x is deposited and is sandwiched between top
and bottom platinum (Pt) electrodes as shown in Fig. 1(a) [8]. This
creates a non–equilibrium state which results in the formation and
rupture of conductive filaments (conducting channel) upon applying

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S. Muthulakshmi et al.
Fig. 2. (a) Schematic of the entire work flow presented emphasizing memristor based approximate computing.
Fig. 3. Schematic of Memristor Ratioed Logic (a) OR and (b) AND gates [30] which are used as building blocks for designing approximate adders.
the electric field [28–31]. The above two phenomenon yields a non-
linear pinched hysteresis and thus able to switch the device among the
two extreme resistance states, i.e., low resistance state (LRS) and high
resistance state (HRS) which are regarded as logic “1” and logic “0”
respectively as shown in Fig. 1(b). The pinched hysteresis loop eluci-
dates word write and erase (SET/RESET) in a cyclic fashion [8]. The
intrinsic bulk resistivity is changed by virtue of ion migration duly in-
itiated by external applied potential. When the said field is removed,
the ion migration ceases and the migrated ion stays in the defect sites
where it got migrated and this is perceived as memory, tuned solely by
the resistivity changes, the so-called non-volatile memory [31]. Though
there are ample mathematical models reported defining the working of
memristor [32–37], there are instances where threshold is exhibited
[32].
Two terminal memristor devices where, when the device is per-
turbed with an external bias voltage, the current across the device
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Int. J. Electron. Commun. (AEÜ) 91 (2018) 91–102
increases which implies an increase in the amount of charge associated
with the device there by lowering the overall memristance (M (q)) and
vice versa upon reversal of applied bias.
Since the above switching parameters have profound effect on the
experimentally fabricated memristor device, we have chosen to adapt
VTEAM model proposed by Kvatinsky et al. [35] for the present work.
Memristor is basically a voltage controlled two terminal passive device
denoted by Eq. (1), where w is the internal state variable whose length
varies from 0 to the maximum length of the active layer under the effect
of an external bias (V).
dw (t )
= f (w,v ),
dt (1)
The current i (t ) passing over the device is given by (2)
i (t ) = G (w,v )·v (t ), (2)
S. Muthulakshmi et al. Int. J. Electron. Commun. (AEÜ) 91 (2018) 91–102

Fig. 4. Methodology of the proposed design.

where G(w,v) is the conductance of memristor. In this paper, the ex- 3. Memristor based approximate circuits
pression for the rate of change of state variable is modeled using the
VTEAM model [35], with the incorporation of threshold voltages (Voff , Interestingly, it has been realized by several groups that memristor
Von ), and is is fabricated on Si substrate whose compatibility with much acclaimed
Case I CMOS circuitry is obviously in place, realizing any gate level equation
αoff
in combination with CMOS inverter is plausible. The following design
dw (t )
= koff . ⎛⎜
v (t ) ⎞
−1⎟ . foff (w ),0 < voff < v flow and its verification have been elucidated in the above context.
dt ⎝ voff ⎠ (3)
3.1. Memristor based approximate adder (MAA)
Case II
αon Traditional full adder circuit like N-bit Ripple Carry Adder (RCA) is
dw (t ) v (t ) ⎞
= kon. ⎛⎜ −1 ⎟ . fon (w ),v < von < 0 built by cascading N-number of single bit adder modules that takes two
dt ⎝ von ⎠ (4)
operands (A, B) along with carry (Cin) as input and produces SUM/
where K off , K on , αon and αoff are fitting parameters/constants given by CARRY as output. The CARRY generated from each single bit full adder
Eqs. (3) and (4) [35]. It is zero if the applied bias is less than Voff. The module is fed into the next immediate higher order block as Cin. Hence,
device turns ON only when the applied bias voltage is greater than the an N-bit RCA produces output only after the addition of all the N-bits,
ON state threshold voltage (Von ). It is well known that a linear depen- i.e., the delay in producing output increases as the number of bits in-
dence between the state variable and the device resistance is adapted in creases, which makes the adder being slow, that consequently degrades
VTEAM model; the current-voltage expression is given by Eq. (5) the speed performance. Also, these traditional circuits are built with
CMOS technology; they suffer from high energy and power consump-
−1
Roff −Ron tion. One of the possible ways to improve the performance of the adder
i (t ) = ⎡Ron + . (w−won )⎤ . v (t )
⎢ w −w ⎥ circuit is by reducing the delay. This can be achieved by decreasing the
⎣ off on ⎦ (5)
complexity of the circuit with lesser number of circuit components. This
where Ron and Roff are ON and OFF state resistances respectively.woff approach not only reduces the delay but also minimizes the energy and
and won are length of the non-stoichiometric (in the case of TiO2-x) and power consumption, with slight compromise on accuracy. In order to
stoichiometric region (TiO2) respectively as well. The present work design CMOS based approximate full adder arithmetic architecture,
proposes the approximate adder and subtractor circuit design equipped several techniques like cell replacement, truncation, segmentation,
with memristors and the results are simulated employing VTEAM logic minimization etc. are used. With cell replacement technique, ac-
model and CMOS 180 nm transistors appropriately. curate module of the adder circuit is replaced by its lower circuit

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S. Muthulakshmi et al. Int. J. Electron. Commun. (AEÜ) 91 (2018) 91–102

Fig. 5. Schematic of a one-bit memristor based full adder.

Fig. 6. Output waveform of a one-bit memristive full adder input combinations A = 1, B = 1, C = 1, the generated SUM = 1 and CARRY = 1; Similarly,for input
combinations A = 0, B = 0, C = 0, the resultant SUM = 0 and CARRY = 0.

complexity equivalent the so-called approximate circuit, thus introdu-
cing deviation in the expected output. Almurib et al. have designed
inexact adder cells through cell replacement technique with less
number of transistors led to a shorter critical path [2]. Another tech-
nique is truncation technique, where many versions of approximate
adder circuit are designed by truncating the propagation of carry to
higher blocks aimed at minimizing the delay; thereby achieving higher
speed performance. Segmentation technique divides the entire accurate
architecture into number of segments and replaces the least significant
modules with approximate blocks [5]. Approximate circuits are built
with logic minimization technique in which bits are reversed in Kar-
naugh map to reduce the complexity of the logical functions, which in
turn reduces the gate level complexity.
In our approach, the proposed memristor based approximate ar-
chitecture is designed with logic minimization technique by random
introduction of errors in SUM and CARRY of the traditional full adder
truth table to arrive at the approximate version as depicted in Fig. 2,
which we have achieved with lesser number of memristive logic gates.
To begin with, we consider the sum of product (SOP) expression for
a conventional full adder:

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Table 1 with the device fed with lower voltage is increasing. On completion of
Proposed truth table. the logical operation, the resistance associated with both the memris-
Input Combination Actual Output Approximate Output tors is nearly equal to Ron and Roff respectively. The voltage at the
output of OR gate is calculated by employing voltage division rule
A B C SUM CARRY SUM CARRY across both the memristors as given in Eq. (7)
0 0 0 0 0 0 0
0 0 1 1 0 1 1× Roff
0 1 0 1 0 0× 0 Vout ,OR = Vhigh = Vhigh
Roff + Ron (7)
0 1 1 0 1 1× 1
1 0 0 1 0 0× 0
When both the inputs are logic 0, no current flows through the
1 0 1 0 1 0 0×
1 1 0 0 1 0 1 circuit as there is no voltage drop between the inputs, hence Vout is low.
1 1 1 1 1 1 1 Similarly, when both the inputs are logic 1, both memristors are in LRS,
hence Vout is high [38].
*× – errored SUM and CARRY. The working of MRL AND gate is similar to the operation of OR gate
only with reversal of polarity of each memristor as shown Fig. 3(b). The
SUM = A B C + A BC + AB C + ABC (6a) expression for output voltage Vout is given in Eq. (8), when both the
inputs are not identical
CARRY = A BC + AB C + ABC + ABC (6b)
Ron
Accordingly, the proposed architecture incorporated the above ex- Vout ,AND = Vhigh = 0
Ron + Roff (8)
pressions for SUM and CARRY which can be realized using both AND
and OR gates built with Memristor Ratioed Logic (MRL) [34] is de- The workflow shown in Fig. 4 depicts the proposed approach of
scribed as follows. approximate computing employing memristor based full adders and its
application in image processing. The basic building block of our eight-
3.2. Memristive logic gates bit memristor based approximate RCA circuit is a one-bit adder cell
based on MRL AND and OR gates [38]. The capacity of the proposed
The MRL OR gate is designed by connecting two memristors in architecture is validated on image processing application, where two
series with opposite polarity as shown in Fig. 3(a). Upon stimulation of images of the same size are considered and bit-wise pixel addition is
bias voltage, the resistance of the memristor device decreases. Thus, performed using exact and approximate logic. As this class of applica-
when one input VA is high and the other input VB is low, the current tion deals with large amount of data, a python code is employed to
flows from high voltage to low voltage which causes change in re- perform approximate pixel addition. MATLAB is used to perform exact
sistance state of both memristors. The resistance of the device stimu- addition. Finally both the images obtained by exact and approximate
lated with higher voltage is lowered while the resistance associated addition are compared on the basis of performance metrics and are

Fig. 7. Schematic of proposed memristor based one-bit approximate full adder.

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S. Muthulakshmi et al. Int. J. Electron. Commun. (AEÜ) 91 (2018) 91–102

Fig. 8. Output waveform of proposed Memristor based one-bit Approximate Full Adder for input combinations A = 1, B = 1, C = 1, the generated SUM = 1 and
CARRY = 1; Similarly, for input combinations A = 0, B = 0, C = 0, the resultant SUM = 0 and CARRY = 0 as expected.

Fig. 9. Waveform exhibiting erroneous (a) for the input combinations of A = 1, B = 0 and C = 0,

deduced using MATLAB.
The ‘complete’ memristor based accurate full adder is designed using
the SOP expression for SUM and CARRY from Eq. (6). CMOS inverters
are engaged to provide negated inputs. The design in Fig. 5 utilizes 33
memristors and the logic state of the device is controlled by tuning the
resistance state of the memristor by providing appropriate external bias
voltage. Although the same SOP expression can be implemented by
CMOS, with exactly the same results, it must be noted that the proposed
circuitry is implemented using memristor, which is identified as a po-
tential candidate to perform logic in-memory which is not possible with
the prevailing CMOS technology [38].
The output waveform for input combinations A = 1, B = 1 and
C = 1 and A = 0, B = 0 and C = 0 is shown in Fig. 6. As one-bit MRL
based full adder is designed only with memristors and without CMOS

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Table 2 the number of input bits. Error Distance (ED) is the arithmetic differ-
Proposed truth table of approximate subtractor. ence between the exact and approximate result. Mean Error Distance
Input Actual ApXs1 ApXs2 (MED) is the average of error distance.
In the proposed approximate adder circuit, three errors are in-
X Y Z D B D B D B troduced in SUM and two errors are introduced in CARRY, hence the
0 0 0 0 0 0 0 0 0
estimated error rate is to be 37.5% and 25%, respectively. The delay for
0 0 1 1 1 1 0× 1 1
0 1 0 1 1 0× 1 1 0×
one-bit accurate and approximate adder is obtained as 32.56 ns and
0 1 1 0 1 0 1 0 1 0.2316 ns, respectively, demonstrating a significant reduction in the
1 0 0 1 0 1 0 1 0 delay.
1 0 1 0 0 0 0 0 0 To deduce the error distance, we need to consider the arithmetic
1 1 0 0 0 1× 0 1× 0
difference between the exact and the approximate result, for instance
1 1 1 1 1 1 1 1 1
10,111,111 and 10,111,111 is added using our proposed approximate
*X – marks stands for the combinations where error is incorporated. adder and exact adder. An error distance of 1 is obtained when initial
CARRY (Cin) = 0 and not considering the final carry (Cout). All the
transistors, it might plausibly lower overall die area consumption. performance metrics stated above are calculated with proposed ap-
Nevertheless, it is accurately not possible to measure the energy and proximate and exact 8-bit ripple carry adders for the same set of input
power dissipation although expectedly such reduction in die area would combinations. Note that buffers, inverters and CMOS logic gates are
lower energy and power dissipation. used in the intermediate states where the magnified input signal is re-
For the proposed approximate full adder, three bits in SUM and two quired. Furthermore, the simulation results for the inaccurate working
bits in CARRY output are flipped to generate inaccurate output as listed of our proposed memristor based approximate adder are shown in
in Table 1. The SOP expression for the proposed approximate adder Fig. 8.
obtained by simplifying Karnaugh Map is The waveforms in Fig. 9 (a) and (b) represent the inaccurate output
for SUM and CARRY that matches with the proposed truth Table 1. For
SUM = A C + BC (9a)
example, for the input combination A = 1, B = 0 and if C = 0, then
CARRY = A C + AB (9b) SUM = 0 which is inaccurate, while we get CARRY = 0 i.e. accurate,
which matches with our proposed truth table as shown in Fig. 9 (a).
The schematic of the proposed memristor based single-bit approx- Similarly inexact CARRY is illustrated in Fig. 9(b) for input combina-
imate full adder is shown in Fig. 7. In order to evaluate the performance tions A = 0, B = 0 and C = 1.
of proposed approximate adder, the metrics such as Error Rate (ER),
Error Distance (ED) and Mean Error Distance (MED) are calculated
using the methods mentioned in [2–4]. The percentage of erroneous 3.3. Memristor based approximate subtractor (MAS)
outputs among all outputs is called as error rate. The general formula to
determine error rate is ER= (Number of errors/2n) × 100, where n is To the best of our knowledge, there were no attempts hitherto on

Fig. 10. Schematic of proposed Memristor based one-bit Approximate Full Subtractor (a) ApXs1 – with 2 errored bits in Difference and 1 errored bit in Borrow, (b)
ApXs2– with 1 errored bits in Difference and 1 errored bit in Borrow; memristor logic gates are shown for clarity to exhibit the number of memristors used for the
logical operation. [ApX refers to approximation].

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S. Muthulakshmi et al.
Fig. 11. Output waveform illustrating approximate difference for (a) ApXs1 (b) ApXs2. In both cases, arrow mark indicates the inexact difference output 1 for the
input combinations xyz “110”.
memristor based approximate circuits using subtractor. Hence, we at-
tempt to design MAS employing memristors as well.
Accordingly, the SOP expression for Difference and Borrow out of
exact subtractor is
D = X Y Z+ X YZ + XY Z + XYZ (10a)
(10b)
B = X Y Z+ X YZ + X YZ + XYZ
where X, Y are the inputs and Z is borrow in.
Similarly, using Karnaugh map, the expression for approximate
subtractors (ApXs1 & ApXs2) is derived from the suggested approximate
truth table (see Table 2) through probabilistic logic minimization
technique and the resulting expressions are shown in Eqs. (11) and (12).
The SOP equations of ApXs1 are derived by employing logic mini-
mization technique to flip two bits in difference and one bit in borrow.
In the same way, one bit in difference and one bit in borrow is flipped to
derive SOP equations for ApXs2. Fig. 10(a & b) illustrate the corre-
sponding one-bit approximate subtractor circuit corroborated with de-
rived K-map yielding the delay for ApXs1 and ApXs2 as 800 ps and
200 ps respectively. Thus, the proposed approximate subtractors (ApXs1
&ApXs2) exhibited the improved delay performance in comparison to
the exact one-bit full subtractor of 16.78 ns (see Fig. 11).
ApXs1
D = XZ + XY + X Y Z (11a)
B = X Y + YZ (11b)
ApXs2
D = XZ + XY + YZ + X Y Z (12a)
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Int. J. Electron. Commun. (AEÜ) 91 (2018) 91–102
B = X Z + YZ (12b)
Interestingly, as expected a decrease in die area can be claimed as
the number of memristors used in the design of exact subtractor, ApXs1
and ApXs2 was found to be 25, 16 and 19 respectively.
4. Application in image processing
4.1. Image addition
A single memristor cell can store a single data bit and can be ac-
cessed based on the address instructed by the control unit of the pro-
cessor for read/write the data. Memristor based crossbar memory array
can be efficiently used to store the image by adapting the approach
proposed by XiaoFang et al. [39] in which each memristor stores a pixel
value. Also, it can be employed to store both binary and grayscale va-
lues as well. The presence of copious resistance states in memristor
facilitates storing the grayscale values. In order to store bigger size
images, only the number of rows and columns need to be increased.
Here, we have considered the grayscale value ‘0’ that corresponds to the
HRS state of the device while grayscale value ‘255’ denotes LRS. The
interim gray scale values correspond to the intermediate resistance
states [39]. While the interim resistance states can be achieved by
keeping the amplitude of the applied voltage constant by varying the
pulse width.
To further evaluate the performance of the proposed memristor
based approximate adder, it has been utilized to add two images of
same size (m × n) which generated a new image of the same size as
shown in Fig. 12. A 512 x 512 Lena image is added with Bright Dark
S. Muthulakshmi et al. Int. J. Electron. Commun. (AEÜ) 91 (2018) 91–102

Fig. 12. Image addition using proposed approximate adder. (a) Input image 1(Bright dark circles image) (b) Input image 2(Lena) (c) Output image generated by exact
addition (d) Output image generated by approximate addition.

m n
circles image where the image obtained by approximate addition re- 1
sembles the image obtained with exact addition as shown in Fig. 12.
AD =
m×n
∑∑ (a (i,j )−e (i,j ))
i=1 j=1 (13)

4.2. Foreground detection Maximum Absolute Difference (MAD): It is the maximum pixel value
obtained upon taking absolute of the difference between the pixel va-
Background removal and foreground detection are the two main lues of images achieved by accurate and approximate addition as
processes in the domain of computer vision to detect the changes in the mentioned
image sequence. Hence, an 8-bit RBS is constructed using one-bit pro-
MAD = max{|a (i,j )−e (i,j )|}
posed approximate subtractor and the same is evaluated on foreground m,n (14)
detection by performing the pixel subtraction of two images (Image 1&
Image 2) of the same size using ApXs1 and ApXs2. The resultant images Mean Absolute Error: It is measured as the average of the sum of the
attained after performing pixel subtraction is shown in Fig. 13. It is absolute difference between pixel values of accurate and approximate
found that image obtained with approximate subtraction is similar to image. MAE can be expressed as
the image obtained by exact subtraction. The various performance 1
m n

metrics such as Average Distance (AD), Maximum Absolute Distance MAE =

m×n
∑∑ |a (i,j )−e (i,j )|
(MAD), Mean Absolute Error (MAE), Normalized Absolute Error (NAE), i=1 j=1 (15)
Mean Square Error (MSE), Structural Content (SC) and Peak-Signal to Mean Square Error (MSE): It is the measure of averaging the square
Noise Ratio (PSNR) are deduced using MATLAB and mentioned in of pixel difference between accurate and approximate images. The ex-
Tables 3 and 4 for approximate adders and subtractors. pression for MSE is
In order to determine the quality of the resultant image following
m n
metrics are computed using MATLAB® from the literature reported 1
elsewhere for the image [2–4].
MSE =
m×n
∑∑ (a (i,j )−e (i,j ))2
i=1 j=1 (16)
Average Difference: It is the average of the sum of the difference
th th
between the pixel values of images achieved by accurate and approx- where a (i, j) and e (i, j) are pixel values of i row and j column of
imate addition stated as accurate and approximate image. m and n denotes the width and height

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S. Muthulakshmi et al. Int. J. Electron. Commun. (AEÜ) 91 (2018) 91–102

Fig. 13. Foreground detection using proposed approximate Subtractor a. Input Image1, b. Input Image 2, c. Output Image after Exact Subtraction, d. Output Image
using ApXs1, e. Output Image by ApXs2.

Table 3 addition. The formula for calculating NAE is

performance metrics of proposed memristor based approx- m n
imate adder. ∑∑ |a (i,j )−e (i,j )|
Parameters Approximate addition i=1 j=1
NAE = m n

AD 140.6484 ∑∑ a (i,j )2
MAD 255 i=1 j=1 (17)
MAE 140.6484
MSE 28,503 Structural Content (SC): It is the ratio of sum of pixel values of the
NAE .0030 image obtained by accurate addition to the image attained by approx-
SC 2.7189 imate addition given as
PSNR 8.24 dB
m n
∑∑ (a (i,j )2
i=1 j=1
Table 4 SC = m n
Performance metrices of proposed memristor based approximate subtractor. ∑∑ (e (i,j )2
i=1 j=1 (18)
Parameters ApXs1 ApXs2
Peak signal to Noise Ratio (PSNR): It is the logarithmic difference
AD 10.3099 2.5154
MAD 225 225 between the square of the maximum possible value of pixel of the image
MAE 10.3099 2.5154 and MSE. It is indirectly proportional to MSE i.e. higher the MSE lower
MSE 87.6338 174.7817 the PSNR. In this case PSNR is affected by MSE. In Eq. (19), the PSNR is
NAE 0.0013 3.09 × 10−4 defined mathematically as
SC 0.2394 0.1735
PSNR 66 dB 59.18 dB (2n−1)2
PSNR = 10log10
MSE (19)

of the images. As mentioned in previous section, the MSE is pre-
dominant owing to the intentional incorporation of error in SUM and
CARRY for certain combination of inputs. The MSE is expected to be
lower; nevertheless, due to intentional incorporation of errors in the
process of approximation, the obtained MSE is comparatively higher.
Normalized Absolute Error: It is the ratio of the sum of absolute dif-
ference between pixel values of accurate and approximate image and
the sum of square of pixel values of the image obtained by exact
It is instrumental in comparing restoration results for the same
image; one cannot judge the visibility of an image on the basis of PSNR
values. Sometimes an image with low PSNR value may look much
better than an image with higher PSNR [40].
The different performance metrics by computing the resultant
images obtained by exact and approximate addition and subtraction
methods are summarized in Tables 3 and 4.
It is observed that the values of the parameters like SC, MSE, PSNR,
MAE and NAE are found to be low, as all the bits are approximated

101
S. Muthulakshmi et al.
considering the worst case scenario, in contrary to the findings of
Almurib et al. [2]. These parameters can be further improved by em-
ploying logic minimization with cell replacement technique and the
results will be published elsewhere.
5. Conclusions
A plausible approach towards approximate computing with mem-
ristor is studied by designing approximate arithmetic architecture
through logic minimization technique for the first time. Further, 8-bit
Ripple Carry Adder is designed using the proposed approximate mem-
ristor full adder and the performance metrics such as ED, MED and ER
are computed. In addition to that, process of storing and retrieving the
image in memristor based crossbar memory array is studied. Moreover,
its performance is analyzed by adding two grayscale images of the same
size and various error metrics such as MSE, PSNR, AD, MAD, MAE, NAE
and SC are deduced. The above mentioned performance metrics were
calculated and verified using the designed RBS for image foreground
detection technique as well. Owing to the intentional incorporation of
error in SUM and CARRY for certain combination of inputs, the MSE has
been found to be predominant and its impact on PSNR is verified. Thus,
the work paved the way for efficient nanoelectronic implementation of
approximate computing applications utilizing memristors as memory as
well as circuit element. The proposed adder circuit can be used for
developing architectures such as Carry Select Adder, multipliers and
other arithmetic circuits. In addition, the proposed adder and sub-
tractor circuits can possibly be used as basic cell to build higher order
architecture using segmentation and cell replacement techniques and
the performance can be compared with our proposed work by deducing
the performance metrics.
Acknowledgement
Authors are indebted to the VIT management for extending their
simulation facilities to carry out this work.
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