UPI-41AH/42AH UNIVERSAL PERIPHERAL INTERFACE 8-BIT SLAVE MICROCONTROLLER we UPI-41: 6 MHz; UPI-42: 12.5 MHz m Pin, Software and Architecturally Compatible with all UPI-41 and UPI-42 Products m 8-Bit CPU plus ROM/OTP EPROM, RAM, 1/0, Timer/Counter and Clock in a Single Package 2048 x 8 ROM/OTP, 256 x 8 RAM on UPI-42, 1024 x 8 ROM/OTP, 128 x 8 RAM on UPI-41, 8-Bit Timer/Counter, 18 Programmable 1/0 Pins m One 8-Bit Status and Two Data Registers for Asynchronous Slave-to- Master Interface m DMA, Interrupt, or Polled Operation ‘Supported Fully Compatible with ail intel and Most Other Microprocessor Families. Interchangeable ROM and OTP EPROM Versions Expandable 1/0 Sync Mode Available Over 90 Instructions: 70% Single Byte Avallable in EXPRESS —Standard Temperature Range Intgligent Programming Algorithm —Fast OTP Programming Avallable In 40-Lead Plastic and 44- Lead Plastic Leaded Chip Carrier Package Type and N ‘The Intel UPI-41AH and UPI-42AH are general-purpose Universal Peripheral Interfaces that allow the designer to develop customized solutions for peripheral device control They are essential ‘slave"” microcontrollers, or microcontrollers with a slave interface included on the chip. Interface registers are included to enable the UPI device to function as a slave peripheral controller in the MCS Modules and iAPX family, as well as other 8-, 16-, and 32-bit systems. To allow full user flexibility, the program memory is available in ROM and One-Time Programmable EPROM (OTP). All UPI-41AH and UPI-42AH devices are fully pin compatible for easy transition from prototype to production level designs. seescedasosoadi ayoa8a-2 Figure 1. DIP Pin Contiguration 4-68 UPI-41AH UPI-42aH SSSS ELE 2roaes-a Figure 2, PLCC Pin Configuration November 1994 ‘Order Number 210399-008UPI-41AH/42AH 0080-1 Figure 3. Block Diagram UPI PRODUCT MATRIX OTP Programming | ioe EPROM oo Voltage _ 2K lS 256 = 2K S 256 = e742AH = 2K 256 12.5V 8041AH 1K = 128 = 8741AH = 1K 128 125V THE INTEL 8242 ‘As shown in the UPI-42 product matrix, the UPI-42, willbe offered as a pre-programmed 8042 with sev- ‘eral software vendors’ keyboard controller firmware. ‘The current list of available 8242 versions include keyboard controller firmware trom both Phoenix Technologies Ltd., IBM, and Award Software Inc. ‘The 8242 is programmed with Phoenix Technologies Ltd. keyboard controller firmware for AT-compatible systems. This keyboard controller is fully compatible with all AT-compatible operating systems and appli- cations. The 8242PC also contains Phoenix Tach: nologies Ltd. firmware. This keyboard controller provides support for AT, PS/2 and most EISA plat- forms as well as PS/2-style mouse support for either AT oF PS/2 platforms. ‘The Intel 824288 is programmed with IBM's key board controller firmware. The 8242BB provides an off the sheit keyboard and auxiliary device controller for AT, PS/2, EISA, and PCI architectures. ‘The 8242WA contains Award Software Inc. firm- ware. This device provides at AT-compatible key- board controller for use in BM PC AT compatible computers. The 8242WB contains a version of ‘Award Software Inc. firmware that provides PS/2 style mouse support in addition to the standard fea- tures of the 8242WA. “Contact factory for current code revision available in all versions of the 8242 product lines, 4.69UPI-41AH/42AH intel. Table 1. Pin Description pip [Puce symbot| Pin | Pin |type| Name and Function No. | No. vesto,| 1 | 2 | 1 | TESTINPUTS: Input pins which can be crecty tested using conditional branch rest: | 99 | 43 instructions FREQUENCY REFERENCE: TEST 1 (73) also functions as the event mer input (under software control). TEST 0 (To) is used during PROM programming and ROM/EPROM Voriication tis also used during Sync Mode to reset the instruction state to St and ‘synchronize the internal clock 1o PH1. See the Sync Mode Section. xtacs.| 2 | 3 | 1 [aNPUTS: inputs ora crystal, LC or en extemal timing signal to determine the internal xrac2 | 3 | 4 ‘oscilato frequency. Reset | «| 5 | 1 [RESET: inputusod to reset status fip-fops and to set the program counter to zero, RESET is also used during EPROM programming and verfication. ss 5 | & | 1 [SINGLE STEP: Singe stop input used in conjunction with the SYNC output to step the program through each instruction (EPROM). This shouldbe tied to + 5V when not used This pins also used to put tho device in Sync Mode by applying 12.5V tot es 6 | 7 | 1 [cet seLecr: chip solectinput used to select one UPI microcomputer out of several connected to a common data bus. EA 7 | 8 | 1 JEXTERNAL ACCESS: External access input which allows emulation testing and OM/EPROM vertication. This pin shouldbe ted low i unused. Ro & | © | 1 [READ:1/0 readinput which enables to master CPU to ead data and status words trom the OUTPUT DATA BUS BUFFER or status ropstr. ho @ | 10 | 1 |COMMAND/DATA SELECT: Address input used by the master processor to indi ‘whether byte transfers data (Ap = 0, F1 i reset) or command (Ag ~ 1, Fis at). Ag ~ 0 dung program and verity poration, Z wr 10 | 11 [1 | WRETE:1/0 writo input which enables the master CPU to write data and command words to the UPI INPUT DATA BUS BUFFER. sync [11 | 19 | 0 [ouTPUT CLOCK: Output signal wrien occurs once per UP instruction cycle. SYNC can be used as a strobo for oxtoral ercuty: tis also used to synchronize single step operation 1D9-07 [12-19] 14-21] 1/0 [DATA BUS: Tiree-stato, bdrectional DATA BUS BUFFER lines used to interface the UPI (aus) microcomputer to an 8-bit master system data bus. Py9-P17| 27-26] 90-23] 1/0 | PORT 1:6-bi, PORT 1 quasibidrectionall/O lines. Pjo-P17 access the signature row 26-38] [and security bit Pa9-Pr7|21-24| 24-27] 1/0 | PORT 2:0-bA, PORT 2 quasibidrectional I/O tines. The lower 4 bita(P2o-Paa)intertace 135-38] 39-42| | dvaetly tothe 8243 1/0 expander device and contain address and data information during PORT 4-7 access, The upper 4 bits (P24-Pzr) can be programmed o provide interupt ‘Request and DMA Handshake capability. Sofware control can configure Pay 2 Output ;Buttor Full (OBF) interrupt, Pas as Input Butler Ful (BF) interupt P2e as OMA Request (ORO), and Pz7 a8 OMA ACKnowledge (DACKY. PROG | 25 | 28 | 1/0 | PROGRAM: Mutituncton pin used asthe program pulse input during PROM programing ‘During I/O expander access the PROG pin acts as an address/data strobe tothe 8243. “This pin should be to hight unused voc | 40 | 44 POWER: + 5V main power supply pin oo | (26 | a8 POWER: + 5V during normal operation. + 12.5V during programming operation. Low owor standby supply pin, ves | 20 | 22 GROUND: Circuit ground potential 470intel. UPI-41AH and UPI-42AH FEATURES 1. Two Data Bus Butters, one for input and one for output. This allows a much cleaner Master/Slave protocol 2.8 Bis of Status ST] St6[ STs] St«] Fi | Fo] 8 | OBF D7 0s Ds D4 Dy Dz Dy Dp ST4-ST; are user definable status bits, These bits are defined by IOV STS, A” single byte, single cycle instruction. Bits 4-7 of the acccumu: lator are moved to bts 4~7 of the status rogster. Bits 0-3 of the status register are not affected. MOV STS, A_Op Code: 0H + [ololio]e]olo or Do 3. AD and WA are edge triggered. IBF, OBF, Fy and INT change internally after the traling edge of FO o WR wom VO 210080-6 UPI-41AH/42AH During the time that the host GPU is reading the status register, the UPI is prevented from updat- ing this register or 4.Po4 and Pos are port pins or Butter Flag pins which can be used to interrupt a master proces- sor. These pins default to port pins on Reset. If the “EN FLAGS" instruction has been exocut- ‘6d, P24 becomes the OBF (Output Butler Full) pin. ‘At written to Poa enables the OBF pin (the pin ‘outputs the OBF Status Bit). A "0" written to Pag disables the OBF pin (the pin remains low). This pin can be used to indicate that valid data is avail able from the UPI (in Output Data Bus Butter). It“EN FLAGS” has been executed, Pzs becomes the IBF (Input Butter Full pin. A" written to Pos ‘enables the IBF pin (the pin outputs the inverso of the IBF Status Bit, A “0” written to Pos disables the TBF pin (the pin remains low). This pin can be used to indicate that the UPI is ready for data. ta} DO ote onrennunr ntouesy || ED atm 2100805 Data Bus Buffer interrupt Capability [1A08 opcode om th lebPeLs 07 Do anUPI-41AH/42AH 5. Pog and P27 are port pins or DMA handshake pins for use with a DMA controller. These pins default to port pins on Reset H the “EN DMA" instruction has bean executed, Pag becomes the DRQ (OMA Request) pin. A “1 written to Pog causes a DMA request (ORC is acti- vated). DRQ is deactivated by DACKeAD, DACK*WR, or execution of the “EN DMA" in- struction It “EN DMA" has bean executed, P27 becomes the DACK (OMA ACKnowledge) pin. This pin acts as a chip select input for the Data Bus Butter rag: Isters during DMA transfers. unauan ono a] =o 1080-8 ~ DMA Handshake Capability EN DMA _Op Code: 05H rime |i) Z|] kv on |] 7 Do 6. When EA is enabled on the UPI, the program ‘counter is placed on Port 1 and the lower three: bits of Pot 2 (MSB = P29, LSB = Py). On the UPI this information is multiplexed with PORT DATA (S00 port timing diagrams at ond of this data sheet) 7. The 8741AH and 8742AH support the intgligent Programming Algorithm. (See the Programming Section.) APPLICATIONS Figure 6. 8048H-UPI-41/42 Interface 210280-9 Figure 7. UPI-41/42-6243 Keyboard Scanner 472 ~— sera 00 21008920 Figure 4, UPI-41AH/42AH Keyboard Controlleruu Figure 8 UPI-41AH/42AH 80-Column Mateix Printer Interface PROGRAMMING AND VERIFYING THE 8741AH AND 8742AH OTP EPROM Programming Verification In brief, the programming process consists of: acti- vating the program mode, applying an address, latching the address, applying data, and applying a programming pulse. Each word is programmed com- pletely before moving on to the next and is followed by a verification step. The following is a list of the pins used for programming and a description of their functions: Pin Funetion [ XTAL1 | 2Clock Inputs _ i Fresci_| initialization and Address Latching [Testo | Selection of Program or Verify Mode EA | Activation of Program/Venty Signature Row/Securty Bit Modes BUS | Address and Data Input Data Output During Verity Pao-22 | Address input Voo _, Programming Power Supply PROG | Program Pulse Input WARNING Irettemt to program a masocketed B741AH or 87424H ws resto ‘severe damage tthe par An rca. of a reper sockotod ars ‘ha appearance othe SYNC cots output Thock otha Sock may De uaed fo abla te progammer UPI-41AH/42AH ‘The Program/Verify sequence is: 1.08 = 5V, Voc = 5V, Voo = 5V, RESET = ov, ‘Ag = OV, TEST 0 = SV, clock applied or internal oscillator operating, BUS floating, PROG = 5V. 2, Insert 8741AH or 8742AH in programming socket 3. TEST 0 = OV (select program mode) 4. EA = 12.8V (active program mode) 5. Voc = 6V (programming supply) 6 iz 8 Vop = 12.5V (programming power) . Address applied to BUS and Pao_22 3. RESET = SV (latch address) 9. Data applied to BUS 10. PROG = SV followed by one 1 ms pulse to OV 11.TEST 0 = SV (verity mode) 412. Plead and verity data on BUS 13, TESTO = ov 14. Apply overprogram pulse 18. RESET = OV and repeat from step 6 16. Programmer should be at conditions of step 1 when 8741 AH or 8742AH is removed from socket Please follow the inteligent Programming flow chart {or proper programming procedure. Inteligent Programming Algorithm ‘The intgligent Programming Algorithm rapidly pro- ‘grams Intel 8741AH/8742AH EPROMS using an efti- Cient and reliable method particularly suited to the production programming environment. Typical pro- gramming time for individual devices is on the order of 10 seconds. Programming reliability is also en- sured as the incremental program margin of each byte is continually monitored to determine when it hhas been successfully programmed. A flowchart of the 8741AH/8742AH intgligent Programming Algo- rithm is shown in Figure 9. The Intgligent Programming Algorithm utilizes two different pulse types: initial and overprogram. Tho duration of the initial PROG pulse(s) is one millisoc- ‘ond, which will then be followed by a longer overpro- gram pulse of length 3X msec. X is an iteration coun- fer and is equal to the number of the initial one mil second pulses applied to a particular 8741AH/ 8742AH location, before a correct verify occurs. UP. to 25 one-milisecond pulses per byte are provided for before the overprogram pulse is applied. 473UPI-41AH/42AH intel . "ADDRESS = FIRST LOCATION “6 INCREMENT ADDRESS Device FAILED 21098912 Figure 9. Programming Algorithm 474 |intel. ‘The entire sequence of program pulses and byt verifications is performed at Voc = 6.0V and Vpp 12.5V. When the intgligent Programming cycle he boen completed, all bytes should be compared to the original data with Voc = 5.0, Vpp = 5V. Verity A verity should be performed on the programmed bits to determine that they have been correctly pro- grammed. The verity is performed with TO = SV, Vop = SV. EA = 12.5V, SS = 5V, PROG = 5V, AD = OV, and CS = 5v. SECURITY BIT ‘The security bit is a single EPROM call outside the EPROM array. The user can program this bit with the appropriate access code and the normal program- ming procedure, to inhibit any external access to the EPROM contents. Thus the user's resident program is protected. There is no direct external access to this bit. However, the security byte in the signature row has the same address and can be used 10 check indirectly whether the security bit has boon programmed or not. The security bit has no effect on the signature mode, so the security byte can always be examined. SECURITY BIT PROGRAMMING/ VERIFICATION Programming a. Read the security byte of the signature mode. Make sure it is OOH. UPI-41AH/42AH b. Apply access code to appropriate inputs to put the device into security mode . Apply high voltage to EA and Voo pins. 4. Follow the programming procedure as per the intgligant Programming Algorithm with known data on the databus. Not only the security bit, but also the security byte of the signature row is pro- ‘grammed. @. Verify that the security byte of the signature mode contains the same data as appeared on the data bus. (if DB0-DB7 = high, the security byte will contain FFH.) {. Read two consecutive known bytes trom the EPROM array and vorify that the wrong data are retrieved In at least one verification. If the EPROM can still be read, the security bit may have not been fully programmed though the se- ‘curity byte in the signature mode has. Verification Since the secutity bit address overlaps the address of the secunty byte of the signature mode, it can be used to check indirectly whether the security bit has been programmed or not. Therefore, the security bit verification is a mere read operation of the security byte of the signature row (OFFH = security bit pro- grammed; 00H = security bit unprogrammed). Note thal during the security bit programming, the reading of the security byte does not necessarily indicate that the security bit has been successfully pro- ‘grammed. Thus, itis recommended that two consec- utive known bytes in the EPROM array be read and the wrong data should be read at least once, be- Cause itis highly improbable that random data coin- cides with the correct ones twice. 475UPI-61AH/42AH_ SIGNATURE MODE The UPI-41AH/42AH has an additional 32 bytes of EPROM available for intel and user signatures and miscellaneous purposes. The 32 bytes are part tioned as follows: A, Test code/checkeum—This can accommodate up to 25 bytes of code for testing the internal ‘nodes that are not testable by executing from the ‘external memory. The test code/checksum is, present on ROMS, and OTPs. B. Intel signature—This allows the programmer to read from the UPI-41AH/42AH the manufacturer of the device and the exact product namo. It fa cilitates automatic device identification and will be present in the ROM and OTP versions. Loca- tion 10H contains the manufacturer code. For In- tel, itis 89H. Location 11H contains the device code. intel. The code is 43H and 42H for the 8042AH and OTP 8742AH, and 41H and 40H for the 8041AH and OTP 8741AH, respectively. The code is 44H for any device with the security bit sat by Intel C. User signature—The user signature memory is implemented in the EPROM and consists of 2 bytes for the customer to program his own signa- ture code (for identification purposes and quick sorting of previously programmed materials) D. Test signature—This memory is used to store testing information such as: test data, bin num- ber, ete. (for use in quality and manufacturing control. E. Security byte—This byte is used to chock whether the security bit has been programmed (soe the security bit section). The signature mode can be accessed by setting P10 = 0, P11-P17 = 1, and then following the programming ‘and/or verification procedures. The location of the various address partitions are as follows: Aree a Tesitomithedam | 0 en} ROWTP ‘ote : : Ta Satan ‘ot | RWOTP 2 User Sree ‘aia om 2 Test Signature 14H 15H ROM/OTP 2 Sez By ri or ‘ 476intel. SYNC MODE ‘The Sync Mode is provided to ease the design of multiple controller circuits by allowing the designer to force the device into known phase and state time. ‘The Sync Mode may also be utilized by automatic test equipment (ATE) for quick, easy. and efficient synchronizing between the tester and the DUT (de- vice under test). SYNC MODE TIMING DIAGRAMS: am SUA AAA prase 1 ——— === === = muster a ‘TIME STATE I 1 1 2 I a ! 4 | a RESET ov. Minimum Specitications ‘SYNC Operation Time, tgyno NOTE: ‘The rising and faling edges of TO should occur during low state of XTAL! clock. 5 XTAL 1 Clock cycles. Reset Time, tag = 4 tov. up! 1AH/42AH Sync Mode is enabled when 3B pin is raised to high voltage level of + 12 volts. To begin synchronize tion, TO is raised to 5 volts at least four clock eycles after SS, TO must be high for at least four X1 clock ‘cles to fully reset the prescalor and time stato generators. TO may than be brought down during low state of X1. Two clock cycles later, withthe rs: ing edge of Xi, the device enters into Time State 1, Phase 1. 5S is then brought down to 5 volts 4 clocks later attor 0. RESET is allowed to go high § tC (75, clocks) later for normal execution of code. 210309-20 arrACCESS CODE ‘The following table summarizes the access codes required to invoke the Sync Mode, Signature Mode, and the Security Bit, respectively. Also, the programming and verification modes are included tor ‘comparison. ‘Access Code Modes Contra! Signals Data Bus aa aa ‘To [Rst|ss[EA]PROG| Von |Veclo 1 2 3 4 § 6 7/01 2/01234567| Programming [0 | © | + [Hv] 1 |Voou| Vcc ‘Adress ‘Addr Jay ay X XX K XX Mode © [+] [avy ste [Voonl Veo! Data in ‘Ade Wveritcation [0 | 0 |1|Hv|_ 1 | Voc|Vec| ‘Address ‘Addr Jag ay X XX x x x{ Mode aft [a fowl [voc [veo] Data Out ‘Addr [SyncMode (STB! 0 [uv[o| x |Voc|Veclx x x x x x x x|xxx|x xXXxXXxX High| [Signature] Prog]_o | 0 | 1 [HV] + |Voon|Vco| Addr (S00 SigMode Tabi) [oo of0 111 1xxt ode o | + [4 [av] st |Vooul Voc! Data in ovo verty| 0 | 0 [1 [Hv 1 |Vcc|Voc| Addr (s00Sig Mode Tabiey [0 0 0 tft [afew a [vee [vec Date Out 000 {Security | Prog]_o | 0 [1 [Hv] + |VooulVoo| Address O00 [eiveyie 0 [+ [1 [eo] st8 [ool veo Data in O00 verty| 0 [0 [1 [rv] + | vcc|voc Address O00 +L Ts fevl 1 [vee [vee Data Out O00 NoTEs: 1.9 = 0.0F 1; a) = 0.0F 1. ap must = ay ABSOLUTE MAXIMUM RATINGS* NOTICE: This is a production data sheet. The specifi- cations are subject to change without notice, Ambiont Temperature Under Bias ....0°C to +70°C. Storage Temperature . Voltage on Any Pin with Respect to Ground Power Dissipation 65°C to + 150°C -05Vto +7V 1.5W “WARNING: Stressing the device beyond the “Absoluie Maximum Ratings” may cause permanent damage. These are stress ratings only. Operation beyond the “Operating Conditions” is not recommended and ex. tended exposure beyond the “Operating Conditions” ‘may attoct device reliebilly D.C. CHARACTERISTICS 1, = 0°C to + 70°C, Voc = Vop = +5V 10% symbol Parameter UPLATAH/S2AH | unity Min | Max Vi.___| Input Low Voltage (Except XTAL1, xTAL2,AESET)| 05 | 08 | V Vier __| Input Low Voltage (XTAL!, XTAL2, RESET) os | o6 | v Vin | Input High Voltage (Except XTAL1, XTAL2, RESET) | 20 | Vcc | V Vin | Input High Voltage (XTAL1, RESET) as | vec | V Vine | Input High Voltage (XTAL2) 22 | veo | Vv Vor | Output Low Voltage (Op-O7) 045 | Vv [ig = 20mA 4.78intel * UPI-41AH/42AH D.C. CHARACTERISTICS 1, = 0°C to + 70°C, Voc = Voo = +5V + 10% (Continued) ‘Symbol Parameter UPIATAH/AZAH | rita) Notes min | Max Nour [Output Low Voltage (PoP 37, PooPo7 |_| 04s |v fou = tema [Vor [Output Low Voltage (PROG) 045 | Vv fin = 10mA Vou (Output High Voltage (Dp-D7) V_ flow = —400 pA Vout [Output High Voltage {All Other Outputs) 24 ~ lon = —50 nA in Input Loakage Current To, Ts, RD. WR, OS. Ao. EA) #10 | uA [vss 5 Vin 5 Veol lor, [Output Leakage Curent (0p-Dp. High Z State) 210 | HA [Veg +048 = Vout § Voc tu Low Input Load Current (PyoP 17, P2oP27) 03 mA [Vi = 0.8V lus Low input Load Current (RESET, SS) 02 | ma |vy = 08v loo Von Supply Curent 20_| mA [Typical = 6 ma loc * top _|Total Supply Curent 195 | mA | Typical = 80 ma lao Standtby| Power Down Supply Gurrent 20_| mA [Typical = 6 ma Ie Input Leakage Curent (Py9-Py7,P0-Pa2) 100_| wA |Vin = Voc [Cin Input Capacitance 7 30_| oF [ta = 2500 0 _[vOCapactance 20 | oF [ta = 25 4a | wo} 1. Samplod, not 100% tested D.C. CHARACTERISTICS—PROGRAMMING Ta = 25°C 15°C, Voc = BV £0.25V. Voo - 12.5V £0.5V Symbol Parameter ia ee] Vpou - po Program Voltage High Level 12 13, vay oo. Vo Votage Low Love 478 | a8 v vn PROG Progam Votagotightew | 20 35 Ve. | PROG Votago Low Level osm arose |e Vea Input High Votago for EA reo | erro eA Vent EA Vliage Low Love stat aaeos v loo Voo High Votage Suny Garon 300 | mA [tes EA igh Voago Sopoy Garon 10 mA ores 1. Voltages over 13V applied to pin Vpg will parmanantly damage the device, 2. Veaw must be applied to EA before Voy, and removed after Vo. 3. Voc must be appliod simultaneously or betore Vog and must be removed simultaneously or after Voo- I 4.79UPI-41AH/42AH A.C. CHARACTERISTICS Ty = 0°C to + 70°C, Vsg = OV, Voc = Voo = +5V +10% DBB READ ‘Symbol "Parameter Min Max Unite tan CS, Ag Setup to RD | 0 a tha (CS, Ag Hold After RD T ° ns tan AD Pulse Width 160 ns. tao GS, Ag to Data Out Delay as tao AD | to Data Out Dolay o ns tor AD f to Data Float Delay 85 ns BB WRITE Symbol Parameter Min Max Units taw 6S, Ag Setup toWR J ° as twa CS, Ag Hold Atter WR T 0 ns ww WA Pulse Width 160 ns tow Data Setup to WR T 130 ns two Data Hold After WR T ° ns cLock ‘Symbol Param Min Max Units {cy (UPI-41AH/42AH) Cycle Time 12 920 st) toy¢ (UPI-41AH/42AH) Clock Period 80 613 ns tewe Clock High Time 30 ns tow. Clock Low Time 30 ns. ta Glock Rise Time 10 ns te Clock Fall 10 ns NoTE: Tetey = 15/10CTALY A.C. CHARACTERISTICS DMA ‘Symbol Parameter Min Max Unite tace DACK to WR or RO. ns toac RD or WR to DACK 08. taco DACK to Data Valio 430 ns. tora RO of WR to DAQ Cleared 110 st) NoTe: 1.0. = 150 pF 4-80intel. A.C. CHARACTERISTICS—PROGRAMMING Ta = 28°C #5°C, Voc (8741AH/8742AH ONLY) 3V £0.25V, Vop, = +5V +0.25V, VooH = 12.5V +0.5V Symbol Parameter min Max Unite taw ‘Address Setup Time to RESET T ‘toy twa ‘Address Hold Time After RESET T ‘icy tow Data in Setup Time to PROG | ‘toy Z two Data in Hold Time After PROG T ‘Aioy tow Initial Program Pulse Width 0.95 1.08; mat?) thw Test 0 Setup Time for Program Mode aicy wr Test 0 Hold Time After Program Mode toy too Test 0 to Data Out Delay sty ww RESET Pulse Width to Latch Address ‘toy tote | __PROG Rise and Fall Times 06 100 Bs. toy ‘CPU Operation Cycle Time 25 3.75 as the RESET Sotup Time Before EAT ‘toy torw_ Overprogram Pulse Width 2.85 78.75 ms(2) toe EA High to Vop High Hoy Nores: 1. Typical nial Program Puls wath tolerance = 11 ms + 5%. 2. Ths vatiton isa function of tho eration counter value. X 5. TEST Os gh, tog can be tiggered by RESET T A.C. CHARACTERISTICS PORT 2T, = 0°Cto +700, Voc = +5V 10% ‘Symbol Parameter tow) [ Min | Max | Unite tor. Port Control Setup Before Falling Edge of PROG | 1/15tcy~28 | 55 na) tec. Port Control Hold After Falling Edge of PROG | 1/10 toy 125 ns) ter PROG to Time P2 Input Must Be Valid 8/15 toy - 16 650 ns(t) ter Input Data Hold Time 0 | 150 | ns op Output Data Setup Time Oley _| 250 net) to. ‘Output Data Hold Time ~ 1/10 tey—-80 | 45 ns) tp. PROG Pulse Width 7 6/10 toy 750 ns NoTes 1. = 806 2G = 20pF 3 toy = 125 ps 481UPI-41AH/42AH A.C. TESTING INPUT/OUTPUT WAVEFORM \euT/ouTeUT ESTING LOAD CIRCUIT ae 2ro2eo-14 uF ayna9a-s DRIVING FROM EXTERNAL SOURCE-TWO OPTIONS. LC OSCILLATOR MODE “ue =] : ayoma-16 20m Figo and Fall Timas Should Not Excood 10 ne oss tore toga Needed t0 Eneure Vig = 29 TTL Greuity is Uso CRYSTAL OSCILLATOR MODE Lc NOMINAL 1 45H 20pF 52MKe ed 120K ZopF 32Mne tte fis | cr = $+ a6e ee tl. cop = 5-105F TL fos Boe 210380-18 en © Should be Approximatly 20 pF, rcuding Stay Capactarco 4-82 cee Ly [ewe 003-19 1 Spr STRAY Sor) C2 (CRYSTAL + STRAY) 8 oF (6320-20 pF INCLUDING STRAY Crystal Series Rasistance Shou tbe Less Than 300? at 12.5 MHZ,intel . UPI-41AH/42AH WAVEFORMS, READ OPERATION—DATA BUS BUFFER REGISTER WRITE OPERATION—-DATA BUS BUFFER REGISTER CLOCK TIMING 210090-22 | 4-83UPI. }1AH/42AH intel. WAVEFORMS (Continued) COMBINATION PROGRAM/VERIFY MODE roca +} — verry f+ oan = 82. ie otene vet259) ae wsM / \ on : ea wo 80 ™ “ aN | wow vento) vO ae oo X Cle .com 1 saat) = SET 21098923 ores: 1. Ag must be held low (OV) during progrem/venty modes. 2. For Vi Vint. Vit. Vint, Voom, and Vo. please consult the D.C. Characteristics Table. 3. When programming the B741AH/8742AH, @0.1 wF capacitors required across Vpp and ground to suppress spurious voltage transients which can demage the device. VERIFY MODE oer Came Xa) 210989-20 1. PROG must float it EA is low. 2. PROG must float or — SV whon EA is high. 3. Pyo-Py7 = 5V oF must float. 4. Paq-Pa7 = 5V oF must float 5. Ap must be held low during programming/verty modes, 484 |intel ° UPI-41AH/42AH_ WAVEFORMS (Continued) - , ee .— ~[-— 21020925, nee S\N EXPANDER PORT PORT TIMING DURING EXTERNAL ACCESS (EA) f sync Pro vr OX re Xa Xe Paoz. a (On the Rising Edge of SYNC and EA is Enabled, Port Data is Valid and can be Strobed. On the Trang Edge of Syne the Program Counter Contents are Available | 485 pons 4 |UPI-41AH/42AH_ intel. Table 2. UPI Instruction Set Moemonle Beseription _Byten cycles] [_Mromonle Description Bytes Cyclon ACCUMULATOR DATAMOVES AODAAY AddrogstertoA 11 | MOVALRY MovorogstorioA tt ADDAeR —Adddolamemary =| | |MOVAC@R® — Mowodeamomay 1 OA ea ADDA edna Aadimmodeoiod 22 NoveinmedatowA 22 AOOCA RY AdgroguertoA Tt Nove Awregna tt ‘ath cary Nowe Atwdate 1 ADOCA. AY Aaddataamory 1 renery ‘oawitveny Mov, edala Mowemmedaieto 22 AOOCA. #éala Aadmmedso = 22 vouesr Neale Wovens, Noveimmedaisto 22 AMLARe — ANOrgnDA 1 oate deta memory ANLA@RY —-ANDatamemoy 1-1 | |MOVA.PSW Mowe PSA = 1 eA MovesW.A Mmoawesw 1 ANLA,¢data ANDmedaored 2 2 | |KCHAR Exchangeaand = 1 CHAR ORngserek ft ropelor OALA cer ORgoamemey 1 | XGHA@RY EuchangoAand = tt eA cou renoey ORLA, edea ORimmodatctoa 2-2 || XCHOA@RY ExchangoagtotA tt XRLAR Bumeonrgs Tt ondrogens wea MOvPA@A Mowlwawon 12 NALA RY ErcwweORGeta 1 cmertpage amar) eA MOVF.A8A Mowiohton 12 HALA eanta CrcuueORinme 22 peo diate to A ‘TIMER/COUNTER: INCA Increment ' 1 MOV A, T Read Timer/Counter 1 1 DECA Oscroment A 2 1 MOV T. A Load Timer/Counter 1 1 GRA Gear A ' 7 STRTT ‘Start Timer 1 1 oA Compbmeta ¢ tf | STATE Sarto pg O&A DecmalAchwta 1 || Sropront Stop imevGounter 1 SWAPA—Swapnanienata 1 | [STORTONT. Stop Tina/Co 7 RUA Rowio Aton 4 ne RLCA Rotate Aloft through = ! DIS TNT Disable Timer/ 1 1 cony Couto erupt Aaa fata Arent 14 RRC A Rotate A right 1 1 CONTROL ae ENDMA, —EnabloOMAHand. tt ny shat Lies WNPUT/OUTPUT ENI Enable IGF Interrupt 1 1 APD iputponto to OUTLPp.A Output Ato port 1 2 ost Diable IBF inter- 1 4 AMLPD sania -ANDmmoseioio = 2 at ont ENFLAGS Enable Master 1 1 ORL Pp. eden Onmmadatcto = 2 nae Mas on SELROD ——Selctrogata 14 WADE putes, = tt coon clear IBF SELRBY ‘Select register 1 1 ouross. A Oupaaioose, = 1 — pire aie MOV STS, A ‘Ag-A7 to Bits 4-7 of 1 1 bed He Operation. : : a REGISTERS a INCRT Weeremantgltor tt MONDA.P pal Expr 12 | YNGer — tnerementate tt i foc wowra arose = 1 2 | lecay ——_peseeaegitee : ANLDPp|A AND ATOEmpendor 12 pon ORLDPP,A OR Ato Expander 4.86 portintel. ‘Table 2. UP! Instruction Set (Continued) Mnemonic Description Bytes Cycles ‘SUBROUTINE CALLeddr — Jumptosubroutne = 22 RET Retun 1 2 RETR Rrotum and restore 1 2 status FLAGS unc (Clear Carry 1 1 CPL Complement Cary 1 1 CLR FO (Clear Flag 1 1 PL FO GompiomentFlagd 1 1 cLRFI Clear F1 Flag 1 1 CPLA Complement Fi Flag 1 1 BRANCH AMP addr Jumpunconditinal © 22 UMPP.@A Jump indirect 1 2 DINZRr, addr Decromentregistor = 22 and jump WCador sumponCary=1 22 SNCaddr — umponGary= 0 2 Wadce Jump on & Zero ea NZ addr JumponAnot2Zer0 = 22 UT0add §— umpon To ~ 1 2 2 INTO addr Jump on TO = 0 2 2 UTVadde Jump on T1 ead NTI addr Jumpon Tt = 0 2 2 JFOaddr = JumponFOFlg=1 2 9 2 JFiaddr = JumponFtFlag=1 2 © 2 STF addr JumponTimerFlag 22 = 1, Clear Flag LINIBF addr Jump on IBF Fag 2 2 =o JOBF addr JumponOBFFlag = 2 1 JBbadd —JumponAccumula = 2 for Bit == UPI-61AH/42AH 4.87