DSP Processors - Lecture 7 - Part2 Fundamentals: H05H4, H05E7 Goal: Skiing Down A Mountain

DSP Processors – Lecture 7 – part2
Fundamentals
Ingrid Verbauwhede
Departement Elektrotechniek, afdeling ESAT/COSIC
iverbauw@esat.kuleuven.be
1
H5H4, Spring 2008, Ingrid Verbauwhede, les 7-2
H05H4, H05E7 goal: Skiing down a mountain
• DSP = highly multiplexed
SPW, Matlab, C++ Specification
pipelining, unrolling Algorithm Transformations
Memory Transformations
loop merging, compaction
and Optimizations
40 bit accumulator Floating-point to Fixed-point
Special Retargetable DSP DSP-

ASIC RISC
Purpose coprocessor processor RISC
2
1
References
• The origins:
• E.A. Lee, “Programmable DSP Processors,” Part I, IEEE ASSP
magazine, October 1988, pg. 4-19.
• Part II, IEEE ASSP magazine, January 1989, pg. 4-14
• Good overview:
• P. Lapsley, J. Bier, A. Shoham, E.A.Lee, “DSP Processor Fundamentals:
Architectures and Features,” IEEE Press, 1998.
• Domain specific processor:

•I. Verbauwhede, “Low Power DSPs”, Chapter 19 in Low Power Electronics
and Design, Edited by Christian Piguet, CRC Press, 2005.
3
DSP Processor Fundamentals
Processor Components:
Data Path Interconnect

Processing Processing
Unit Unit
Instruction Memory
Processing Management
Unit Unit
4
2
Von Neumann machine
One memory space
Processor
Core mpy ALU
Address Bus
Data Bus
Memory
5
FIR implementation
x(n-1)
x(n) -1 -1 -1
Z Z Z
x(n-(N-1))
(50 TAPS)
N-1 c(0) c(N-1) X
Σ c(i)
X X X
y(n) = x(n-i)
i=0
y(n)
+ + +
y(0) = c(0)x(0) + c(1)x(-1) + c(2)x(-2) + . . . + c(N-1)x(1-N);

y(1) = c(0)x(1) + c(1)x(0) + c(2)x(-1) + . . . + c(N-1)x(2-N);
y(2) = c(0)x(2) + c(1)x(1) + c(2)x(0) + . . . + c(N-1)x(3-N);
. . .
y(n) = c(0)x(n) + c(1)x(n-1) + c(2)x(n-2)+ . . + c(N-1)x(n-(N-1));
Execute row by row

6
3
FIR on Von Neumann
Assume Von Neumann has multiply and accumulate instruction

(not necessarily the case)
Assume also that pipelining allows to execute the multiply and accumulate
in parallel with the read or write operations.
Then one tap needs 4 cycles:
1. read multiply-accumulate instruction
2. read data value from memory
3. read coefficient from memory
4. write data value to the next location in the delay line
(because for the next sample, all values are shifted by one location)
Memory bandwidth is crucial !!!
7
Basic Harvard Architecture

Separate data memory from program memory!
Program Data
Memory Memory
Instruction
Multiply 16 x 16 mpy
Processing
Unit Accumulate
ALU
8
4
Example 1: TMS320C10 (1982)
Data RAM Program ROM

144 x 16 1.5K x 16 160/200ns Instruction
A (11-0)
cycle time
4K word external
PA (7-0)
D (15-0) (A 2-0, D 15-0) address reach
CPU 60 general purpose and
16-bit T-register DSP specific instructions
16-bit Barrel I/O Ports
16 x 16 Multiply 8 x 16
Shifter (L) Single cycle multiply
32-bit P-register
32-bit ALU 16-bit Barrel Shifter
32-bit Accumulator
External interrupt and
ShiftL (0,1,4)
polled input pins
2 Auxiliary Regs
Four Level H/W Stack Eight 16-bit I/O ports
Status Register
40-pin DIP/44-pin PLCC
Courtesy: Texas Instruments

9
TMS320C1x Example - Sum of Products
Data Bus Compute Y = AX1 + BX2 + CX3 + DX4
ZAC ACC=0
T (16)
LT X1 T=X1
MPY A P=AX1
Multiplier
LTA X2 ACC=AX1;T=X2
MPY B P=BX2
P (32) LTA X3 ACC=AX1+BX2;T=X3
MPY C P=CX3
MUX LTA X4 ACC=AX1+BX2+CX3;T=X4
MPY D P=DX4
APAC ACC=AX1+BX2+Cx3+DX4
ALU (32)
SACH Y1 STORE 32-BIT RESULT
ACC (32) SACH Y2 AT LOCATIONS Y1, Y2
• 50 taps = 103 cycles

• = Program ROM of 103 instructions
10
5
TMS320C1x Memory and Buses
Data Program Single cycle reads

RAM
and writes
ROM EPROM OTP
256x16 8Kx16 Modified Harvard
Architecture
16 8 16 16 - Separate Program
Program Address and Data Buses
A15-A0,
PA2-PA0
- "Bridge" between
Program and Data
Program Data Space
D15-D0
16
MUX
DEN Up to 8K words of
Data Data on-chip Program ROM
MEN
WE
4K words of
Data Address EPROM
16 16
and OTP available
16 8
Up to 64K words
Program Control, CPU External Program
Instruction Register Memory
Courtesy: Texas Instruments 11

Modified Harvard Architecture
Program Data
Memory Memory
Instruction
Multiply 16 x 16 mpy
Processing
Unit Accumulate
ALU
Program bus to get instruction

Or to get coefficients (often stored in ROM)
12
6
Same FIR: 53 cycles, 3 prog words
x(n-1)
x(n) -1 -1 -1
Z Z Z
x(n-(N-1))
N-1 (50 TAPS)
y(n) =
Σ c(i) x(n-i) c(0) X X X c(N-1) X
i=0
y(n)
+ + +
Single Cycle Multiply - Accumulate!
TMS320C10 TMS320C25
LT LTD RPTK 49 LT
DMOV MPY MACD DMOV
APAC LTD APAC
MPY 53 Cycles MPY
LTD 3 Words Prog Memory
..
. 100 Cycles
MPY
100 Words Prog Memory
13
Example: MACD
MACD = Multiply by Program Memory and Accumulate with Delay

(Instruction is still present in current C54x and C55x)
MACD Smem, pmad, src

Smem = data memory
pmad = program address
src = accumulator (A or B)
Executes (simplified):
(Smem) x (Pmem(at location pmad)) + src -> src ; = multiply – accumulate

(Smem) -> Treg ; load data in Treg register
(Smem) -> Smem +1 ; load data in next mem loc.
(pmad) +1 -> pmad ; increment program address
pointer
When executing with a repeat instruction, takes one cycle

14
7
Single Cycle MAC
TMS320C2x Multiplier/ALU
Program Bus
Single Cycle 16x16 bit
Data Bus 16
16 16 16 Multiply yielding a
Left T Register (16) MUX 32-bit product
Shifter 16
(0-16) 16
Multiplier (16x16)
32 Supports simultaneous
P Register (32) Program and two Data
32
Left Shifter (0-16) Operand acquisition
32 32
MUX Supports simultaneous
32
32
ALU and Multiplier
Arithmetic Logic Unit (ALU)
32 operations
C Accumulator Register (32)
32 0-16 bit Left Post-Shifter
16
Left Shifter (0-7)
Courtesy: Texas Instruments 15
TMS320C2x Enhancements Over C1x
1986:
80/100ns instruction cycle time
Simultaneous single-cycle Multiply/ALU operations
Zero overhead repeat single instruction
64K words of off-chip Data RAM
Optimizing ANSI C-Compiler
544 words of on-chip Data/Program RAM
Multiplier Post Shifter and enhanced Accumulator Post Shifter
74 additional instructions
- Single-cycle MAC and zero overhead repeat
- Long immediate and carry bit support
- More logical and conditional branch operations
- Data block move support
Bit reversed addressing for FFTs
Eight auxiliary registers
Hardware wait states
DMA support
Idle and Powerdown Capability
Courtesy: Texas Instruments

16
8
Other memory configurations
Program Data Data Multiple data memories

Memory Memory Memory e.g. Motorola 56000:
- program memory
- X memory
- Y memory
Program Program/ Data Data
Cache Memory Memory
Instruction cache
• single instruction RPTK (repeat in TMS320C2x))
• a few instructions (up to 15 in AT&T 16A)
• ALWAYS under programmers control!
• ALWAYS known at compile time!
17
Memory configurations (more)
• Very cost sensitive applications

• all memory ON chip (even in the 80’s!)
• multiple small memories instead of unpredictable memory cache hierarchy
• program memory mostly ROM (now Flash Memory)
• Programmer decides the distribution of arrays over the memories
to make sure that the two parallel reads are from different memory banks!
• More fancy stuff:

• special instructions to move samples in a delay line
• circular buffers for delay lines
18
9
Block Diagram (C54x)
• Memory Access
– 4 internal bus pairs
– C,D for data read
– E for data write
– P for program
• Others
– 2 40-bit Accum.
– 40-bit Barrel shifter
– 40-bit ALU
– 17bx17b multiplier
and 40b dedicated
adder perform a
non pipelined
single-cycle MAC
19
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DSP Processors – Lecture 7 – part2

Departement Elektrotechniek, afdeling ESAT/COSIC

H05H4, H05E7 goal: Skiing down a mountain

• DSP = highly multiplexed

SPW, Matlab, C++ Specification

pipelining, unrolling Algorithm Transformations

40 bit accumulator Floating-point to Fixed-point

Special Retargetable DSP DSP-

• Domain specific processor:

DSP Processor Fundamentals

Data Path Interconnect

y(0) = c(0)x(0) + c(1)x(-1) + c(2)x(-2) + . . . + c(N-1)x(1-N);

Execute row by row

Assume Von Neumann has multiply and accumulate instruction

Memory bandwidth is crucial !!!

Basic Harvard Architecture

Data RAM Program ROM

Courtesy: Texas Instruments

TMS320C1x Example - Sum of Products

Data Bus Compute Y = AX1 + BX2 + CX3 + DX4

ACC (32) SACH Y2 AT LOCATIONS Y1, Y2

• 50 taps = 103 cycles

Data Program Single cycle reads

Courtesy: Texas Instruments 11

Modified Harvard Architecture

Program bus to get instruction

Single Cycle Multiply - Accumulate!

MACD = Multiply by Program Memory and Accumulate with Delay

MACD Smem, pmad, src

(Smem) x (Pmem(at location pmad)) + src -> src ; = multiply – accumulate

When executing with a repeat instruction, takes one cycle

TMS320C2x Enhancements Over C1x

Courtesy: Texas Instruments

Program Data Data Multiple data memories

Memory configurations (more)

• Very cost sensitive applications

• More fancy stuff:

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