Design and Implementation of FPGA - Digital Based

PID Controller

Michal Kocur, Stefan Kozak, Branislav Dvorscak

Faculty of Electrical Engineering and Information Technology
Slovak University of Technology in Bratislava
Bratislava, Slovakia
{michal.kocur, stefan.kozak, branislav.dvorscak}@stuba.sk

Abstract² The main aim of this paper is to design an effective functional simplicity, and the ease with which engineers can
realization of digital PID control algorithms using field- implement it using current computer technology. Proportional-
programmable gate array (FPGA) technology. The proportional± integral-derivative (PID) controllers are the most adopted
integral±derivative (PID) control methods and algorithms are one controllers in industrial settings because of the advantageous
of the most common types of effective feedback controllers that are cost/benefit ratio they are able to provide. Despite their long
used in automatic control in many industrial processes. PID history and the know-how gained from years of experience, the
controller has been widely used in many different areas, such as availability of microprocessors and software tools and the
power systems, drives control, automotive mechatronics, increasing demand for higher product quality at reduced cost
aerospace, process control, and robotics. Implementation of PID
have stimulated researchers to devise new methodologies to
control algorithms has gone through several stages of realization,
improve their performance and make them easier to use.
from early mechanical, electrical and pneumatic designs to
microprocessor-based systems. Recently, field-programmable Practical PID Control covers important issues that arise when a
gate arrays (FPGAs) have become an alternative solution for the PID controller is to be applied in control practical industrial
realization of digital control algorithm systems, which were processes.
previously dominated by general-purpose microprocessor The main reason of the popularity of PID controller is that
systems. In comparison with convention PID realization, FPGA- this controller combines two important features sought by
EDVHGFRQWUROOHU¶VUHDOL]DWLRQRIIHUDGYDQWDJHVVXFKDVKLJKVSHHG control engineers:
complex functionality, and low power consumption. Another
advantage of FPGA-based platforms is their capability to execute x simplicity of the control law and easy implementation in
concurrent operations, allowing parallel architectural design of continuous-time or digital-time form into microcomputer,
different digital controllers system. In the propose paper we PLC or as hardware FPGA controller realization. (FPGA - is
demonstrate of the one application of hardware and software an acronym for Field Programmable Gate Array).
module development for the application and realization of digital
PID control algorithm for dynamical systems with fast dynamics. x robustness properties ensures the stability and high
We successfully implemented verified and analyze the FPGA PID performance under the changes of process parameters of the
control algorithm realization for high speed DC motors using controlled processes. Robustness, reliability, steady state and
FPGA technology (Spartan - 6 FPGA Family of company Xilinx) the shaping of the transient response are the most important
which delivers an optimal balance of low risk, low cost, and low issue. There are several form of the used industrial controllers
power for this applications. are of standard PID type (in continuous and/or digital form).
For practical implementation, only 10-20 basic algorithms are
Keywords—digital controller;PID control; DC motors used being modified according to the used processor type,
plant dynamics, time delays, etc.
I. INTRODUCTION ,QWKHUHFHQW\HDUVWKHVSHFL¿FDWLRQVIRUFRQWUROV\VWHPVKDV
grown to include a certain degree of intelligence. They vary
The vast majority of automatic control loops in the process IURPVSHFL¿FDWLRQVUHTXLULQJFHUWDLQDPRXQWRIIDXOWWROHUDQFH
industries (90%) still rely on various forms of the ubiquitous to operating under varying operating conditions. These systems
PID controller which has been commercially available for over must also be capable of intelligent sensor selection, remote
70 years. [1] For many batch processing operations, process monitoring and operation and must be capable of implementing
control is achieved via infrequent manual adjustments by plant sophisticated control algorithms that require adaptation. Hence
operators. LQRUGHUWRPHHWWKHVHVSHFL¿FDWLRQVRQHKDVWROook at a new
Proportional integral derivative (PID) control is the most approach in terms of either hardware software co-design or
commonly used control algorithm in the industry today. PID UHFRQ¿JXUDEOHKDUGZDUH OLNH )3*$WKDWDOORZ VXFKD W\SHRI
FRQWUROOHU SRSXODULW\ FDQ EH DWWULEXWHG WR WKH FRQWUROOHU¶V hardware/software co-design to take place. By systematically
effectiveness in a wide range of operation conditions, its partitioning the system; functionality requiring large amounts

233
978-1-4799-3528-4/14/$31.00 ©2014 IEEE
oI UHFRQ¿JXUDWLRQ FDQ EH JLYHQ VXFK NLQG RI UHVRXUFHV RQ DQ Their difference between u(k) and u(k-1) is then:
FPGA; there by ensuring that the above mentioned objectives
are met. ‫ݑ‬ሺ݇ሻ െ ‫ݑ‬ሺ݇ െ ͳሻ ൌ
் ்
ܲ ቄ݁ሺ݇ሻ െ ݁ሺ݇ െ ͳሻ ൅ ݁ሺ݇ െ ͳሻ ൅ ವ ሾ݁ሺ݇ሻ െ ʹ݁ሺ݇ െ ͳሻ െ ݁ሺ݇ െ ʹሻሿቅሺͶሻ
There are two approaches for implementing of control ்೔ ்

systems using GLJLWDOWHFKQRORJ\7KH¿UVWDSSURDFKLVEDVHGRQ

software which implies a memory-processor interaction. The The recursive control output u(k) is computed as:
memory holds the application program while the processor
fetches, decodes, and executes the program instructions. ‫ݑ‬ሺ݇ሻ ൌ ‫ݑ‬ሺ݇ െ ͳሻ ൅  ‫ݍ‬଴ ݁ሺ݇ሻ ൅ ‫ݍ‬ଵ ݁ሺ݇ െ ͳሻ ൅  ‫ݍ‬ଶ ݁ሺ݇ െ ʹሻ 
Programmable Logic Controllers (PLCs), microcontrollers,
microprocessors, Digital Signal Processors (DSPs), and general where
purpose computers are tools for software implementation. On
the other hand, the second approach is based on hardware. Early ்
‫ݍ‬଴ ൌ ܲ ቀͳ ൅  ೏ ቁ‫ݍ‬ଵ ൌ െܲ ቀͳ െ 
்
൅ʹ
்೏
ቁ‫ݍ‬ଶ ൌ ܲ
்೏
 
் ்೔ ் ்
hardware implementation is achieved by magnetic relays
extensively used in old industry automation systems. It then
If is used only discrete PI controller is control output computed
became achievable by means of digital logic gates and Medium
as:
Scale Integration (MSI) components. When the system size and
FRPSOH[LW\LQFUHDVHV$SSOLFDWLRQ6SHFL¿F,QWHJUDWHG&LUFXLWV
(ASICs) are utilized. The ASIC must be fabricated on a ‫ݑ‬ሺ݇ሻ ൌ ‫ݑ‬ሺ݇ െ ͳሻ ൅  ‫ݍ‬଴ ݁ሺ݇ሻ ൅ ‫ݍ‬ଵ ݁ሺ݇ െ ͳሻ 
manufacturing line, a process that takes several months, before
it can be used or even tested [2][4])3*$VDUHFRQ¿JXUDEOH,&V where
and used to implement logic functions. Early generations of
்
FPGAs were most often used as glue logic which is the logic ‫ݍ‬଴ ൌ ܲ‫ݍ‬ଵ ൌ െܲ ቀͳ െ  ቁ 
்೔
needed to connect the major components of a system. They
were often used in prototypes because they could be For implementation of the PID algorithm for FPGA is
programmed and inserted into a board in a few minutes, but they necessary to decompose (5) into simple arithmetic operations:
GLGQRWDOZD\VPDNHLWLQWRWKH¿QDOSURGXFW7RGD\¶VKLJK-end
FPGAs can hold several millions gates and have some ݁ሺ݇ሻ ൌ ‫ݓ‬ሺ݇ሻ െ ‫ݕ‬ሺ݇ሻ
VLJQL¿FDQWDGYDQWDJHVRYHU$6,&V7KH\HQVXUHHDVHRIGHVLJQ ‫݌‬଴ ൌ ‫ݍ‬଴ ‫݁ כ‬ሺ݇ሻ
lower development costs, more product revenue, and the
opportunity to speed products to market [3]. At the same time ‫݌‬ଵ ൌ ‫ݍ‬ଵ ‫݁ כ‬ሺ݇ െ ͳሻ
they are superior to software-based controllers as they are more ‫݌‬ଶ ൌ ‫ݍ‬ଶ ‫݁ כ‬ሺ݇ െ ʹሻ
compact, power-HI¿FLHQWZKLOHDGding high speed capabilities. 
‫ݏ‬ଵ ൌ ‫݌‬଴ ൅ ‫݌‬ଵ
‫ݏ‬ଶ ൌ ‫݌‬ଶ ൅ ‫ݏ‬ଵ
II. DESIGN OF THE DISCRETE PID CONTROLLER ‫ݑ‬ሺ݇ሻ ൌ ‫ݏ‬ଶ ൅ ‫ݑ‬ሺ݇ െ ͳሻ
The conventional PID controller equation is given as
follows: In this case it is used the parallel design of the digital based
PID algorithm [7] which means that each of the operation has
ଵ ௧ ௗ௘ሺ௧ሻ its own arithmetic unit, either accumulator or multiplier.
‫ݑ‬ሺ‫ݐ‬ሻ ൌ ‫ܭ‬௣ ቄ݁ሺ‫ݐ‬ሻ  ൅  ‫׬‬଴ ݁ሺ߬ሻ݀߬ ൅  ܶௗ
் ௗ௧
ቅ (1) Parallel design is shown In Fig. 1.
೔

q0
where Kp is the proportional gain, Ti is integral time constant,
MULT1

e(k)
Td is derivate time constant, e is the error signal and u is the p0
s1

control output. For a sample time T this equation can be

SUM2

w
SUM1

e(k-1)
u(k)
REG2

modified into a difference equation:

COMPL

in
REG1

SUM4
2nd

p1
y -y
MULT2

clk
் ்ವ
൅  σ௞ିଵ ሾ݁ሺ݇ሻ െ ݁ሺ݇ െ ͳሻሿቅ ሺʹሻ
SUM3

‫ݑ‬ሺ݇ሻ ൌ ‫ܭ‬௣ ቄ݁ሺ݇ሻ ݁ሺ݅ሻ ൅ clk q1

்೔ ௜ୀ଴ ் p2
s2
REG4

u(k-1)
This type of difference equation is called the position PID
REG3
MULT3

algorithm [8]. It is not ideal for the realizations in the real clk

application because to compute the summation in (2) it must be q2

clk
stored all the previous errors (e(0), e(1) … e(k-1)). This problem
Fig. 1. Parallel design of discrete PID for FPGA design
is solved by the recursive PID algorithm. Control output u(k) is
expressed in (2). Control output u(k-1) can be expressed in Each sampling period there is loaded output y(k) from motor
form: system to the input in. Using binary functions of negation and
subtraction there is calculated WZR¶VFRPSOHPHQWELQDU\YHFWRU
‫ݑ‬ሺ݇ െ ͳሻ ൌ y which gives the negative value of y. Control error e(k) is
் ்ವ
ܲ ቄ݁ሺ݇ െ ͳሻ ൅  σ௞ିଶ
௜ୀ଴ ݁ሺ݅ሻ ൅  ሾ݁ሺ݇ െ ͳሻ െ ݁ሺ݇ െ ʹሻሿቅ ሺ͵ሻ computed in block SUM1 where the signal y(k) is subtracted
்೔ ்
 from w(k). Signal e(k) is held as a constant in the registry REG2

2014 15th International Carpathian Control Conference (ICCC) 234

for one sampling period. Register REG2 output signal is thus
e(k-1). In the same manner e(kí2) and u(kí1) are recorded at
REG4 and REG3 by latching e(kí1) and u(k) respectively.
A. Software verification
Before the hardware implementation the discrete PID
algorithm is verified of software Matlab-Simulink. System
Generator toolbox ensures that between the blocks gateway in
and gateway out algorithm performs as it was implemented on
FPGA. We proposed decomposed control algorithm to be
consisted of Xilinx blocks (in Fig. 2). In this step we determined
the minimum widths of the internal signals. For the
implementation of decimals numbers it has been used fixed
point arithmetic. Based on the successful verification of the
Xilinx blocks algorithm we created the VHDL code which is
used in the resulting hardware solutions. The VHDL code we
have developed in Xilinx ISE Design Suite. For the Fig. 5. Time response of control output
implementation of fixed point arithmetic in VHDL code there
is used library (ieee_proposed.fixed_pkg). Simulation of VHDL As we can see on Fig. 4 and Fig. 5 there is any differences
code is possible using Xilinx black box block. Simulation between Simulink discrete PID, discrete PID realization with
results are in Fig. 4 and Fig. 5. Xilinx blocks and VHDL based discrete PID. Control algorithm
was designed successfully.
III. HARDWARE IMPLEMENTATION
For the PID control it is used simply feedback control loop
(Fig. 4.). Controlled motor system consist of two DC motors
linked by a common shaft whit the incremental encoder. One
motor can be used as the main one and the other as a load.
Fig. 2. Schematic of control circuit using Xilinx blocks Moreover, the motor system includes the electronic
components for the motor drive and the components for transfer
data from the incremental encoder in the standard voltage from
0 to 3.3 V. In this case is used only one input for main motor.
Input can be voltage from 0 to 3.3 V. Output of the motor
system is velocity represented also by Volts.
The overall control system is based on Xilinx Spartan-6
FPGA witch is included in SP-601 demoboard. Spartan-6
FPGAs offer advanced power management technology, up to
150K logic cells, advanced memory support, 250MHz DSP
slices, and 3.2Gbps low-power transceivers. The overall control
Fig. 3. Schematic of VHDL control circuit code using Black Box system is composed of five components as we as we can see in
the Fig. 6. Clock divider provides the sample rate and the CLK
signal for the other components. Setpoint management
generates a reference signal w. In control algorithm there is
computed each sample time control output u. Control algorithm
is described in the previous section. DAC an ADC interfaces
transmit or receive data from convertors.
Communication between FPGA and motor system provides
A/D and D/A converters. The ADC has width of 12-bit and the
DAC has width of 8-bit. Both converters operate up to a
maximum frequency 1MSPS [6].

switch Setpoint Control D/A

w u DAC inteface Motor Load
management algorithm converter

Measurement
Clock divider A/D
y ADC inteface of motor
converter
speed

FPGA Motor system

Fig. 4. Time response of closed-loop

Fig. 6. Block scheme of control loop

2014 15th International Carpathian Control Conference (ICCC) 235

 IV. RESULTS processes and we presented in this paper the basic necessary
For verification of the FGPA hardware implementation of principles how to realize and modified existing PID control
the digital PID controller we performed experiment. Around the algorithms. We scheduled this approach for the predictive
operating point of the motor system we made step of reference control and soft computing methods.
signal. We compared then time response of hardware closed ACKNOWLEDGMENT
loop on the Matlab simulation with designed digital PID
controller. Experiment results of the closed loop control are This paper is supported by APVV project No APVV-0772-12
shown in Fig. 7 and Fig.8.

REFERENCES
[1] â.R]iN³0RGHUQpDSUDNWLFNpSUtVWXS\UHDOL]iFLH3,'UHJXOiWRURY´LQ
ATP Journal, ISSN 1335-2237, 2011, no.4.
[2] .R]iN â 'HYHORSPHQW RI FRQWURO HQJLQHHULQJ PHWKRGV DQG WKHLU
applications in industry (Invited Lectures) In 5th International Scientific-
Technical Conference Process Control 2002. Kouty nad Desnou, Czech
Republic:June 9-12, 2002. CD
[3] V. Viswanathan, ³(PEHGGHG&RQWURO8VLQJ)3*$´ Indian Institute of
Technology, Bombay.
[4] M. Koc~U ³+: UHDOL]iFLD 3,' DOJRULWPRY QD Ei]H )3*$ ãWUXNW~U´
Slovak University of Technology in Bratislava, Bratislava.
[5] ;LOLQ[,QF³6SDUWDQ-6 FPGA Family´ http://www.xilinx.com.
[6] 'LJLOHQW,QF³Digilent PmodAD1 and PmodDA1´ http://digilentinc.com.
[7] W. Zhao, B. Hwa, A.Larson, and R9R\OHV³FPGA implementation of
closed loop control system for small scale robot.´ In Proceedings.,12th
International conference on advanced robotics-ICAR 05, pages 70±77,
Fig. 7. Time response of closed-loop 2005.
[8] I, âYDUF0âHGDDQG09tWUþNRYi$XWRPDWLFNpĜt]HQt%UQR9\VRNp
XþHQtWHFKQLFNpY%UQČ,6%1 978-80-214-2491-2.

Fig. 8. Time response of control output

As seen in Fig. 7, the results of the hardware

implementation are very similar with Matlab obtained by
simulation only the high noise is making differences. In the
Matlab simulation it was used digital PID controller
implemented in VHDL by Xilinx Back box it was verified in
the previous section. Focused on the quality of control at the
steady state it was reached zero control error. The maximum
overshoot is 10% as in the case of simulation. For the defined
steady state sensitivity range “  FRQWUROOHG signal was
stabilized at 0.495s. At the VHQVLWLYLW\RI“ regulation had
time 0.885s.
V. CONCLUSION
In this paper we presented design and implementation of the
digital based PID on FPGA. Digital PID was successfully
implemented and deployed for the real motor system.
Application of FPGA structure is very suitable for high speed

2014 15th International Carpathian Control Conference (ICCC) 236