Automatic relocking of an FPGA-based PID controller

using a bandpass-filtering approach

Alexander Hungenberg

supervised by
Ludwig de Clercq
Vlad Negnevitsky

and Prof. Dr. Jonathan Home

Trapped Ion Quantum Information Group

Department of Physics, ETH Zurich

August 21, 2013

Abstract
This report describes a discrete-time filter approach to improve the stability of
PID controlled locks with respect to infrequent and comparatively large disturbances
that exceed the usable error signal range. The concept has been implemented with
Verilog on an FPGA and was tested on several systems of varying intrinsic stability.
Further work has been put into the PyQt based configuration interface to allow
completely asynchronous data streaming of input and output channels as well as
configuration updates on a single serial communication channel.

1
Contents
1 Introduction 3

2 Error signal theory 3

2.1 General applicability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2 Pound-Drever-Hall error signal . . . . . . . . . . . . . . . . . . . . . . . . 4

3 Digital filtering theory 5

3.1 Laplace- and Z-transform . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2 Transfer function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.3 Frequency response of a discrete low-pass filter . . . . . . . . . . . . . . . 7

4 Relocking using a bandpass filter 7

4.1 PID output high pass filter . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2 User configurable low pass filter . . . . . . . . . . . . . . . . . . . . . . . . 9
4.3 Automatic relocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

5 Graphical user interface 10

5.1 Python Global Interpreter Lock (GIL) issues . . . . . . . . . . . . . . . . 10
5.2 Solution for PyQt integrated parallel code execution . . . . . . . . . . . . 10
5.2.1 Communication process . . . . . . . . . . . . . . . . . . . . . . . . 10
5.2.2 Queuing thread . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.2.3 GUI thread . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.3 Implementation of a live oscilloscope view . . . . . . . . . . . . . . . . . . 12

6 Functional verification and tests 12

6.1 Verilog testbenches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6.2 Digital oscilloscope and waveform generator . . . . . . . . . . . . . . . . . 12

7 Experimental setup 13
7.1 Test procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

8 Results 14

9 Conclusion 15

10 Acknowledgements 16

A Module documentation and sourcecode 17

A.1 Low-pass filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
A.2 Out-of-lock detection module . . . . . . . . . . . . . . . . . . . . . . . . . 18

2
1 Introduction
Proportional-integral-derivative (PID) feedback loop controllers are widely used algo-
rithms to control devices automatically and keep their output stable (locked) at a given
configuration. When configured correctly they provide great performance and stability
with minimal user intervention. However, when it comes to sudden external influences
with unusually high magnitudes, the PID parameters may not provide corrections large
enough to keep the device stable. In many cases this is not a long-term problem, since the
error signal guides the controller back to the desired configuration - but unfortunately
there are setups which provide a usable error signal only within a very narrow region
around the lock point (example in figure 3b). If this region is exceeded, the controller
will no longer provide a correcting output. A common example is the Pound-Drever-Hall
error signal which is widely used to stabilize lasers or cavities.
To tackle this problem a digital filter solution has been developed on top of an existing
PID controller FPGA module to disallow control outputs of uncommon significance. This
report contains a theoretical analysis of the filter, a complete description of the solution
and some experimental results.
Additionally, since the (filtered) PID controller is configurable via a Python/PyQt
based graphical user interface (GUI) over an USB connection, many improvements have
been implemented into the configuration GUI. The most significant change introduces
a live oscilloscope view of the PID input and output channels. This modification re-
quired a complete rewrite of the former single-threaded program. The new solution for
asynchronous, serial communication which integrates nicely with PyQt’s signal/slot sys-
tem and works around Python’s global-interpreter-lock restrictions will be discussed in
section 5.

2 Error signal theory

The out-of-lock detection and relocking software was written to be used with a Pound-
Drever-Hall error signal initially. This specific type of error signal will be explained later.
The general applicability of this technique is much broader.
The reason why the relocking feature is even needed, follows from the fact that the
error signal is only nonzero and linear within a small region around the locking point. If,
after some significant disturbance, the controlled device jumps out of the non-zero error
signal region, the unmodified PID controller will not come back to the linear region.

2.1 General applicability

This method of relocking will be applicable to every error signal which has odd symmetry.
As an improvement, the usable error signal region may be much smaller than before. This
follows from the bandpass filter approach which detects PID corrections that probably
will leave the usable error signal region.

3
Figure 1: Pound-Drever-Hall error signal generation setup [1]. The incoming laser beam
will be slightly modulated to gain access to the odd-symmetric derivative of the reflected
cavity intensity.

2.2 Pound-Drever-Hall error signal

Generating a usable error signal for frequency stabilization of a laser is not as intuitive as
it seems. For example using the intensity measured behind a cavity (e.g. Fabry-Perot)
will not work, since this error signal is symmetric around the lock point (compare fig. 2).
A possible and widely-used, but more com-
plex solution is the Pound-Drever-Hall error signal.
With this method (fig. 1) it is possible to generate
a usable error signal which can then be fed back to
a PID controller to regulate and stabilize the laser
frequency.
Basically, the reflected intensity of a cavity is
used as a starting point. This is zero when the
laser is at cavity resonance frequency and will sym-
Figure 2: Fabry-Perot etalon trans- metrically increase around this point. To achieve
mission intensity [1] a PID usable signal from this, the frequency of the
laser beam is modulated sinusoidally over a small
range. Measuring the resulting reflected intensity
and multiplying it with the frequency modulation sine (including some phase shift) in
the small-modulation limit, gives the derivative of the intensity signal, which will be
negative when below resonance frequency and positive above.
Figure 3a gives a plot of the resulting Pound-Drever-Hall error signal with slow
modulation frequencies. When the modulation frequency is increased this plot will
shrink horizontally and include additional sidebands (fig. 3b).

4
 (b) Fast modulation at carrier resonance
(a) Slow modulation of Beam frequency frequency

Figure 3: Pound-Drever-Hall error signal with two different beam frequency modulation
speeds [1]

The mathematical derivation and a much more detailed explanation of this topic can
be found in the excellent paper of Eric D. Black [1].

3 Digital filtering theory

Filters are devices widely used in signal processing
R setups to remove unwanted frequencies from a sig-
nal as well as for other purposes. The most basic
types are either high-pass (suppresses low frequen-
vin vout cies) or low-pass (suppresses high frequencies) fil-
C
ters. For example, a common application for a low-
pass filter is to remove high-frequency noise from
a signal. Such noise is often picked up when the
Figure 4: First-order RC low-pass signal is transmitted over a long cable. On the
filter [9] other hand, a possible high-pass filter application
is to extract the ripple component of an oscillating
voltage.
Originally, these filter devices have been created with analog electronic circuits, like
the famous RC low-pass filter design (fig 4). As an alternative to building these circuits
using analog components, it is possible to implement similar filters on a discrete time-
base using synchronized logic hardware like an FPGA. This makes (re-)configuration of
the setup much simpler and allows the addition of further features; like the relocking
functionality. FPGAs do have an advantage over conventional computers or microcon-
trollers due to their massive concurrent design. Therefore it is possible to add additional
features without affecting the main PID controller speed at all.
The behaviour of a filter can mathematically be described with its transfer function
which relates the filter output to its input in the frequency (Laplace) domain. This will

5
be described in greater detail in the following two sections.

3.1 Laplace- and Z-transform

The Laplace transform L is defined as a change of basis of a function φ(x) into the space
of exponentially decaying functions.
Z ∞
φ̂(s) = [Lφ](s) = e−ts φ(t)dt
0

It works for all piecewise continuous functions φ(t) which are zero for t < 0 and do not
grow faster than Ceαt for some α ∈ R and C > 0 [2].
Laplace transforms mainly have two very important properties which are frequently
used especially for calculation purposes:
• Complex linearity: L(wφ + vψ) = wLφ + vLψ
• Differentiation in the time domain becomes multiplication by s:
φ0 (t) = sφ̂(s) − φ(0+ )
Having the first property makes it a lot simpler to transform functions with the usage of
readily calculated tables. The second one can then for example be used to solve ordinary
differential equations algebraically.

If it is the case that φ(t) can only be sampled at discrete timesteps T such that φ[n] =
φ(nT ), the corresponding discrete transform Z is called the (unilateral) Z-transform:
∞
X
φ̂(z) = Zφ(z) = φ[n]z −n
n=0

It has the same linearity property as the Laplace transform. Additionally, the shifting
theorem [7] is very important for daily use:
f [n − 1] = z −1 fˆ(z) + f [−1]
Here f [−1] is the initial condition which is usually set to 0.

3.2 Transfer function

Consider some linear differential equation which relates the input x(t) of a system to its
output y(t)
dn y
an y (n) (t) + an−1 y (n−1) (t) + · · · + a0 y(t) = x(t) where y (n) :=
dtn
This equation can be solved more easily when transformed into Laplace space where it
can always be rearranged to the following form due to the differentiation rule
ŷ(s) = h(s)x̂(s)

6
Here h(s) is called the transfer function of a continuous system since it relates the system
input and output in Laplace space.
Transfer functions of discrete or continuous systems can be related to each other
by using the so called bilinear transform (chapter 7.1.2, Oppenheim and Schafer [6]).
It provides the following two substitutions, where z is the parameter in Z-space, s the
parameter in Laplace-space and T the sampling period:
2 z−1 2 + sT
s= · z=
T z+1 2 − sT
This is very useful in digital filter design, since now the algorithm can be immediately
derived from a continuous design transfer function.

3.3 Frequency response of a discrete low-pass filter

A first-order, discrete low-pass filter with unity gain at DC has the following iterative
equation [10]
y[n] = αx[n] + (1 − α)y[n − 1]
where α is a real constant determining the frequency response. Applying the Z-transform
to both sides of the equation yields:

ŷ(z) = αx̂(z) + (1 − α)(z −1 ŷ(z) + y[0])

α
= ·x̂(z)
1 − (1 − α)z −1
| {z }
h(z)

From this transfer function h(z) the frequency response for a sinusoidal input signal
with frequency ω can easily be calculated by substituting z = eiωT (see page 28 of [8])

|h(eiωT )|

An example has been plotted in figure 5.

Linear filters may also be characterized with a single real number called cutoff fre-
quency. It is defined as the frequency where the amplitude gain drops below -3 dB of its
maximum and corresponds approximately to the intersection point of two straight lines
the reader may fit into figure 5.

4 Relocking using a bandpass filter

Using a bandpass filter to solve the problem with a very small usable error signal region
is explained step by step in the following sections. While reading them, it might be
helpful for the reader to look at the illustrative signal evolution example in figure 6.
Let us analyze what happens when a significant disturbance occurs and the system
leaves the locking range. Since the controlled device usually has mechanical properties,
it will not react instantly to control inputs due to its inertia. Therefore, it might happen

7
Gain @dBD
0

-5

-10

-15

Hz
0.01 0.1 1 10 100
Figure 5: Frequency dependent amplitude gain of a first-order, time-discrete low-pass
filter with a sampling frequency of 93.75 kHz and α = 2−16 . The cutoff frequency is
2.47 Hz.

that although the PID controller tries to compensate, the cavity jumps far away from
its original lockpoint to an unusable error signal region. As soon as this happens, the
controller will not be able to go back to the original lockpoint since the odd-symmetry
of the slope is gone.
Now, when this procedure is over, the absolute PID output value will be far away
from its original average point. And exactly this is what we will try to detect. In section
8 a real world measured example of such an event can be found.

4.1 PID output high pass filter

As a result, we are interested in very large short term corrections of the PID output
value, which will not happen during normal operation. Therefore we attach a high pass
filter to the PID output. Since a generic low-pass filter Verilog module has already been
developed, it will be reused at this point simply by taking the original PID output and
subtracting the low-pass filtered part. Of course this results in a subtraction of low
frequencies, leaving the higher ones behind.
The filter has a hard-programmed smoothing constant α and actually has exactly the
inverted specifications shown in figure 5. Therefore it lets almost everything pass except

8
 PID output

High-pass filter
extracts short time variations
from the PID output signal

Low-pass filter
configurable, smoothes signal
threshold

Threshold and TTL Expansion

configurable, triggers OOL signal
and extends its lifetime
OOL detected

Figure 6: Out-of-lock (OOL) detection module: Internal signal processing example.

some very low frequencies (smaller than approximately 2.5 Hz) that are for example
introduced due to temperature variations.

4.2 User configurable low pass filter

As a next step the absolute value of the filtered PID output is calculated since the
value’s jump direction is not of interest. This absolute value is now filtered again with
a configurable low-pass filter. This way the user can decide the extend to which smaller
or very narrow peaks shall be ignored. It should be noted here, that the low-pass filter
reacts to the surface below the peaks (so large and narrow is equivalent to small and
wide). The optimal setting for this configuration option is mainly determined by the
mechanical properties of the controlled device.

4.3 Automatic relocking

Finally, the detection of out-of-lock events reduces to a simple comparison whether the
filtered output goes above a configurable threshold value. As soon as this happens the
module’s peak detection o output will go high (see appendix A.2).
On top of the signal an additional time-to-live (TTL) expander has been integrated
to the module which will extend the peak detection signal lifetime. This is needed to give
the controlled device the ability to mechanically stabilize again after the disturbance.

9
5 Graphical user interface
One aim of the project was to remove the need for an external oscilloscope during
the laser locking process and implement a real time display with the already available
streaming feature on the hardware side.
Since the previous GUI version was basically a single-threaded configuration interface
for the PID controller, streaming data to the GUI required a complete rewrite. The
asynchronous nature of the streaming made it impractical to stay with the single thread
design and forced a fully parallel approach.

5.1 Python Global Interpreter Lock (GIL) issues

Python’s standard implementation ‘CPython’ uses a mechanism called GIL to prevent
the interpreter of running python code in parallel. According to the Python wiki [4] this
has to be avoided due to the not thread-safe memory management of the interpreter.
The only possible solution to workaround this problem is the usage of more than one
python interpreter process. Unfortunately this breaks the standard PyQt signal/slot
event dispatching since they will not work across different processes. Therefore a mech-
anism with the usage of queues has been implemented to integrate the communication
process into the GUI.

5.2 Solution for PyQt integrated parallel code execution

Figure 7 gives an overview of the chosen approach to solve the GIL restrictions for
parallel python code execution and while also integrating nicely with Qt’s signal/slot
system.
In this setup all the low level communication runs serialized in a separate process
that communicates with the GUI via a result and command queue which will then be
translated in another thread to Qt signals.

5.2.1 Communication process

This python function runs via the multiprocessing library in a second interpreter process.
It features an infinite loop which pulls a new command via a non-blocking call. If no
command was received and streaming is enabled, a streaming packet will be requested
according to the settings and then pushed to the result queue when the data is ready.

10
 Main process
GUI thread Queuing thread

generate signals queue user inter-

Qt
due to action events to
signals/slots
user interaction command queue

provide slots to receive results

alter GUI and convert them
FPGA (e.g. plot display) into PyQt signals

Communication process
USB connection
- fetch command from command queue
- FPGA communication
- post result into result queue

Figure 7: Internal thread and process structure of the GUI to allow asynchronous com-
munication and therefore streaming with the FPGA

5.2.2 Queuing thread

This thread acts as interface between PyQt’s signal/slot system and the communication
process. It features two parts:
• command methods These methods will be called in the GUI thread as a high-
level interface. They will enqueue the corresponding command into the command
queue. Some available commands are for example read (read register value), write
(write register value) or start streaming.
• result receiver loop This infinite loop waits on the result queue for new results
(waiting releases the GIL and allows the main thread to run concurrently) and
posts them to the main thread via signals (currently read setting(int) and
got stream data(numpy.ndarray))

5.2.3 GUI thread

This is the main application thread and currently handles everything non communica-
tion related. As an important feature it provides slots for the read setting(int) and
got stream data(numpy.ndarray) signal from the queuing thread.

11
5.3 Implementation of a live oscilloscope view
This feature is intended to replace the single-shot time-series display which existed be-
fore. It basically recorded a specific number of samples with a given rate from a chosen
channel (PID input, PID output, ...) and displayed them in a plot generated with
matplotlib [5].
Unfortunately this library has difficulties with fast plot updates and also Qt inte-
gration is not very elegant. Therefore PyQtGraph [3] was chosen as a powerful and
fast alternative. Its PlotWidget can be used as a QGraphicsView replacement, and
from there the live view is just a connection of the PlotWidget.plot method to the
got stream data signal generated by the queueing thread.

6 Functional verification and tests

The functionality of the written Verilog code has been verified on increasing levels of
abstraction. First via simulation with Verilog testbenches and second with a digital
waveform generator and oscilloscope. Finally it has been tested with a real experimental
setup in the lab which will be described in section 7.

6.1 Verilog testbenches

Basically, two additional Verilog modules were written during the implementation of
this project: one configurable discrete low-pass filter and the mentioned out-of-lock
detection module. Both have been tested first with simulation using testbenches. To
simplify writing them, only square wave data input was considered.
The filter testbench created a sudden jump in the input from zero to an arbitrary
value. According to the theory (sec. 3), the output should exponentially tend toward
the new value with a time constant as calculated (time constant equals the inverse cutoff
frequency).
On the out-of-lock detection module testbench the input consisted of a constant arbi-
trary value with small peaks of different width and height. Depending on the parameter
configuration and peak shape, the peak detection signal should trigger and stay high for
the configured TTL expansion.

6.2 Digital oscilloscope and waveform generator

As soon as the simulations ran successfully, the firmware was implemented on the FPGA
to which a digital waveform generator and oscilloscope were connected. This device1
was able to generate similar waveforms as in the software testbench and simultaneously
monitor output values. Therefore it was possible to test the GUI interaction with the
out-of-lock detection module as well as the relocking feature.
1
Digilent Inc. ‘Analog Discovery’ Design Kit

12
 Laser Pound-Drever-Hall Doubling cavity
Blackbox

error signal
Python GUI PID output
FPGA

USB connection
Figure 8: Possible real world application of the lockbox. Here it is used to control the
length of an unstable frequency doubling device to track a given laser frequency. The
error signal is generated by using a Pound-Drever-Hall blackbox with the reflected cavity
intensity.

7 Experimental setup
The lab testing setup covers a standard application situation and is displayed in figure 8.
A frequency doubling cavity should precisely track a given laser frequency. Due to small
temperature changes and acoustic disturbances in the laboratory the cavity length has
to be constantly adjusted with the use of a PID controller acting on a Pound-Drever-Hall
error signal. Originally the cavity was controlled without the bandpass filter solution.
This worked sufficiently well in a controlled environment.
But to the used doubling cavity disturbances as someone clapping or, more likely,
accidentally hitting the table had significant effects. In such cases the pure PID controller
was not able to keep the lock at the correct position and probably jumped to a sideband,
even with carefully chosen gain values. This behaviour is even worse than falling out of
lock completely, since the cavity frequency changes without any notice of the user.

7.1 Test procedure

Before each test the laser was locked to the desired frequency using the same PID
gain parameters such that it stayed in lock during quiescent operation. Then a weight

13
 Figure 9: Disturbance of the cavity with relocking feature disabled.

(approximately 100 g) was dropped on the table from a height of 1 cm and 20 cm away
from the cavity.

8 Results
The following individual plots are recorded from comparable but different events due
to the lack of a multi-channel streaming possibility. The data has been taken solely for
visualization purposes within the given precision in the plots.
Figure 9 shows the error signal (orange) and the eight most significant bits of the PID
output value (green). Starting from left one can see a stable controlled lock. Then, at
about 120 ms the error signal shows the disturbance which results in a huge drift of the
PID output, corresponding to a cavity length change. Finally, the output stabilizes at a
completely different length of the cavity, which is the worst scenario for a user unaware
of the resulting output frequency shift.
In contrast to this figure 10 shows the same procedure, but now with the relocking
feature enabled and TTL expansion set to roughly 400 ms. This time the green plot

14
 Figure 10: Disturbance of the cavity with relocking feature enabled.

corresponds to the eight least significant bits of the PID output, while the topmost eight
bits (as shown in the last figure) do not change at all due to the action of the relocking
system. One clearly sees the disturbance which is almost immediately detected and the
PID output is held constant at its last known average value. Then, as the disturbance
goes away after about 200 ms the TTL expander still holds the PID constant for another
400 ms until it releases the controller back to normal operation.

9 Conclusion
The results did clearly show a huge improvement regarding shock resistance of the cavity
lock. In reality, the lock even stabilized after much larger impacts like dropping a
screwdriver from 30cm or running against the table. These situations are not uncommon
when working in a lab, and using a controller which does not require manual interaction
in the case of such events increases productivity a lot. Also the new oscilloscope feature
of the GUI simplifies debugging during the development process on the FPGA as well as
configuration of the relocking feature. This is due to the possibility of having a live view

15
of the filtered PID output used in the out-of-lock detection module, which can then be
used to choose the cutoff frequencies and threshold values.
Still, lots of further improvements could be made: for example the ability to stream
more than one channel simultaneously (at cost of package length) or even automagical
configuration of the whole device to reduce (re-)configuration effort once again. The
implementation of these features is greatly eased by the code structure of the Python
GUI, giving users the flexibility to automate these actions in the future without needing
to modify the FPGA code.

10 Acknowledgements
I would like to express my very great appreciation to my supervisors Professor Dr
Jonathan Home, Mr. Vlad Negnevitsky and Ludwig de Clercq for their outstanding
support, helpful hints and very useful critiques during my work. Additionally I am par-
ticularly grateful for the end-user feedback and assistance given by Mr. Florian Leupold
and Mr. Hsiang-yu Lo during the software testing.

16
A Module documentation and sourcecode
A.1 Low-pass filter
clk Supposed to be a 96 MHz clock. Different clock speeds will alter the cutoff fre-
quency.
data i
Filter input value.
smoothing i
This parameter is meant to be configured with values between 0 and 32767 and
determines the low-pass filter cutoff frequency. Higher values mean faster response.
Further explanations can be found in section 3.3.
data o
Low-pass filtered output value.

module l p f i l t e r (
input clk ,
input signed [ 1 5 : 0 ] data i ,
input signed [ 1 5 : 0 ] smoothing i ,
output reg signed [ 1 5 : 0 ] d a t a o ) ;
// r e a l smoothing i s smoothing ∗2ˆ( −16)

parameter a c c b i t s = 3 1 ;
parameter g a t e d c l o c k b i t s = 1 0 ;
parameter u s e g a t e d c l o c k = 1 ;

reg signed [ 1 5 : 0 ] data last i = 0;

reg signed [ a c c b i t s : 0 ] d a t a r = 0 ;
reg signed [ a c c b i t s : 0 ] s m o o t h i n g m u l t i p l i e d r = 0 ;

wire signed [ 1 5 : 0 ] d a t a o w ;
reg signed [ 1 5 : 0 ] data temp = 0 ;
assign d a t a o w = d a t a r [ a c c b i t s : a c c b i t s − 1 5 ] ;

i n i t i a l begin
d a t a o <= 0 ;
end

// Gated c l o c k t o s l o w down s a m p l i n g r a t e
reg [ g a t e d c l o c k b i t s − 1 : 0 ] g a t e d c l o c k c o u n t e r r = 0 ;
always @( posedge c l k ) begin
if ( use gated clock )
g a t e d c l o c k c o u n t e r r <= g a t e d c l o c k c o u n t e r r + 1 ;
else

17
 g a t e d c l o c k c o u n t e r r <= 0 ;
end

always @( posedge c l k ) begin

d a t a l a s t i <= d a t a i ;
data temp <= d a t a l a s t i − d a t a o w ;
s m o o t h i n g m u l t i p l i e d r <= s m o o t h i n g i ∗ data temp ;
i f ( g a t e d c l o c k c o u n t e r r == 0 ) begin
d a t a r <= d a t a r + s m o o t h i n g m u l t i p l i e d r ;
d a t a o <= d a t a o w ;
end
end

endmodule // l p f i l t e r

A.2 Out-of-lock detection module

clk Supposed to be a 96 MHz clock
data i
The data on which large deviations will be detected. In our setup this is connected
to the PID controller output.
smoothing i
This parameter is meant to be configured with values between 0 and 32767 and
determines the low-pass filter time constant. Higher values mean faster response.
peak threshold i
Determines the absolute value of the bandpass-filtered data at which the peak
detection module will trigger.
peak detected ttl i
After the peak detection has been triggered this parameter will extend the lifetime
of the detection signal. Higher values mean longer lifetime.
peak detected rst i
If this line is low, the entire module will be disabled (data slow lp o will continue
to update).
peak detected o
This output will go high as the filtered absolute data passed the threshold
data slow lp o
Follows the data i parameter very slowly. Used in our setup as a starting point
for relocking after an out-of-lock event.
data i filtered o
The completely bandpass filtered output. In the complete setup this parameter
can be streamed to GUI. This helps a lot to configure the smoothing, TTL and
threshold parameters.

18
module l p p e a k d e t e c t o r (
input clk ,

input signed [ 1 5 : 0 ] data i ,

input signed [ 1 5 : 0 ] smoothing i ,
input [15:0] peak threshold i ,
input [15:0] peak detected ttl i ,
input peak detected rst i ,

output reg peak detected o ,

output reg [ 1 5 : 0 ] data slow lp o ,
output reg [ 1 5 : 0 ] data i filtered o );

i n i t i a l begin
p e a k d e t e c t e d o <= 0 ;
d a t a s l o w l p o <= 0 ;
end

// Make t h e i n p u t an r e g i s t e r f o r o p t i m i z a t i o n p u r p o s e s
reg signed [ 1 5 : 0 ] d a t a i r = 0 ;
reg signed [ 1 5 : 0 ] s m o o t h i n g i r = 0 ;
reg [ 1 5 : 0 ] peak threshold i r = 0;
reg [ 1 5 : 0 ] peak detected ttl i r = 0;
always @( posedge c l k ) begin
d a t a i r <= d a t a i ;
s m o o t h i n g i r <= s m o o t h i n g i ;
p e a k t h r e s h o l d i r <= p e a k t h r e s h o l d i ;
p e a k d e t e c t e d t t l i r <= p e a k d e t e c t e d t t l i ;
end

wire [ 1 5 : 0 ] d a t a i s l o w l p ;
wire [ 1 5 : 0 ] d a t a i l p d i f f ;

// d a t a i l p d i f f i s h i g h −p a s s f i l t e r e d v a l u e
assign d a t a i l p d i f f = d a t a i r − d a t a i s l o w l p ;

lp filter l p f i l t e r s l o w i (. clk ( clk ) ,

. data i ( data i r ) ,
. s m o o t h i n g i ( 1 6 ’ d1 ) ,
. data o ( d a t a i s l o w l p ) ) ;

wire [ 1 5 : 0 ] d a t a i f i l t e r e d ;
reg [ 1 5 : 0 ] d a t a i f i l t e r e d a b s = 1 6 ’ d0 ;

19
// g e t a b s o l u t e v a l u e o f d a t a i l p d i f f
always @( posedge c l k ) begin
if ( data i filtered [15])
d a t a i f i l t e r e d a b s <= − d a t a i f i l t e r e d ;
e l s e d a t a i f i l t e r e d a b s <= d a t a i f i l t e r e d ;

d a t a i f i l t e r e d o <= d a t a i f i l t e r e d a b s ;
end

lp filter l p f i l t e r i (. clk ( clk ) ,

. data i ( data i lp diff ) ,
. smoothing i ( smoothing i r ) ,
. data o ( d a t a i f i l t e r e d ) ) ;

// c r e a t e a g a t e d c l o c k t o be used w i t h t h e t t l
// f o r p e a k d e t e c t i o n s i g n a l . we have a
// 16 b i t c o n f i g u r a t i o n r e g i s t e r f o r t t l and want
// t o make i t c o n f i g u r a b l e up t o a l e n g t h o f a b o u t
// one second ( a 96MHz c o u n t e r would use 27 b i t ) .
// so we i n t r o d u c e a 11 b i t g a t e d c l o c k
reg [ 1 0 : 0 ] p e a k d e t e c t i o n g a t e d c l o c k = 0 ;
always @( posedge c l k ) begin
p e a k d e t e c t i o n g a t e d c l o c k <= p e a k d e t e c t i o n g a t e d c l o c k + 1 ;
end

reg [ 1 5 : 0 ] p e a k d e t e c t i o n r s t c o u n t e r r = 0 ;

always @( posedge c l k ) begin

i f ( d a t a i f i l t e r e d a b s > p e a k t h r e s h o l d i r ) begin
p e a k d e t e c t e d o <= 1 ;
end e l s e begin
// we w i l l s t a r t t h e t t l expand o n l y
// a f t e r t h e peak has gone
i f ( p e a k d e t e c t e d o && p e a k d e t e c t i o n g a t e d c l o c k == 0 )
peak detection rst counter r
<= p e a k d e t e c t i o n r s t c o u n t e r r + 1 ;
i f ( p e a k d e t e c t i o n r s t c o u n t e r r > p e a k d e t e c t e d t t l i r ) begin
p e a k d e t e c t e d o <= 0 ;
p e a k d e t e c t i o n r s t c o u n t e r r <= 0 ;
end
end

20
 d a t a s l o w l p o <= d a t a i s l o w l p ;

// a r e s e t w i l l c l e a r t h e peak d e t e c t i o n s i g n a l
// and t t l c o u n t e r i m m e d i a t e l y
i f ( p e a k d e t e c t e d r s t i == 0 ) begin
p e a k d e t e c t e d o <= 0 ;
p e a k d e t e c t i o n r s t c o u n t e r r <= 0 ;
end
end

endmodule // l p p e a k d e t e c t o r

References
[1] Eric D. Black. “An introduction to Pound-Drever-Hall laser frequency stabiliza-
tion”. In: American Journal of Physics 69.1 (Jan. 2001), pp. 79–87. issn: 00029505.
doi: 10.1119/1.1286663. url: http://dx.doi.org/10.1119/1.1286663.
[2] Christian Blatter. Laplace-Transformationen. German, p. 186. url: http://www.
math.ethz.ch/~blatter/complex_8.pdf.
[3] Luke Campagnola. PyQtGraph. Scientific Graphics and GUI Library for Python.
June 14, 2013. url: http://www.pyqtgraph.org/.
[4] Global Intepreter Lock. Python Wiki. June 13, 2013. url: http://wiki.python.
org/moin/GlobalInterpreterLock?action=recall&rev=27.
[5] J. D. Hunter. “Matplotlib: A 2D graphics environment”. In: Computing In Science
& Engineering 9.3 (2007), pp. 90–95.
[6] A. V. Oppenheim and R. W. Schafer. Discrete-time signal processing. Prentice
Hall, 1989.
[7] Athanasios Papoulis. Circuits and Systems. A Modern Approach. 1980, p. 100.
[8] Elena Punskaya. Basics of Digital Filters. url: http : / / www - sigproc . eng .
cam . ac . uk / ~op205 / 3F3 _ 4 _ Basics _ of _ Digital _ FIlters . pdf (visited on
06/26/2013).
[9] Wikipedia. A circuit diagram of a simple 1st order RC lowpass filter. url: http:
//en.wikipedia.org/wiki/File:1st_Order_Lowpass_Filter_RC.svg (visited
on 06/26/2013).
[10] Wikipedia. Low-pass filter — Wikipedia, The Free Encyclopedia. 2013. url: http:
/ / en . wikipedia . org / w / index . php ? title = Low - pass _ filter & oldid =
559549649 (visited on 06/27/2013).

21