Important

Week1

 According to Moore’s law, the number of transistors that can be fabricated in a chip will
double every 18 months, i.e. an exponential growth is predicted. It does not talk anything
about power consumption.
 The functionality of a design at the behavioral level can be specified as Boolean equation,
truth table, state transition diagram/table and algorithms written in some high level
languages.
functionality of a design
 The truth table and verilog “assign” statement represent design at the behavioral level. At
structural level functionality can also be specified as a netlist consisting of logic gates.
 Truth table represents behavioral description, and so are logic expressions specified using
“assign” statements. Any netlist representingan interconnection of blocks represents
structural description.
FPGA
 The LUTs are typically realized using small SRAM units, and can realize any arbitrary
function of up to 4 variables. The output column of the truth table of the function to be
realized is downloaded to the SRAM.
 The LUTs in FPGA chips are realized using 16x1 SRAM units and an LUT can realize any
arbitrary 4 input and single output Boolean function. The functionality of a LUT can be changed
by downloading appropriate bit stream in the SRAM;
 (FPGA), where technology mapping from the gate level netlist is used.
Can be programmed in-field.• Much greater flexibility, but less speed.
 A standard mask is designed in case of gate array based implementation, consisting of an
array of unconnected transistors or gates. Depending on the function to be realized, the
transistors and gates can be suitably interconnected (customization step). Thus option (a)
is true.
 FPGA is predesigned device that is needed to be programmed or configured whereas
standard cell based design style use predesigned cell as building blocks and in full custom
style the placement, orientation and geometry of each individual transistor has been
considered.
 For gate arrays, fabrication proceeds in two phases. In the first phase, uncommitted
transistors are fabricated that are independent of the functions being implemented. In the
second phase, the interconnections of the transistors are carried out to realize arbitrary
functionality. The first component of the cost (C1) is shared among all customers who are
fabricating gate array chips, while the second component (C2) is specific to every customer).
standard cell based design
 It requires less design effort as compared to full custom design. The heights of the cells
are fixed but the widths can be different. In case of standard cell based design, since in a
row number of cells that can be placed is variable as cell width differs, and as over-the-
cell routing is also possible. Any number of cells can be placed in a row. since the
number of cells that can be placed in a row depends on their widths. since the cells are
already pre-designed and just have to be places along rows in the layout.
 correct ordering with respect to speed of circuits (slowest to fastest)
 FPGA, Gate array, Standard cell, Full custom
 (fastest to slowest) The correct ordering should be
Full Custom, Standard Cell, Gate Array, FPGA
 A test bench is required when we want to simulate a design. Technology specific
mapping of a design does not require a test bench. When we map a design to
hardware like FPGA or ASIC, we do not need any test bench. Test bench is required
for simulation, which involves using simulator software to analyze the input output
behavior of a given design.
 Test bench is only required for simulating the behavior of a design, it has no role in
case of technology specific mapping. Thus options (a) and (b) are true, Finally
simulation means verifying the behavior of the design applying certain inputs, thus
option.
 The module is designed using gates and interconnects, it represents the design at the
structural level.
Expressions

 A module cannot contain definitions of other modules. If a module X is instantiated 4

times within another module, 4 copies of X are created.
 verilog modules declarations must be disjoint. When a module X called N number of
times from another module, N copies of X are embedded inside the module. Any number
of modules can be invoked from within a module.
 More than one module can be instantiated within another module. Module definitions
must be disjoint. Also there is no concept of calling amodule from other modules. We can
only make copies or “instantiate” amodule any number of times within another module.
statement “assign f = !(a & b) | !(a ^ b)” signify?

 The value at LHS gets changed whenever there is a change in the expression at
RHS.Specification of a combinational circuit design at behavioral level An assign
statement represent continuous assignment, where the variable on the LHS gets updated
whenever the expression on the RHS changes. The LHS of an assign statement must be
net type whereas RHS can contain both net type as well as register type variables.. The
assign statement is typically used to model combinational circuit at the behavioral level.
 A behavioral description of the function f. A continuous assignment of the function
realized by the right hand side to the net type variable on the left hand side. The “assign”
statement only specifies the function; it does not specify the gates or the netlist to be used
for implementation..It only specifies the behavior of the function. Only “net” type
variables canbe assigned in an “assign” statement.
 register type variables?
 It can be used in an expression on the RHS of an “assign”statement.. Once a value is
assigned, it will hold the value. A register type variable may either map to a storage cell
during synthesis,
 or it may also realize a pure combinational circuit.In an “assign” statement, both “net”
and “register” type variables may beused in the expression on the right hand side. In
terms of the behavior, a register type variable holds a value once it is assigned to it.

net type variables?

 It represents connections continuously driven by the outputs of the connected device.
It can be used in an expression on the RHS of an “assign” statement. A net type variable
is continuously driven by the output of a gate or module. Thus option (a) is true. A net
type variable may appear on the RHS of an assign statement. Thus option (b) is also true.
Since net type variable is continuously driven, the value gets changed whenever the
output of the connected gate or module change. Thus option (c) is false.