Subject Code: G6803/R13

M. Tech – I Semester Regular/Supplementary Examinations, April, 2015

CMOS ANALOG IC DESIGN
(Common to VLSI&ES, ES&VLSI, VLSID&ES, ES&VLSID, VLSI, VLSID,
VLSISD and VLSI&ME)
Time: 3 Hours Max Marks: 60
Answer any FIVE questions
All questions carry EQUAL marks
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1. a) Draw the small-signal model for the MOS transistor. Briefly explain each component in
that?
b) Choose values of VGS = 1,2,3,4 and 5V, assume that the channel modulation parameter is
zero. Sketch to scale the output characteristics of an enhancement n-channel device if
VT = 0.7V and ID = 500µA when VGS = 5 Vin saturation.

2. a) Explain about the Bipolar simple current mirror with degeneration helper with necessary
equations.
b) Explain in details the MOS cascode current mirror with necessary equations.

3. a) Briefly explain the differential amplifiers.With necessary equation give the large signal
analysis of CMOS differential amplifiers.
b) Design a CMOS current mirror load differential amplifier.

4. a) Explain the concept of push-pull inverter with neat diagram. Derive the small signal
voltage gain and find the zero in plane.
b) Explain the slew rate and noise for p-channel differential amplifier with necessary
equations.

5. With neat sketch explain the following

a) Characteristics of Op-Amp
b) Classification of Op-Amp

6. a) With neat sketch and necessary equations explain the concept of nulling resistor
compensation of two stage CMOS Op-Amp.
b) Write a short note on design aspects of Op-Amp.

7. a) With neat sketch and necessary equations explain the Design aspect of a two stage open
loop comparator for slewing response.
b) Compare the dynamic latch with the NMOS and PMOS latches. What are the advantages
and disadvantages of the two latches?

8. Explain the following terms with neat sketch.

a) Switched capacitor comparators
b) Regenerative comparators
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