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Racearound KV
Racearound KV
Clock Pulse
tP
tPLH
tPHL
Now tPLH = tPHL = ∆t (Propagation delay time)
Potential Timing Problem in Flip Flops
Clock Skew: The clock signal which is applied to
all FFs may undergo varying degrees of delay caused
by wiring between components and hence arrive at
different FFs inputs at different times.
Race Around Condition
The race around condition occurs if t >> ∆t.
P
How we can avoid racearound condition?
We can avoid race around condition by the
following way.
1. If tP < ∆t.
2. By using edge triggering flipflop.
3. By using MasterSlave JK Flipflop.
Race Around in JK Flip Flop