module example(

input clk, input rst_n, input enable,

output reg [3:0] count0, output reg [3:0] count1
);

always @(posedge clk or negedge rst_n)

begin
if(!rst_n)
begin
count0<=4'b0;
count1<=4'b0;

end
else if (enable)
begin
if (count0==9)
begin
count0<=0;
count1<=count1+1'b1;

end
else
count0<=count0+1'b1;
end

end
endmodule

module testbench ();

reg rst,clk,enable;
wire [3:0]count0;
wire [3:0]count1;
example test(clk,rst,enable,count0,count1);
initial begin
#0 rst = 1;
#1 rst = 0;
#1;
rst=1;
enable=1;
clk =0;
forever #5 clk=~clk;
end

endmodule