16BEE0153

Gaurav Sharma
VLSI DESIGN
(EEE4028)
DIGITAL ASSIGNMENT
WITHOUT REDUCTION
CARRY

Bounding Box Area=50.49 um^2

OUTPUT IN XILINX

Latency=2133.333ns
Sum

Bounding box area=67.32 um^2

OUTPUT IN XILINX

Latency=2883.288ns
Cout

Bounding box area=9.9 um^2

OUTPUT IN XILINX

Latency=1133.333ns
Total bounding box area=50.49+67.32+9.9
=127.71 um^2
After Reduction
MagCAD

Bounding Box area=112.32um^2

OUTPUT IN XILINX

Result: Bounding box area is reduced to 112.32 um^2