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P-type SC at k will be working as a insulator.
Acceptor's
Energy Level (E,)
H0.01 ev
9.05 ev
Energy Bond Diagram
at 300K
In P-type SC every impurity atom will be receiving one e to
complete is co-valuect bounding (Hence p-type sc is also called
acceptors)
Po>N
* When p-type SC is at room temperature, a large number of co-
valent bonds will be broken and equal number of e+ and holes
are created and most of these e* will be moving from valence
bond into acceptor energy level to complete the bounding and
very few electrons is moving from VB to CB, so that hole
come in VB is for greater than e~ conc. in the CB and therefore
holes are majority carrier's and e? are minority carries,
e In p-type SC the current is dominated by holes.
p-type > Positive type
N-type — Negative type
¢ The condition for p-type SC is
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For G,
E,(T) = 0.785 - 2.23 x 104 T
For §,: E,(T) = 1.21 - 3.6 « 10¢T
(vy) Ripple factor of centre tapped full wave rectifier :
Ripple Factor : The AC component present in pulsating DC
output of rectifier is called ripple.
Riple factor is a measure of the amount of AC component or ripple
present in the output of rectifier.
Higher ripple factor indicates large amount of AC. Since AC
component is unwanted ripple factor should be smaller and ideally
it should be zero.
rms value of AC component
DC component
= TB), _ Te
T= al ona =yg7!
r= 0.483
(vi) Intrinsic Semiconductor : Crystalline structure at OK (diamond
structure) :
Cy +-Empty
Vs + Filled
Energy Bond Diagram
at OK
© The sharing of e+ with the neigh bouring atoms is called co-
valent bouding.
* Co-Valent bounding consists of two valence e+. P.Code:BEO4 SSC-JB : 2019 (Mains] : Test Series Wayeln maui os mend
© All valence e+ are in perfect co-valent banding.
¢ Intrivsec SC at OK will be working as an insulatory.
Crystalline Structure at 300 K :
Hole
Free &
Energy Bond Diagram
at 300 K
¢ When a co-valent bond is broken it will create le and 1 hole
(The e- will be moving from valence band into conduction band.
and becomes a free e and hole will remain in the valence
band)
¢ Free e is also called conduction band e-
¢ Hole is defined as deficiency of an e-in the broken covalent
bond.
¢ Hole is a carrier of current with a positive charge of +1.6 =
10-" C.
Always n=p
The condition for intensic SC is
n-p=n,
I=L 41
¢ Inthe SC e+ and holes always moves in the opposite direction.
but they contribute the current in the same direction.
¢ Free e“ full be moving in the conduction band and contributing
current at the same time hole will be moving in the VB, in the
opposite direction and contribute some current and the total
current is the sum of e- and hole current.
The conductivity of intrisic SC is
9,=nq H, tpq p, O/em
But n = nin intrisic SC
o,=niqth th)
6,0 n
But n, a T?
¢ Hence o, 1 with T as a non-linear variation
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Intrinsic Resistivi
Pi- G,
P= nqu.+n,] Om
¢ The main disadvantage of intrinsic SC is very law conductivity
and this is due to the smaller value of n.
¢ The only electronic device fabricated with intrinsic SC is PIN
diode (microwave switch).
2. (a) Forward Bias :
Vz, or,
+=
{1
IW
V=V,+V,
V=IR, +IR,
R, — Current limiting Resistance
Vp
L= le — 1
y,
L® Lem
n= 1 for c,, | Earlier methods
1 = 2 for Si of writing
1 = 1 for larger current | Latest
1 =2 for smaller current Notation.
When P-N Junction is forward Bias :
¢ The width of the depletion layer decreases.
¢ The barrier height reduces.
¢ Forward current is only due to majority carriers.
It, Saturation current gets doubled for every 5°C, as against
the thumbruts which indicates doubles for every 10°C.
¢ The forward current exponentially increases with the forward
voltage across the diode.
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P N
Soe rs
es! fo |
Minority Minority
Carriers Carriers
of P of N
In a forward biased diode the minority carriers of P and N
region will be moving away from the junction and they will
deposit in the device and the will not contribute any flow of
current.
2
¢ Ina forward biased diode the current up to the edge of depletion
layer is a drift current due to majority carriers.
¢ Forward current is a diffusion current forward current is due
to majority carriers and these majority carriers will be crossing
the junction from higher conc. to lower conc. i.e. due to the
property called diffusion.
¢ Forward current is due to excess minority carriers.
« The majority carriers of P and N regions are crossing the
junction and will become minority carriers and they are called
excess minority carriers.
¢ Forward current is controlled by excess minority carrier conc.
crossing the junction.
¢ Forward current flows from P to N.
¢ Forward current is due to excess minority carriers.
ngineersacedemy.ora ENTER CL MME www.engineersacademy.org> 11 2. b)
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Minimum current which pass through R, is
I
VM
s
Vg— Vo
Rs
30-11
Rs
R,
3. (a) Common Emitter Characteristic :
o—_____
iv
IA
Li th
Lt
1+ 10
ll
ll
ll mA
1.818 kQ
| __‘g
¢ Input Characteristic : A plot of I, V, V, while maintaining
V._ constant.
¢ For a BJT Base current V,, is due to compensating carriers
which enter the base region to maintain it neutral. P.Code:EE04 SSC-JE : 2019 (Mains) : Test EEsED> ENGINEERS ACADEMY | ACADEMY |
¢ 1, & Number of recombination.
¢ Number of recombination inside base is proportional to current I.
L
Vou Ver Vers
Vex
Vers > Ver > Vea
I, is neglisible for small V,, values but it increases rapidly
when V,, = V,
BE out in’
v. <* V for S, \
EE atin For npn
0.1 V for G, mp
I, also depends on V,,, due to early effect.
¢ Higher V,, will produce lower base current.
If Vz 1 > Vag(Veg — Veg) > Effective base width | >
Number of hole recombination | > I, L
¢ When V,, is increased input characteristic shifts towards right.
Output Characteristic :
¢ Aplot of I, V, 1,, while maintaining 1, constant.
I,
“| Saturation ——
Active
region
t La
Vig saturation cut-off region
Cut-off Region : Region where 1, is almost zero.
It list on
urve and to right of
Vv,
ce NCE sat
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If I,
then 1,= (1+ Bl,
For 8, 1, is in nA => I, will be neglisible in cut-off.
For G,, [,, is in pA = I, will be considerable.
¢ Therefore the make I, = 0 or make a G, transistor for off base
to emitter voltage should be slightly negative the value of V,,
for which [, becomes almost zero is called V,
BE cubaff
vy OV for S,
sem brow NPN
—0.1 V for G,
Saturation Region : Region where I, increases with V_,. It les
above I, = 0 curve and to the left of V,, = V,
CE sit"
Vv. 0.2 V for S,
st < en npn.
0.1 V for G,
Vax V,
cese — Transistor is in saturation region.
Active Region : Region where I, is approximately constant but
not exactly constant w.r.t. V',, it lies above I, = 0 curve and to
the right of Vi. = Vex sa
in active region I, = Bl, + + BI,
¢ The small increase in 1, w.r.t. V., in active region is because
of increase in B. B increase due to early effect.
¢ = Ifthe output characteristic are projected backward they intersect
the voltage axis at 0 single point (-V,, 0)
I
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Consider A and B
L-0
Slope ~ Veg att Va
I,
Slope = Ve
Consider B and C, slope
(b) N-Channel JFET :
G G
Channel
0
o.
JFET is a symmetrical device.
When JFET is open circuited channel cross sector area will be
maximum and channel current density is maximum.
Teoma ear e ENGINEERS ACADEMY | ACADEMY
2m Qn
TS = EIN = Ja2xd0? 50x10)
= 12.825 sec
vii) 9, = Oise |
wh _D__D
oe, S$ D> 2K
5x10?
= p50? xd2eloe ~ 9-102
9 = 0.01266) 1+ ee moog
07358 rad = 2 x 1000 x 0.07358 mm
= 147.164 mm __ ...First maximum deflection
(viii) & = Relative damping = 0.102
. me 7x 0.102
Gx) R= f= Ji-@.102" = 0.3221
b)
I, _ 2000
= 2a =
K,= [= 7 = 400
I, sind +1, cosd
R=0+2——
Where, 1, = 5 A (fall load)
_ 399 Sin36.869")+ 3x08 _ 96 59
% ratio error = Ka 199 = 0,3713%
180] 1,,cosd—[,sind
=F nl,
180] 8x 0.8 —3xsin(-36.8698°)
a 399x5
= 0.2355° = 14.13 P.Code:EE04 SSC-JE : 2019 (Mains) : Test EEsED> ENGINEERS ACADEMY | ACADEMY |
6. (a) For Balanced Load :
Let us consider the rms values of the currents and voltages to
prove that sum of two wattmeter gives total power consumed
by three phase load.
W, = 1, X Vig X coat, © Vig)
W,= I, * Vi, * cos(I, * V,.)
To find angle between (I, and V,,) and (I, and V,,) let us
draw phasor diagram. (Assuming load pf be cosh lagging)
Ve
and Veg = W-Va P.Code:EE04 SSC-JE : 2019 (Mains) : Test EEsED> ENGINEERS ACADEMY | ACADEMY |
WwW. V_T.cos(30° — 4)
and W, = LV, c08(30° + 6)
W, = V_Tcos(30° + 4)
W, + W, = V,I,[eos(30° — 6) + cos(30° + 6)]
V,I_[cos30° cos + sin30° sin @ + cos30°
cas — sin30° sino]
= 2V_T_cos30° cosh = 2v,t, Borg
Ww, + W, = 3 VI, cosp = total 3 phase power
Consider delta connected balanced load, as shown in the figure.
Ww,
R
Figure : Two wattmeter method for deita connected load
For W,, I= I, and V,. = Vip
For W,, 1,= I, and V,, = Vi
W, = 1,008, * Vig)
W,= IV,,cost], * V,,)
To find I, * V,, and I, * V,, let us draw phasor diagram.
Assume load having cosd lagging p.f.
W,+W, = V],[eos(30° — 0) + cos(30° + 4)]
3 V1, coso
= Total power consumed by three phase load.
For load having leading power factor, L,. will lead V, oh by angle
and it can be observed from phasor diagram that W, reading
and W, reading will get interchanged as 30° — > will become 30
° + @ and viceversa.
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Refer figure for leading power factor phasor diagram.
Ve
Vee
Figure : Star Connected Leading pf
) R, = 6600 Q
V= 120 V
T=20A
8 = 160°
Vv
e=- aL cong ix AM
R, dé
Where, K = Spring constant
Assuming nw constant throughout the operation.
K!
e=—%*P
R,
,_ 1dM
Where, K'= Kd
and P = VI cosb
160° = op li20«20x1]
K' = 440 degrees Q/W
If Meter constant = 20 W/degree then
— P
Meter constant P.Code:EE04 SSC-JE : 2019 (Mains) : Test EEsED> ENGINEERS ACADEMY | ACADEMY |
1 2400 _ oqe
8 = = = 120
At this time, R,=R,/+R,
440
120° = prX2400
R
R, = 8800 Q = 6600 + R
?
“ R, = 2200 Q Additional resistance required.
7. (a) W, = 5000 W, W, = -1000 W
@ cos} = co [ea
_, | ¥3[5000—(1000)]
- can eas
| ¥3x6000
= co | Se so0e = cos( 68.948}
= 0.3592 lag
Gi) Now capacitance is connected at the source which does not
affect the active power consumption.
W = 5000 — 1000 = 4000 W
Before connecting capacitor
W= BVI, cosd
A000
1. = \Bxa40x03502 ~ M612 A
For delta, Vin =V=40V
and 1, = VBI,
ie, L, = 8.4362 A
pa
v,
— ye _ 4400 _
l= Ty = gaagg = 21561 2
6 = 68.948°
X,, = Z,, sind = 48.6749 Q (inductive)
* ‘
=Z,, cosd = 18.7352 © (resistive)
ph Spt
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After connecting capacitor
W, = W = 4000 W
A
W,=0 W
But W, = V,I.cos (30° + 9) = 0
ie, 30° + 6 = 90°
ie, > = 60°
cosh = cos(60°) = 0.5 lagging
Due to pure capacitor, Ra remains same.
= 18. 7352 "2
x
- oS
Now, tang = Rn
Where, =X), = New reactance
x
ey = sh
tan(60%) = 737355
Xi, = 32.4503
Xi =X, — Xa = 48.6749 — 32.4503
= 16.226.Q
1
But Koon ~ CaO)
C= pe ae =~ 196.28 UF
2nx 50x 16.2246
(b) Maxweil’s Inductance Bridge :
Using this bridge, we can measure inductance by comparing it with
a standard variable self inductance arrangeed in bridge circuit as
shown in figure.
Detector P.Code:EE04 SSC-JE : 2019 (Mains) : Test EEsED> ENGINEERS ACADEMY | ACADEMY |
Vo Vy
ini,
iRAR, — (Ret1)-iR,
Figure (b) : Phasor diagram
Consider Maxwell's inductance bridge as shown in the figure. Two
branches consist of non-inductive resistances R, and R,. One of
the arms consists variable inductance with series resistance 1. The
remaining arm consists unknown inductance L..
At balance, we get condition as
— Rk _ RL
[R; +1) + jobs] ~ Ry + jal,
RIRHeL] = RR, + DHeL,]
RRjAoP L, = RAR, + 1) + joRL,
Equating imaginary terms, we can write
RL,= RL,
L,= Ris
Equating real terms, we can write,
R,R, = RR, + 1)
R= RRA
999
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