Datasheet IC 74LS Series-National-Semiconductor

54LS00/DM54LS00/DM74LS00 Quad 2-Input NAND Gates
June 1989
54LS00/DM54LS00/DM74LS00
Quad 2-Input NAND Gates
General Description Features
This device contains four independent gates each of which Y Alternate Military/Aerospace device (54LS00) is avail-
performs the logic NAND function. able. Contact a National Semiconductor Sales Office/
Distributor for specifications.
Connection Diagram
Dual-In-Line Package
TL/F/6439 – 1
Order Number 54LS00DMQB, 54LS00FMQB, 54LS00LMQB, DM54LS00J, DM54LS00W, DM74LS00M or DM74LS00N
See NS Package Number E20A, J14A, M14A, N14A or W14B
Function Table
Y e AB
Inputs Output
A B Y
L L H
L H H
H L H
H H L
H e High Logic Level
L e Low Logic Level
C1995 National Semiconductor Corporation TL/F/6439 RRD-B30M105/Printed in U. S. A.

Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required, Note: The ‘‘Absolute Maximum Ratings’’ are those values
please contact the National Semiconductor Sales beyond which the safety of the device cannot be guaran-
Office/Distributors for availability and specifications. teed. The device should not be operated at these limits. The
Supply Voltage 7V parametric values defined in the ‘‘Electrical Characteristics’’
table are not guaranteed at the absolute maximum ratings.
Input Voltage 7V
The ‘‘Recommended Operating Conditions’’ table will define
Operating Free Air Temperature Range the conditions for actual device operation.
DM54LS and 54LS b 55§ C to a 125§ C
DM74LS 0§ C to a 70§ C
Storage Temperature Range b 65§ C to a 150§ C
Recommended Operating Conditions

DM54LS00 DM74LS00
Symbol Parameter Units
Min Nom Max Min Nom Max
VCC Supply Voltage 4.5 5 5.5 4.75 5 5.25 V
VIH High Level Input Voltage 2 2 V
VIL Low Level Input Voltage 0.7 0.8 V
IOH High Level Output Current b 0.4 b 0.4 mA
IOL Low Level Output Current 4 8 mA
TA Free Air Operating Temperature b 55 125 0 70 §C
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Typ
Symbol Parameter Conditions Min Max Units
(Note 1)
VI Input Clamp Voltage VCC e Min, II e b18 mA b 1.5 V
VOH High Level Output VCC e Min, IOH e Max, DM54 2.5 3.4
V
Voltage VIL e Max
DM74 2.7 3.4
VOL Low Level Output VCC e Min, IOL e Max, DM54 0.25 0.4
Voltage VIH e Min
DM74 0.35 0.5 V
IOL e 4 mA, VCC e Min DM74 0.25 0.4
II Input Current @ Max VCC e Max, VI e 7V
0.1 mA
Input Voltage
IIH High Level Input Current VCC e Max, VI e 2.7V 20 mA
IIL Low Level Input Current VCC e Max, VI e 0.4V b 0.36 mA
IOS Short Circuit VCC e Max DM54 b 20 b 100
mA
Output Current (Note 2)
DM74 b 20 b 100
ICCH Supply Current with VCC e Max

0.8 1.6 mA
Outputs High
ICCL Supply Current with VCC e Max
2.4 4.4 mA
Outputs Low
Switching Characteristics at VCC e 5V and TA e 25§ C (See Section 1 for Test Waveforms and Output Load)
RL e 2 kX
Symbol Parameter CL e 15 pF CL e 50 pF Units
Min Max Min Max
tPLH Propagation Delay Time
3 10 4 15 ns
Low to High Level Output
tPHL Propagation Delay Time
3 10 4 15 ns
High to Low Level Output
Note 1: All typicals are at VCC e 5V, TA e 25§ C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
2
Physical Dimensions inches (millimeters)
Ceramic Leadless Chip Carrier Package (E)

Order Number 54LS00LMQB
NS Package Number E20A
3
14-Lead Ceramic Dual-In-Line Package (J)

Order Number 54LS00DMQB or DM54LS00J
NS Package Number J14A
14-Lead Small Outline Molded Package (M)

Order Number DM74LS00M
NS Package Number M14A
4
Physical Dimensions inches (millimeters) (Continued)
14-Lead Molded Dual-In-Line Package (N)

Order Number DM74LS00N
NS Package Number N14A
5
54LS00/DM54LS00/DM74LS00 Quad 2-Input NAND Gates
14-Lead Ceramic Flat Package (W)

Order Number 54LS00FMQB or DM54LS00W
NS Package Number W14B
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant support device or system whose failure to perform can
into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor
product or service without notice, and advises its customers to obtain the latest version of relevant information
to verify, before placing orders, that the information being relied on is current.
TI warrants performance of its semiconductor products and related software to the specifications applicable at
the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are
utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each
device is not necessarily performed, except those mandated by government requirements.
Certain applications using semiconductor products may involve potential risks of death, personal injury, or
severe property or environmental damage (“Critical Applications”).
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED

TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER
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Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use of TI
products in such applications requires the written approval of an appropriate TI officer. Questions concerning
potential risk applications should be directed to TI through a local SC sales office.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards should be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance, customer product design, software performance, or
infringement of patents or services described herein. Nor does TI warrant or represent that any license, either
express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property
right of TI covering or relating to any combination, machine, or process in which such semiconductor products
or services might be or are used.
Copyright  1996, Texas Instruments Incorporated

54LS02/DM54LS02/DM74LS02 Quad 2-Input NOR Gates
June 1989
Quad 2-Input NOR Gates
performs the logic NOR function. able. Contact a National Semiconductor Sales Office/
Distributor for specifications
Connection Diagram
TL/F/6441 – 1
Function Table
YeAaB
Inputs Output
A B Y
L L H
L H L
H L L
H H L
L e Low Logic Level

Input Voltage 7V

DM54LS02 DM74LS02
Typ
(Note 1)
V
Voltage VIL e Max
DM74 2.7 3.4
Voltage VIH e Min
DM74 0.35 0.5 V
0.1 mA
Input Voltage
mA
DM74 b 20 b 100

1.6 3.2 mA
Outputs High
2.8 5.4 mA
Outputs Low
RL e 2 kX
Min Max Min Max
13 18 ns
10 15 ns
2

3


4

5
54LS02/DM54LS02/DM74LS02 Quad 2-Input NOR Gates

LIFE SUPPORT POLICY
to the user.

Fran3ais Tel: (a49) 0-180-532 93 58 Tel: (852) 2737-1600
54LS03/DM54LS03/DM74LS03 Quad 2-Input NAND Gates with Open-Collector Outputs
June 1989
Quad 2-Input NAND Gates
with Open-Collector Outputs
General Description Pull-Up Resistor Equations
This device contains four independent gates each of which VCC (Min) b VOH
performs the logic NAND function. The open-collector out- RMAX e
N1 (IOH) a N2 (IIH)
puts require external pull-up resistors for proper logical op-
eration. VCC (Max) b VOL
RMIN e
IOL b N3 (IIL)
Features
Y Alternate Military/Aerospace device (54LS03) is avail- Where: N1 (IOH) e total maximum output high current for all
able. Contact a National Semiconductor Sales Office/ outputs tied to pull-up resistor
Distributor for specifications. N2 (IIH) e total maximum input high current for all
inputs tied to pull-up resistor
N3 (IIL) e total maximum input low current for all
Connection Diagram
TL/F/6344 – 1
Order Number 54LS03DMQB, 54LS03FMQB, 54LS03LMQB,
DM54LS03J, DM54LS03W, DM74LS03M or DM74LS03N
Function Table
Y e AB
Inputs Output
A B Y
L L H
L H H
H L H
H H L
L e Low Logic Level

Input Voltage 7V
Output Voltage 7V the conditions for actual device operation.
Operating Free Air Temperature Range

DM54LS03 DM74LS03
VOH High Level Output Voltage 5.5 5.5 V
Typ
(Note 1)
ICEX High Level Output VCC e Min, VO e 5.5V,
100 mA
Current VIL e Max
Voltage VIH e Min
DM74 0.35 0.5 V
0.1 mA
Input Voltage
0.8 1.6 mA
Outputs High
2.4 4.4 mA
Outputs Low
RL e 2 kX
Min Max Min Max
6 20 20 45 ns
3 15 4 20 ns
2
3


4


5
54LS03/DM54LS03/DM74LS03 Quad 2-Input NAND Gates with Open-Collector Outputs

LIFE SUPPORT POLICY
to the user.

Fran3ais Tel: (a49) 0-180-532 93 58 Tel: (852) 2737-1600
SN5404, SN54LS04, SN54S04,
SN7404, SN74LS04, SN74S04
HEX INVERTERS
SDLS029B – DECEMBER 1983 – REVISED FEBRUARY 2002
D Dependable Texas Instruments Quality and SN5404 . . . J PACKAGE

Reliability SN54LS04, SN54S04 . . . J OR W PACKAGE
SN7404 . . . D, N, OR NS PACKAGE
SN74LS04 . . . D, DB, N, OR NS PACKAGE
description SN74S04 . . . D OR N PACKAGE
(TOP VIEW)
These devices contain six independent inverters.
1A 1 14 VCC
1Y 2 13 6A
2A 3 12 6Y
2Y 4 11 5A
3A 5 10 5Y
3Y 6 9 4A
GND 7 8 4Y
SN5404 . . . W PACKAGE
(TOP VIEW)
1A 1 14 1Y
2Y 2 13 6A
2A 3 12 6Y
VCC 4 11 GND
3A 5 10 5Y
3Y 6 9 5A
4A 7 8 4Y
SN54LS04, SN54S04 . . . FK PACKAGE

(TOP VIEW)
VCC
NC
1Y
1A
6A
3 2 1 20 19
2A 4 18 6Y
NC 5 17 NC
2Y 6 16 5A
NC 7 15 NC
3A 8 14 5Y
9 10 11 12 13
3Y
4Y
4A
NC
GND
NC – No internal connection
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright  2002, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments On products compliant to MIL-PRF-38535, all parameters are tested
standard warranty. Production processing does not necessarily include unless otherwise noted. On all other products, production
testing of all parameters. processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

SN5404, SN54LS04, SN54S04,
SN7404, SN74LS04, SN74S04
HEX INVERTERS
ORDERING INFORMATION
ORDERABLE TOP-SIDE
TA PACKAGE†
PART NUMBER MARKING
Tube SN7404N SN7404N
PDIP – N Tube SN74LS04N SN74LS04N
Tube SN74S04N SN74S04N
Tube SN7404D 7404
Tube SN74LS04D
LS04
0°C to 70°C SOIC – D Tape and reel SN74LS04DR
Tube SN74S04D
S04
Tape and reel SN74S04DR
Tape and reel SN7404NSR SN7404
SOP – NS
Tape and reel SN74LS04NSR 74LS04
SSOP – DB Tape and reel SN74LS04DBR LS04
Tube SN5404J SN5404J
Tube SNJ5404J SNJ5404J
Tube SN54LS04J SN54LS04J
CDIP – J
Tube SN54S04J SN54S04J
Tube SNJ54LS04J SNJ54LS04J
–55°C to 125°C Tube SNJ54S04J SNJ54S04J
Tube SNJ5404W SNJ5404W
CFP – W Tube SNJ54LS04W SNJ54LS04W
Tube SNJ54S04W SNJ54S04W
Tube SNJ54LS04FK SNJ54LS04FK
LCCC – FK
Tube SNJ54S04FK SNJ54S04FK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
FUNCTION TABLE
(each inverter)
INPUT OUTPUT
A Y
H L
L H
2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN5404, SN54LS04, SN54S04,
SN7404, SN74LS04, SN74S04
HEX INVERTERS
logic diagram (positive logic)
1A 1Y
2A 2Y
3A 3Y
4A 4Y
5A 5Y
6A 6Y
Y=A

SN5404, SN54LS04, SN54S04,
SN7404, SN74LS04, SN74S04
HEX INVERTERS
schematics (each gate)

’04
VCC
4 kΩ 1.6 kΩ 130 Ω
Input A
Output Y
1 kΩ
GND
’LS04 ’S04
VCC VCC
20 kΩ 8 kΩ 120 Ω 2.8 kΩ 50 Ω
900 Ω
Input
A 3.5 kΩ Output
Input 4 kΩ Output Y
A Y
12 kΩ
250 Ω
500 Ω
3 kΩ
1.5 kΩ
GND
GND
Resistor values shown are nominal.

SN5404, SN54LS04, SN54S04,
SN7404, SN74LS04, SN74S04
HEX INVERTERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage, VI: ’04, ’S04 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
’LS04 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. This are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Voltage values are with respect to network ground terminal.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions

SN5404 SN7404
UNIT
MIN NOM MAX MIN NOM MAX
VCC Supply voltage 4.5 5 5.5 4.75 5 5.25 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
IOH High-level output current –0.4 –0.4 mA
IOL Low-level output current 16 16 mA
TA Operating free-air temperature – 55 125 0 70 °C
electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
SN5404 SN7404
PARAMETER TEST CONDITIONS‡ UNIT
MIN TYP§ MAX MIN TYP§ MAX
VIK VCC = MIN, II = – 12 mA – 1.5 – 1.5 V
VOH VCC = MIN, VIL = 0.8 V, IOH = –0.4 mA 2.4 3.4 2.4 3.4 V
VOL VCC = MIN, VIH = 2 V, IOL = 16 mA 0.2 0.4 0.2 0.4 V
II VCC = MAX, VI = 5.5 V 1 1 mA
IIH VCC = MAX, VI = 2.4 V 40 40 µA
IIL VCC = MAX, VI = 0.4 V – 1.6 – 1.6 mA
IOS¶ VCC = MAX –20 –55 –18 –55 mA
ICCH VCC = MAX, VI = 0 V 6 12 6 12 mA
ICCL VCC = MAX, VI = 4.5 V 18 33 18 33 mA
‡ For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
§ All typical values are at VCC = 5 V, TA = 25°C.
¶ Not more than one output should be shorted at a time.
switching characteristics, VCC = 5 V, TA = 25°C (see Figure 1)

SN5404
FROM TO SN7404
PARAMETER TEST CONDITIONS UNIT
(INPUT) (OUTPUT)
MIN TYP MAX
tPLH 12 22
A Y RL = 400 Ω
Ω, CL = 15 pF
F ns
tPHL 8 15

SN5404, SN54LS04, SN54S04,
SN7404, SN74LS04, SN74S04
HEX INVERTERS

SN54LS04 SN74LS04
UNIT
IOH High-level output current –0.4 –0.4 mA

otherwise noted)
SN54LS04 SN74LS04
PARAMETER TEST CONDITIONS† UNIT
MIN TYP‡ MAX MIN TYP‡ MAX
VIK VCC = MIN, II = – 18 mA – 1.5 – 1.5 V
VOH VCC = MIN, VIL = MAX, IOH = –0.4 mA 2.5 3.4 2.7 3.4 V
IOL = 4 mA 0.25 0.4 0.4
VOL VCC = MIN
MIN, VIH = 2 V V
IOL = 8 mA 0.25 0.5
II VCC = MAX, VI = 7 V 0.1 0.1 mA
IIL VCC = MAX, VI = 0.4 V – 0.4 – 0.4 mA
IOS§ VCC = MAX –20 –100 –20 –100 mA
ICCH VCC = MAX, VI = 0 V 1.2 2.4 1.2 2.4 mA
ICCL VCC = MAX, VI = 4.5 V 3.6 6.6 3.6 6.6 mA
† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
‡ All typical values are at VCC = 5 V, TA = 25°C.
§ Not more than one output should be shorted at a time and the duration of the short-circuit should not exceed one second.

SN54LS04
FROM TO SN74LS04
(INPUT) (OUTPUT)
MIN TYP MAX
tPLH 9 15
A Y RL = 2 kΩ
kΩ, CL = 15 pF
F ns
tPHL 10 15

SN5404, SN54LS04, SN54S04,
SN7404, SN74LS04, SN74S04
HEX INVERTERS

SN54S04 SN74S04
UNIT
IOH High-level output current –1 –1 mA

otherwise noted)
SN54S04 SN74S04
PARAMETER TEST CONDITIONS† UNIT
VIK VCC = MIN, II = – 18 mA – 1.2 – 1.2 V
VOH VCC = MIN, VIL = 0.8 V, IOH = –1 mA 2.5 3.4 2.7 3.4 V
VOL VCC = MIN, VIH = 2 V, IOL = 20 mA 0.5 0.5 V
II VCC = MAX, VI = 5.5 V 1 1 mA
IIL VCC = MAX, VI = 0.5 V –2 –2 mA
IOS§ VCC = MAX –40 –100 –40 –100 mA
ICCH VCC = MAX, VI = 0 V 15 24 15 24 mA
ICCL VCC = MAX, VI = 4.5 V 30 54 30 54 mA
§ Not more than one output should be shorted at a time and the duration of the short-circuit should not exceed one second.

SN54S04
FROM TO SN74S04
(INPUT) (OUTPUT)
MIN TYP MAX
tPLH 3 4.5
A Y RL = 280 Ω
Ω, CL = 15 pF
F ns
tPHL 3 5
tPLH 4.5
A Y RL = 280 Ω
Ω, CL = 50 pF
F ns
tPHL 5

SN5404, SN54LS04, SN54S04,
SN7404, SN74LS04, SN74S04
HEX INVERTERS
PARAMETER MEASUREMENT INFORMATION

SERIES 54/74 AND 54S/74S DEVICES
VCC
Test RL
Test Point S1
Point VCC
From Output
VCC Under Test (see Note B)
RL CL
From Output RL (see Note A) 1 kΩ
Under Test (see Note B) From Output Test
CL Under Test Point
(see Note A) CL
(see Note A) S2
LOAD CIRCUIT LOAD CIRCUIT LOAD CIRCUIT

FOR 2-STATE TOTEM-POLE OUTPUTS FOR OPEN-COLLECTOR OUTPUTS FOR 3-STATE OUTPUTS
3V
High-Level Timing
Pulse 1.5 V 1.5 V Input 1.5 V
0V
tw th
tsu
3V
Low-Level Data
1.5 V 1.5 V 1.5 V 1.5 V
Pulse Input
0V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PULSE DURATIONS SETUP AND HOLD TIMES
Output 3V
Control
(low-level 1.5 V 1.5 V
3V
Input 1.5 V 1.5 V enabling) 0V
0V tPZL tPLZ
tPLH tPHL
Waveform 1 ≈1.5 V
In-Phase VOH (see Notes C 1.5 V
Output 1.5 V 1.5 V and D) VOL + 0.5 V
(see Note D) VOL
VOL
tPZH tPHZ
tPHL tPLH
VOH
Out-of-Phase VOH Waveform 2 VOH – 0.5 V
(see Notes C 1.5 V
Output 1.5 V 1.5 V ≈1.5 V
(see Note D) and D)
VOL
PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance.

B. All diodes are 1N3064 or equivalent.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL.
E. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω; tr and tf ≤ 7 ns for Series
54/74 devices and tr and tf ≤ 2.5 ns for Series 54S/74S devices.
F. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms

SN5404, SN54LS04, SN54S04,
SN7404, SN74LS04, SN74S04
HEX INVERTERS

SERIES 54LS/74LS DEVICES
VCC
Test RL
Test Point S1
Point VCC
From Output
RL CL
CL Under Test Point
(see Note A) CL
(see Note A) S2

3V
High-Level Timing
0V
tw th
tsu
3V
Low-Level Data
1.3 V 1.3 V 1.3 V 1.3 V
Pulse Input
0V
Output 3V
Control
3V
Input enabling)
1.3 V 1.3 V 0V
0V tPZL tPLZ
tPLH tPHL
In-Phase
Waveform 1 ≈1.5 V
VOH (see Notes C 1.3 V
Output 1.3 V 1.3 V VOL + 0.5 V
and D)
(see Note D) VOL VOL
tPZH tPHZ
tPHL tPLH
VOH
Out-of-Phase Waveform 2 VOH – 0.5 V
VOH
(see Notes C 1.3 V
Output 1.3 V 1.3 V
and D) ≈1.5 V
(see Note D) VOL
E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples.
F. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω, tr ≤ 1.5 ns, tf ≤ 2.6 ns.
G. The outputs are measured one at a time with one input transition per measurement.

IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third–party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265

54LS05/DM54LS05/DM74LS05 Hex Inverters with Open-Collector Outputs
June 1989
54LS05/DM54LS05/DM74LS05 Hex Inverters

with Open-Collector Outputs
General Description Pull-Up Resistor Equations
This device contains six independent gates each of which VCC (Min) b VOH
performs the logic INVERT function. The open-collector out- RMAX e
N1 (IOH) a N2 (IIH)
puts require external pull-up resistors for proper logical op-
eration. VCC (Max) b VOL
RMIN e
IOL b N3 (IIL)
Features Where: N1 (IOH) e total maximum output high current for all
Y Alternate Military/Aerospace device (54LS05) is avail- outputs tied to pull-up resistor
able. Contact a National Semiconductor Sales Office/
N2 (IIH) e total maximum input high current for all
N3 (IIL) e total maximum input low current for all
Connection Diagram
TL/F/6346 – 1
Order Number 54LS05DMQB, 54LS05FMQB, DM54LS05J, DM54LS05W, DM74LS05M or DM74LS05N
Function Table
YeA
Input Output
A Y
L H
H L
L e Low Logic Level

Input Voltage 7V
Output Voltage 7V the conditions for actual device operation.

DM54LS05 DM74LS05
VOH High Level Output Voltage 5.5 5.5 V
Typ
(Note 1)
ICEX High Level Output VCC e Min, VO e 5.5V
100 mA
Current VIL e Max
VOL Low Level Output VCC e Min, IOL e Max DM54 0.25 0.4
Voltage VIH e Min
DM74 0.35 0.5 V
II Input Current @ VCC e Max, VI e 7V
0.1 mA
Max Input Voltage
1.2 2.4 mA
Outputs High
3.6 6.6 mA
Outputs Low
RL e 2 kX
Min Max Min Max
6 20 20 45 ns
3 15 4 20 ns
2


3
54LS05/DM54LS05/DM74LS05 Hex Inverters with Open-Collector Outputs


LIFE SUPPORT POLICY
to the user.

Fran3ais Tel: (a49) 0-180-532 93 58 Tel: (852) 2737-1600
SN54LS06, SN74LS06, SN74LS16
HEX INVERTER BUFFERS/DRIVERS
The SN74LS16 is obsolete
and is no longer supplied. WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS
SDLS020B – MAY 1990 – REVISED JANUARY 2002
D Convert TTL Voltage Levels to MOS Levels SN54LS06 . . . J PACKAGE
D High Sink-Current Capability

SN74LS06, SN74LS16 . . . D, N, OR NS PACKAGE
(TOP VIEW)
D Input Clamping Diodes Simplify System
Design 1A 1 14 VCC
D Open-Collector Driver for Indicator Lamps 1Y 2 13 6A
and Relays 2A 3 12 6Y
D Inputs Fully Compatible With Most TTL
2Y
3A
4 11 5A
5 10 5Y
Circuits
3Y 6 9 4A
description GND 7 8 4Y
These hex inverter buffers/drivers feature

SN54LS06 . . . FK PACKAGE
high-voltage open-collector outputs to interface
(TOP VIEW)
with high-level circuits (such as MOS), or for
VCC
NC
1Y
1A
6A
driving high-current loads, and also are character-
ized for use as inverter buffers for driving TTL
inputs. The ’LS06 devices have a rated output 3 2 1 20 19
2A 4 18 6Y
voltage of 30 V, and the SN74LS16 has a rated NC 5 17 NC
output voltage of 15 V. The maximum sink current 2Y 6 16 5A
for the SN54LS06 is 30 mA, and for the NC
NC 7 15
SN74LS06 and SN74LS16 is 40 mA. 14 5Y
3A 8
9 10 11 12 13
These devices are compatible with most TTL
families. Inputs are diode-clamped to minimize
3Y
4Y
4A
NC
GND
transmission effects, which simplifies design.
Typical power dissipation is 175 mW and average
propagation delay time is 8 ns.
ORDERABLE TOP-SIDE
TA PACKAGE†
PART NUMBER MARKING
Tube SN74LS06D
SOIC – D LS06
Tape and reel SN74LS06DR
0°C to 70°C SOP – NS Tape and reel SN74LS06NSR 74LS06
SSOP – DB Tape and reel SN74LS06DBR LS06
PDIP – N Tube SN74LS06N SN74LS06N
Tube SN54LS06J SN54LS06J
CDIP – J
–55°C to 125°C Tube SNJ54LS06J SNJ54LS06J
LCCC – FK Tube SNJ54LS06FK SNJ54LS06FK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB
design guidelines are available at www.ti.com/sc/package.

WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS and is no longer supplied.
logic diagram (positive logic)
1 2 1Y
1A
3 4 2Y
2A
5 6
3A 3Y
9 8
4A 4Y
11 10
5A 5Y
13 12
6A 6Y
Pin numbers shown are for the D, J, N, and NS packages.
schematic (each gate)

VCC
9 kΩ 2.5 kΩ
15 kΩ 1 kΩ
2.5 kΩ Output
Input
2 kΩ 2 kΩ
GND

Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Output voltage, VO (see Notes 1 and 2): SN54LS06, SN74LS06 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 V
SN74LS16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
NOTES: 1. All voltage values are with respect to GND.
2. This is the maximum voltage that should be applied to any output when it is in the off state.

SN74LS06
SN54LS06
SN74LS16 UNIT
’LS06 30 30 V
VOH High level output voltage
High-level
SN74LS16 15 V
TA Operating free-air temperature –55 125 0 70 °C

otherwise noted)
SN74LS06
SN54LS06
PARAMETER TEST CONDITIONS‡ SN74LS16 UNIT
MIN TYP§ MAX MIN TYP§ MAX
VIK VCC = MIN, II = –12 mA –1.5 –1.5 V
’LS06, VOH = 30 V 0.25 0.25
IOH VCC = MIN
MIN, VIL = 0
0.8
8V V
SN74LS16, VOH = 15 V 0.25
IOL = 16 mA 0.25 0.4 0.25 0.4
VOL VCC = MIN, VIH = 2 V IOL = 30 mA 0.7 V
IOL = 40 mA 0.7
II VCC = MAX, VI = 7 V 1 1 mA
IIL VCC = MAX, VI = 0.4 V –0.2 –0.2 mA
ICCH VCC = MAX 18 18 mA
ICCL VCC = MAX 60 60 mA
‡ For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
§ All typical values are at VCC = 5 V, and TA = 25°C.

WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS and is no longer supplied.

FROM TO
PARAMETER TEST CONDITIONS MIN MAX UNIT
(INPUT) (OUTPUT)
tPLH 7 15
A Y RL = 110 Ω
Ω, CL = 15 pF ns
tPHL 10 20


VCC
Test RL
Test Point S1
Point VCC
From Output
RL CL
CL Under Test Point
(see Note A) CL
(see Note A) S2

3V
High-Level Timing
0V
tw th
tsu
3V
Low-Level Data
1.3 V 1.3 V 1.3 V 1.3 V
Pulse Input
0V
Output 3V
Control
3V
Input enabling)
1.3 V 1.3 V 0V
0V tPZL tPLZ
tPLH tPHL
In-Phase
Waveform 1 ≈1.5 V
VOH (see Notes C 1.3 V
Output 1.3 V 1.3 V VOL + 0.5 V
and D)
(see Note D) VOL VOL
tPZH tPHZ
tPHL tPLH
VOH
Out-of-Phase Waveform 2 VOH – 0.5 V
VOH
(see Notes C 1.3 V
Output 1.3 V 1.3 V
and D) ≈1.5 V
(see Note D) VOL
E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples.
F. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω, tr ≤ 1.5 ns, tf ≤ 2.6 ns.
G. The outputs are measured one at a time with one input transition per measurement.

IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third–party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Mailing Address:
Texas Instruments
Dallas, Texas 75265

SN5407, SN5417, SN7407, SN7417
HEX BUFFERS/DRIVERS
WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS
SDLS032D – DECEMBER 1983 – REVISED AUGUST 2001
D Convert TTL Voltage Levels to MOS Levels SN5407, SN5417 . . . J OR W PACKAGE

SN7417 . . . D OR N PACKAGE
D Input Clamping Diodes Simplify System (TOP VIEW)
Design
D Open-Collector Driver for Indicator Lamps
1A
1Y
1
2
14
13
VCC
6A
and Relays
2A 3 12 6Y
D Inputs Fully Compatible With Most TTL 2Y 4 11 5A
Circuits 3A 5 10 5Y
3Y 6 9 4A
description GND 4Y
7 8
These TTL hex buffers/drivers feature
high-voltage open-collector outputs for interfacing
with high-level circuits (such as MOS) or for driving high-current loads (such as lamps or relays), and also are
characterized for use as buffers for driving TTL inputs. The SN5407 and SN7407 have minimum breakdown
voltages of 30 V, and the SN5417 and SN7417 have minimum breakdown voltages of 15 V. The maximum sink
current is 30 mA for the SN5407 and SN5417 and 40 mA for the SN7407 and SN7417.
These devices perform Boolean function Y = A in positive logic.
These circuits are completely compatible with most TTL families. Inputs are diode clamped to minimize
transmission-line effects, which simplifies design. Typical power dissipation is 145 mW, and average
ORDERABLE TOP-SIDE
TA PACKAGE†
PART NUMBER MARKING
Tube SN7407D
7407
Tape and reel SN7407DR
SOIC – D
Tube SN7417D
7417
0°C to 70°C Tape and reel SN7417DR
SN7407N SN7407N
PDIP – N Tube
SN7417N SN7417N
SOP – NS Tape and reel SN7407NSR SN7407
SNJ5407J SNJ5407J
CDIP – J Tube
SNJ5417J SNJ5417J
55°C to 125°C
–55°C
SNJ5407W SNJ5407W
CFP – W Tube
SNJ5417W SNJ5417W
logic diagram, each buffer/driver (positive logic)
A Y

SN5407, SN5417, SN7407, SN7417
HEX BUFFERS/DRIVERS
schematic
VCC
6 kΩ 3.4 kΩ 1.6 kΩ
Input A
Output Y
100 Ω
1 kΩ
GND
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 5.5 V
Output voltage, VO (see Notes 1 and 2): SN5407, SN7407 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 V
SN5417, SN7417 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W

MIN NOM MAX UNIT
SN5407, SN5417 4.5 5 5.5
VCC Supply voltage V
SN7407, SN7417 4.75 5 5.25
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
SN5407, SN7407 30
High-level V
SN5417, SN7417 15
SN5407, SN5417 30
IOL Low level output current
Low-level mA
SN7407, SN7417 40
SN5407, SN5417 –55 125
TA Operating free-air
free air temperature °C
SN7407, SN7417 0 70

SN5407, SN5417, SN7407, SN7417
HEX BUFFERS/DRIVERS

otherwise noted)
PARAMETER TEST CONDITIONS† MIN TYP‡ MAX UNIT
VIK VCC = MIN, II = –12 mA –1.5 V
VOH = 30 V (SN5407, SN7407) 0.25
IOH VCC = MIN
MIN, VIH = 2 V mA
VOH = 15 V (SN5417, SN7417) 0.25
IOL = 16 mA 0.4
VOL VCC = MIN, VIL = 0.8 V IOL = 30 mA (SN5407, SN5417) 0.7 V
IOL = 40 mA (SN7407, SN7417) 0.7
II VCC = MAX, VI = 5.5 V 1 mA
IIH VCC = MAX, VIH = 2.4 V 40 µA
IIL VCC = MAX, VIL = 0.4 V –1.6 mA

FROM TO
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
(INPUT) (OUTPUT)
tPLH 6 10
A Y RL = 110 Ω
Ω, CL = 15 pF ns
tPHL 20 30
tPLH 15
A Y RL = 150 Ω,
Ω CL = 50 pF ns
tPHL 26

SN5407, SN5417, SN7407, SN7417
HEX BUFFERS/DRIVERS

VCC
RL
From Output
Test Point
Under Test
CL
(see Note A)
LOAD CIRCUIT
3V
Input 1.5 V 1.5 V
0V
tPLH tPHL
VOH
High-Level In-Phase
1.5 V 1.5 V 1.5 V 1.5 V
Pulse Output
VOL
tw tPHL tPLH
Low-Level VOH
Out-of-Phase
Pulse 1.5 V 1.5 V 1.5 V 1.5 V
Output
VOL
PULSE WIDTHS PROPAGATION DELAY TIMES

B. In the examples above, the phase relationships between inputs and outputs have been chosen arbitrarily.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 7 ns, tf ≤ 7 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms

SN5407, SN5417, SN7407, SN7417
HEX BUFFERS/DRIVERS
D Convert TTL Voltage Levels to MOS Levels SN5407, SN5417 . . . J OR W PACKAGE

SN7417 . . . D OR N PACKAGE
D Input Clamping Diodes Simplify System (TOP VIEW)
Design
D Open-Collector Driver for Indicator Lamps
1A
1Y
1
2
14
13
VCC
6A
and Relays
2A 3 12 6Y
D Inputs Fully Compatible With Most TTL 2Y 4 11 5A
Circuits 3A 5 10 5Y
3Y 6 9 4A
description GND 4Y
7 8
These TTL hex buffers/drivers feature
high-voltage open-collector outputs for interfacing
with high-level circuits (such as MOS) or for driving high-current loads (such as lamps or relays), and also are
characterized for use as buffers for driving TTL inputs. The SN5407 and SN7407 have minimum breakdown
voltages of 30 V, and the SN5417 and SN7417 have minimum breakdown voltages of 15 V. The maximum sink
current is 30 mA for the SN5407 and SN5417 and 40 mA for the SN7407 and SN7417.
These devices perform Boolean function Y = A in positive logic.
These circuits are completely compatible with most TTL families. Inputs are diode clamped to minimize
transmission-line effects, which simplifies design. Typical power dissipation is 145 mW, and average
ORDERABLE TOP-SIDE
TA PACKAGE†
PART NUMBER MARKING
Tube SN7407D
7407
Tape and reel SN7407DR
SOIC – D
Tube SN7417D
7417
0°C to 70°C Tape and reel SN7417DR
SN7407N SN7407N
PDIP – N Tube
SN7417N SN7417N
SOP – NS Tape and reel SN7407NSR SN7407
SNJ5407J SNJ5407J
CDIP – J Tube
SNJ5417J SNJ5417J
55°C to 125°C
–55°C
SNJ5407W SNJ5407W
CFP – W Tube
SNJ5417W SNJ5417W
logic diagram, each buffer/driver (positive logic)
A Y

SN5407, SN5417, SN7407, SN7417
HEX BUFFERS/DRIVERS
schematic
VCC
6 kΩ 3.4 kΩ 1.6 kΩ
Input A
Output Y
100 Ω
1 kΩ
GND
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 5.5 V
Output voltage, VO (see Notes 1 and 2): SN5407, SN7407 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 V
SN5417, SN7417 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W

MIN NOM MAX UNIT
SN5407, SN5417 4.5 5 5.5
VCC Supply voltage V
SN7407, SN7417 4.75 5 5.25
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
SN5407, SN7407 30
High-level V
SN5417, SN7417 15
SN5407, SN5417 30
IOL Low level output current
Low-level mA
SN7407, SN7417 40
SN5407, SN5417 –55 125
TA Operating free-air
free air temperature °C
SN7407, SN7417 0 70

SN5407, SN5417, SN7407, SN7417
HEX BUFFERS/DRIVERS

otherwise noted)
PARAMETER TEST CONDITIONS† MIN TYP‡ MAX UNIT
VIK VCC = MIN, II = –12 mA –1.5 V
VOH = 30 V (SN5407, SN7407) 0.25
IOH VCC = MIN
MIN, VIH = 2 V mA
VOH = 15 V (SN5417, SN7417) 0.25
IOL = 16 mA 0.4
VOL VCC = MIN, VIL = 0.8 V IOL = 30 mA (SN5407, SN5417) 0.7 V
IOL = 40 mA (SN7407, SN7417) 0.7
II VCC = MAX, VI = 5.5 V 1 mA
IIH VCC = MAX, VIH = 2.4 V 40 µA
IIL VCC = MAX, VIL = 0.4 V –1.6 mA

FROM TO
(INPUT) (OUTPUT)
tPLH 6 10
A Y RL = 110 Ω
Ω, CL = 15 pF ns
tPHL 20 30
tPLH 15
A Y RL = 150 Ω,
Ω CL = 50 pF ns
tPHL 26

SN5407, SN5417, SN7407, SN7417
HEX BUFFERS/DRIVERS

VCC
RL
From Output
Test Point
Under Test
CL
(see Note A)
LOAD CIRCUIT
3V
Input 1.5 V 1.5 V
0V
tPLH tPHL
VOH
High-Level In-Phase
1.5 V 1.5 V 1.5 V 1.5 V
Pulse Output
VOL
tw tPHL tPLH
Low-Level VOH
Out-of-Phase
Pulse 1.5 V 1.5 V 1.5 V 1.5 V
Output
VOL
PULSE WIDTHS PROPAGATION DELAY TIMES

B. In the examples above, the phase relationships between inputs and outputs have been chosen arbitrarily.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 7 ns, tf ≤ 7 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms

IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its products to the specifications applicable at the time of sale in accordance with
TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary
to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except
those mandated by government requirements.
Customers are responsible for their applications using TI components.
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
products or services might be or are used. TI’s publication of information regarding any third party’s products
or services does not constitute TI’s approval, license, warranty or endorsement thereof.
alteration and is accompanied by all associated warranties, conditions, limitations and notices. Representation
or reproduction of this information with alteration voids all warranties provided for an associated TI product or
service, is an unfair and deceptive business practice, and TI is not responsible nor liable for any such use.
Resale of TI’s products or services with statements different from or beyond the parameters stated by TI for
that product or service voids all express and any implied warranties for the associated TI product or service,
is an unfair and deceptive business practice, and TI is not responsible nor liable for any such use.
Also see: Standard Terms and Conditions of Sale for Semiconductor Products. www.ti.com/sc/docs/stdterms.htm
Mailing Address:
Texas Instruments
Dallas, Texas 75265

54LS08/DM54LS08/DM74LS08 Quad 2-Input AND Gates
June 1989

performs the logic AND function. able. Contact a National Semiconductor Sales Office/
Connection Diagram
TL/F/6347 – 1
Function Table
Y e AB
Inputs Output
A B Y
L L L
L H L
H L L
H H H
L e Low Logic Level

Input Voltage 7V

DM54LS08 DM74LS08
Typ
(Note 1)
V
Voltage VIH e Min DM74 2.7 3.4
Voltage VIL e Max DM74 0.35 0.5 V
0.1 mA
Input Voltage
mA
Output Current (Note 2) DM74 b 20 b 100
2.4 4.8 mA
Outputs High
4.4 8.8 mA
Outputs Low
RL e 2 kX
Min Max Min Max
4 13 6 18 ns
3 11 5 18 ns
2
3


4


5

LIFE SUPPORT POLICY
to the user.

Fran3ais Tel: (a49) 0-180-532 93 58 Tel: (852) 2737-1600
SN54ALS09, SN74ALS09
QUADRUPLE 2-INPUT POSITIVE-AND GATES
WITH OPEN-COLLECTOR OUTPUTS
SDAS084B – APRIL 1982 – REVISED DECEMBER 1994
• Package Options Include Plastic SN54ALS09 . . . J PACKAGE

Small-Outline (D) Packages, Ceramic Chip SN74ALS09 . . . D OR N PACKAGE
(TOP VIEW)
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
1A 1 14 VCC
description 1B 2 13 4B
1Y 3 12 4A
These devices contain four independent 2-input 2A 4 11 4Y
positive-AND gates. They perform the Boolean 2B 5 10 3B
functions Y = A • B or Y = A + B in positive logic. 2Y 6 9 3A
The open-collector outputs require pullup GND 7 8 3Y
resistors to perform correctly. These outputs may
be connected to other open-collector outputs to
SN54ALS09 . . . FK PACKAGE
implement active-low wired-OR or active-high (TOP VIEW)
wired-AND functions. Open-collector devices are
VCC
often used to generate higher VOH levels.
NC
1B
1A
4B
The SN54ALS09 is characterized for operation
3 2 1 20 19
over the full military temperature range of – 55°C 1Y 4 18 4A
to 125°C. The SN74ALS09 is characterized for NC 5 17 NC
operation from 0°C to 70°C. 16
2A 6 4Y
NC 7 15 NC
FUNCTION TABLE
2B 8 14 3B
(each gate) 9 10 11 12 13
INPUTS OUTPUT
GND
2Y
3Y
3A
NC
A B Y
H H H
L X L NC – No internal connection
X L L
logic symbol† logic diagram (positive logic)

1 1
1A & 3 1A 3
2 1Y 2 1Y
1B 1B
4 4
2A 6 2A 6
5 2Y 5 2Y
2B 2B
9
3A 8 9
10 3Y 3A 8
3B 10 3Y
12 3B
4A 11 12
13 4Y 4A 11
4B 13 4Y
4B
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Off-state output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Operating free-air temperature range, TA: SN54ALS09 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
SN74ALS09 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C

SN54ALS09 SN74ALS09
UNIT
VOH High-level output voltage 5.5 5.5 V

otherwise noted)
SN54ALS09 SN74ALS09
VIK VCC = 4.5 V, II = –18 mA –1.5 –1.5 V
IOL = 4 mA 0.25 0.4 0.25 0.4
VOL VCC = 4 5V
4.5 V
IOL = 8 mA 0.35 0.5
II VCC = 5.5 V, VI = 7 V 0.1 0.1 mA
IIH VCC = 5.5 V, VI = 2.7 V 20 20 µA
IIL VCC = 5.5 V, VI = 0.4 V – 0.1 – 0.1 mA
IOH VCC = 4.5 V, VOH = 5.5 V 0.1 0.1 mA
ICCH VCC = 5.5 V, VI = 4.5 V 1.35 2.4 1.35 2.4 mA
ICCL VCC = 5.5 V, VI = 0 2.2 4 2.2 4 mA
switching characteristics (see Figure 1)

VCC = 4.5 V to 5.5 V,
CL = 50 pF,
FROM TO RL = 2 kΩ,
PARAMETER
(INPUT) (OUTPUT) TA = MIN to MAX§ UNIT
SN54ALS09 SN74ALS09
MIN MAX MIN MAX
tPLH 20 69 23 54
A or B Y ns
tPHL 5 23 5 15
§ For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.


SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
7V
VCC RL = R1 = R2
S1
RL
R1
From Output Test From Output Test From Output Test
Under Test Point Under Test Point Under Test Point
CL RL CL
CL R2
(see Note A) (see Note A)
(see Note A)
LOAD CIRCUIT FOR

BI-STATE LOAD CIRCUIT LOAD CIRCUIT
TOTEM-POLE OUTPUTS FOR OPEN-COLLECTOR OUTPUTS FOR 3-STATE OUTPUTS
Timing 3.5 V High-Level 3.5 V

Input 1.3 V Pulse 1.3 V 1.3 V
0.3 V 0.3 V
th tw
tsu
3.5 V 3.5 V
Data Low-Level
Input 1.3 V 1.3 V 1.3 V 1.3 V
Pulse
0.3 V 0.3 V

SETUP AND HOLD TIMES PULSE DURATIONS
3.5 V
Output
Control 1.3 V 1.3 V
(low-level
enabling) 0.3 V 3.5 V
tPZL Input 1.3 V 1.3 V
tPLZ
[3.5 V 0.3 V
tPHL
Waveform 1 tPLH
S1 Closed 1.3 V
In-Phase VOH
(see Note B) 1.3 V 1.3 V
VOL Output
tPHZ 0.3 V VOL
tPZH tPLH
VOH tPHL
Waveform 2 VOH
Out-of-Phase
S1 Open 1.3 V 0.3 V 1.3 V 1.3 V
Output
(see Note B)
[0 V (see Note C) VOL

ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS PROPAGATION DELAY TIMES

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one transition per measurement.

IMPORTANT NOTICE
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF

DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

54LS10/DM54LS10/DM74LS10 Triple 3-Input NAND Gates
June 1989
Triple 3-Input NAND Gates
This device contains three independent gates each of which Y Alternate Military/Aerospace device (54LS10) is avail-
Connection Diagram
TL/F/6349 – 1
Function Table
Y e ABC
Inputs Output
A B C Y
X X L H
X L X H
L X X H
H H H L
L e Low Logic Level
X e Either Low or High Logic Level

Input Voltage 7V

DM54LS10 DM74LS10
Typ
(Note 1)
V
Voltage VIL e Max
DM74 2.7 3.4
Voltage VIH e Min
DM74 0.35 0.5 V
0.1 mA
Input Voltage
mA
DM74 b 20 b 100

0.6 1.2 mA
Outputs High
1.8 3.3 mA
Outputs Low
RL e 2 kX
Min Max Min Max
3 10 4 15 ns
3 10 4 15 ns
2
3


4


5
54LS10/DM54LS10/DM74LS10 Triple 3-Input NAND Gates

LIFE SUPPORT POLICY
to the user.

Fran3ais Tel: (a49) 0-180-532 93 58 Tel: (852) 2737-1600
54LS11/DM54LS11/DM74LS11 Triple 3-Input AND Gates
June 1989

This device contains three independent gates each of which Y Alternate military/aerospace device (54LS11) is avail-
Connection Diagram
TL/F/6350 – 1
Function Table
Y e ABC
Inputs Output
A B C Y
X X L L
X L X L
L X X L
H H H H
L e Low Logic Level

Input Voltage 7V

DM54LS11 DM74LS11
Typ
(Note 1)
VOH High Level Output VCC e Min, IOH e Max DM54 2.5 3.4
V
0.1 mA
Input Voltage
mA
1.8 3.6 mA
Outputs High
3.3 6.6 mA
Outputs Low
RL e 2 kX
Min Max Min Max
4 13 6 18 ns
3 11 5 18 ns
2
3


4


5

LIFE SUPPORT POLICY
to the user.

Fran3ais Tel: (a49) 0-180-532 93 58 Tel: (852) 2737-1600
IMPORTANT NOTICE


IMPORTANT NOTICE


54LS14/DM74LS14 Hex Inverters with Schmitt Trigger Inputs
June 1989
54LS14/DM74LS14 Hex Inverters

with Schmitt Trigger Inputs
General Description
This device contains six independent gates each of which
performs the logic INVERT function. Each input has hyster-
esis which increases the noise immunity and transforms a
slowly changing input signal to a fast changing, jitter free
output.
Connection Diagram
TL/F/6353 – 1
Order Number 54LS14DMQB, 54LS14FMQB,
54LS14LMQB, DM74LS14M or DM74LS14N
Function Table
YeA
Input Output
A Y
L H
H L
L e Low Logic Level

Input Voltage 7V
54LS b 55§ C to a 125§ C

54LS14 DM74LS14
VT a Positive-Going Input
1.5 1.6 2.0 1.4 1.6 1.9 V
Threshold Voltage (Note 1)
VTb Negative-Going Input
0.6 0.8 1.1 0.5 0.8 1 V
HYS Input Hysteresis (Note 1) 0.4 0.8 0.4 0.8 V
Typ
(Note 2)
VOH High Level Output VCC e Min, IOH e Max 54LS 2.5 3.4
V
Voltage VIL e Max
DM74 2.7 3.4
VOL Low Level Output VCC e Min, IOL e Max 54LS 0.25 0.4
Voltage VIH e Min
DM74 0.35 0.5 V
VCC e Min, IOL e 4 mA DM74 0.25 0.4
IT a Input Current at VCC e 5V, VI e VT a DM74
b 0.14 mA
Positive-Going Threshold
IT b Input Current at VCC e 5V, VI e VTb DM74
b 0.18 mA
Negative-Going Threshold
II Input Current @ Max VCC e Max, VI e 7V DM74
0.1 mA
Input Voltage
VCC e Max, VI e 10.0V 54LS
IOS Short Circuit VCC e Max 54LS b 20 b 100
mA

8.6 16 mA
Outputs High
12 21 mA
Outputs Low
Note 1: VCC e 5V.
2
RL e 2 kX
Min Max Min Max
5 22 8 25 ns
5 22 10 33 ns
3
Ceramic Leadless Chip Carrier (E)


Order Number 54LS14DMQB
4


5
54LS14/DM74LS14 Hex Inverters with Schmitt Trigger Inputs

Order Number 54LS14FMQB
LIFE SUPPORT POLICY
to the user.

Fran3ais Tel: (a49) 0-180-532 93 58 Tel: (852) 2737-1600
SN54LS06, SN54LS16, SN74LS06, SN74LS16
HEX INVERTER BUFFERS/DRIVERS WITH
OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS
SDLS020A – MAY 1990
• Converts TTL Voltage Levels to MOS SN54LS06, SN54LS16 . . . J PACKAGE

Levels SN74LS06, SN74LS16 . . . D OR N PACKAGE
• High Sink-Current Capability

(T0P VIEW)
• Input Clamping Diodes Simplify System 1A 1 14 VCC

Design 1Y 6A
2 13
• Open-Collector Driver for Indicator Lamps 2A 3 12 6Y
and Relays 2Y 4 11 5A
• Package Options Include “Small Outline” 3A 5 10 5Y
Packages, Ceramic Chip Carriers, and 3Y 6 9 4A
Standard Plastic and Ceramic 300-mil DIPs GND 7 8 4Y
description
SN54LS06, SN54LS16 . . . FK PACKAGE
These monolithic hex inverter buffers/drivers (T0P VIEW)
feature high-voltage open-collector outputs to
VCC
NC
1Y
1A
6A
interface with high-level circuits (such as MOS), or
for driving high-current loads, and are also
characterized for use as inverter buffers for driving 3 2 1 20 19
2A 4 18 6Y
TTL inputs. The ′LS06 has a rated output voltage NC NC
5 17
of 30 V and the ′LS16 has a rated output voltage
2Y 6 16 5A
of 15 V. The maximum sink current for the
NC 7 15 NC
SN54LS06 and SN54LS16 is 30 mA and the
3A 8 14 5Y
SN74LS06 and SN74LS16 is 40 mA. 9 10 11 12 13
These circuits are compatible with most TTL
3Y
4Y
4A
NC
GND
transmission-effects, which simplifies design.
The SN54LS06 and SN54LS16 are characterized over the full military temperature range of – 55°C to 125°C.
The SN74LS06 and SN74LS16 are characterized for operation from 0°C to 70°C.

1A 1 2 1Y
1 2
1A 1Y
2A 3 4 2Y
3A 5 6 3Y
3 4
2A 2Y
4A 9 8 4Y
5A 11 10 5Y
5 6
3A 3Y
6A 13 12 6Y
9 8
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC 4A 4Y
Publication 617-12.
Pin numbers shown are for D, J, and N packages. 10
11 5Y
5A
13 12
6A 6Y
UNLESS OTHERWISE NOTED this document contains PRODUCTION Copyright  1990, Texas Instruments Incorporated
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.


VCC
9 kΩ 2.5 kΩ
15 kΩ 1 kΩ
2.5 kΩ Output
Input
2 kΩ 2 kΩ
GND
Output voltage, VO (see Notes 1 and 2): SN54LS06, SN74LS06 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 V
SN54LS16, SN74LS16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V
Operating free-air temperature range: SN54LS06, SN54LS16 . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
SN74LS06, SN74LS16 . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. This are stress ratings only, and

SN54LS06 SN74LS06
SN54LS16 SN74LS16 UNIT
’LS06 30 30
VOH High-level output voltage ’LS16 15 15 V
PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.


otherwise noted)
SN54LS06 SN74LS06
PARAMETER TEST CONDITIONS† SN54LS16 SN74LS16 UNIT
VIK VCC = MIN, II = – 12 mA – 1.5 – 1.5 V
’LS06, VOH = 30 V 0.25 0.25
IOH VCC = MIN, VIL = 0.8 V mA
’LS16, VOH = 15 V 0.25 0.25
IOL = 16 mA 0.25 0.4 0.25 0.4
VOL VCC = MIN, VIH = 2 V IOL = 30 mA 0.7 V
IOL = 40 mA 0.7
IIL VCC =MAX, VI = 0.4 V – 0.2 – 0.2 mA
‡ All typical values are at VCC = 5 V, and TA = 25°C.
switching characteristics, VCC = 5 V, TA = 25°C (see Note 3)

FROM TO
(INPUT) (OUTPUT)
tPLH 7 15
A Y RL = 110 Ω, CL = 15 pF ns
tPHL 10 20
NOTE 3: Load circuit and voltage waveforms are shown in Section 1 of TTL Logic Data Book, 1988.
PRODUCT PREVIEW information concerns products in

the formative or design phase of development.
Characteristic data and other specifications are design
goals. Texas Instruments reserves the right to change or
discontinue these products without notice.

IMPORTANT NOTICE


HEX BUFFERS/DRIVERS WITH
SDLS021A, D3517, MAY 1990–REVISED AUGUST 1991
• Converts TTL-Voltage Levels to MOS SN54LS07 . . . J PACKAGE

SN74LS07, SN74LS17 . . . D OR N PACKAGE
Levels (T0P VIEW)
• High Sink-Current Capability
• Input Clamping Diodes Simplify System
1A
1Y
1
2
14
13
VCC
6A
Design 2A 3 12 6Y
• Open-Collector Driver for Indicator Lamps 2Y 4 11 5A
and Relays 3A 5 10 5Y
•
3Y 6 9 4A
Package Options Include “Small Outline”
GND 7 8 4Y
Packages, Ceramic Chip Carriers, and
Standard and Ceramic 300-mil DIPs
SN54LS07 . . . FK PACKAGE
description (T0P VIEW)
These monolithic hex buffers/drivers feature
VCC
NC
1Y
1A
6A
high-voltage open-collector outputs to interface
with high-level circuits or for driving high-current
3 2 1 20 19
loads. They are also characterized for use as 2A 4 18 6Y
buffers for driving TTL inputs. The ′LS07 has a NC 5 17 NC
rated output voltage of 30 V and the ′LS17 has a 2Y 6 16 5A
rated output voltage of 15 V. The maximum sink NC 7 15 NC
current is 30 mA for the SN54LS07 and 40 mA for 3A 8 14 5Y
the SN74LS07 and SN74LS17. 9 10 11 12 13
3Y
4Y
4A
These circuits are compatible with most TTL
NC
GND
transmission-line effects, which simplifies design. NC – No internal connection
The SN54LS07 is characterized over the full military temperature range of –55°C to 125°C. The SN74LS07 and
SN74LS17 are characterized for operation from 0°C to 70°C.

1 2
1A 1 2 1Y
1A 1Y
2A 3 4 2Y
3 4
3A 5 6 3Y
2A 2Y
4A 9 8 4Y
5 6
5A 11 10 5Y
3A 3Y
6A 13 12 6Y
9 8
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and 4A 4Y
IEC Publication 617-12.
Pin numbers shown are for D, J, and N packages. 11 10
5A 5Y
13 12
6A 6Y
PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.


VCC
9 kΩ 1 kΩ
5 kΩ
Input Output
2 kΩ
2 kΩ
GND
Output voltage, VO (see Notes 1 and 2): SN54LS07, SN74LS07 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 V
SN74LS17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V
Operating free-air temperature range: SN54LS07 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
SN54LS07, SN74LS17 . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C

SN74LS07
SN54LS07 SN74LS17 UNIT
’LS07 30 30
VOH High-level output voltage ’LS17 15 V


otherwise noted)
SN74LS07
SN54LS07
PARAMETER TEST CONDITIONS† SN74LS17 UNIT
VIK VCC = MIN, II = – 12 mA – 1.5 – 1.5 V
’LS07, VOH = 30 V 0.25 0.25
IOH VCC = MIN, VIH = 2 V mA
’LS17, VOH = 15 V 0.25 0.25
IOL = 16 mA 0.4 0.4
VOL VCC = MIN, VIL = 0.8 V V
IOL = MAX§ 0.7 0.7
IIL VCC = MAX, VI = 0.4 V – 0.2 – 0.2 mA
§ IOL = 30 mA for SN54 series parts and 40 mA for SN74 series parts.
switching characteristics, VCC = 5 V, TA = 25°C (see Note 3)

FROM TO
(INPUT) (OUTPUT)
tPLH 6 10
A Y RL = 110 Ω, CL = 15 pF ns
tPHL 19 30
NOTE 3: Load circuit and voltage waveforms are shown in Section 1 of TTL Logic Data Book, 1988.

IMPORTANT NOTICE


54LS20/DM54LS20/DM74LS20 Dual 4-Input NAND Gates
June 1989

This device contains two independent gates each of which Y Alternate Military/Aerospace device (54LS20) is avail-
Distributor for specifications
Connection Diagram
TL/F/6355 – 1
Function Table
Y e ABCD
Inputs Output
A B C D Y
X X X L H
X X L X H
X L X X H
L X X X H
H H H H L
L e Low Logic Level

Input Voltage 7V

DM54LS20 DM74LS20
Typ
(Note 1)
V
Voltage VIL e Max DM74 2.7 3.4
Voltage VIH e Min DM74 0.35 0.5 V
0.1 mA
Input Voltage
mA
0.4 0.8 mA
Outputs High
1.2 2.2 mA
Outputs Low
RL e 2 kX
Min Max Min Max
3 10 4 15 ns
3 10 4 15 ns
2
3


4


5

LIFE SUPPORT POLICY
to the user.

Fran3ais Tel: (a49) 0-180-532 93 58 Tel: (852) 2737-1600
54LS21/DM54LS21/DM74LS21 Dual 4-Input AND Gates
June 1989

This device contains two independent gates each of which Y Alternate Military/Aerospace device (54LS21) is avail-
Connection Diagram
TL/F/6356 – 1
Function Table
Y e ABCD
Inputs Output
A B C D Y
X X X L L
X X L X L
X L X X L
L X X X L
H H H H H
L e Low Logic Level

Input Voltage 7V

DM54LS21 DM74LS21
Typ
(Note 1)
V
0.1 mA
Input Voltage
mA
1.2 2.4 mA
Outputs High
2.2 4.4 mA
Outputs Low
RL e 2 kX
Min Max Min Max
4 13 6 18 ns
3 11 5 18 ns
2
3


4


5

LIFE SUPPORT POLICY
to the user.

Fran3ais Tel: (a49) 0-180-532 93 58 Tel: (852) 2737-1600
IMPORTANT NOTICE


IMPORTANT NOTICE


DM54LS27/DM74LS27 Triple 3-Input NOR Gates
May 1992
DM54LS27/DM74LS27
Triple 3-Input NOR Gates
General Description
This device contains three independent gates each of which
performs the logic NOR function.
Connection Diagram
TL/F/6359 – 1
Order Number DM54LS27J, DM54LS27W,

DM54LS27E, DM74LS27M or DM74LS27N
Function Table
YeAaBaC
Inputs Output
A B C Y
L L L H
X X H L
X H X L
H X X L
L e Low Logic Level

If Military/Aerospace specified devices are required, Storage Temperature Range b 65§ C to a 150§ C
please contact the National Semiconductor Sales Note: The ‘‘Absolute Maximum Ratings’’ are those values
Office/Distributors for availability and specifications. beyond which the safety of the device cannot be guaran-
Supply Voltage 7V teed. The device should not be operated at these limits. The
Input Voltage 7V parametric values defined in the ‘‘Electrical Characteristics’’
the conditions for actual device operation.

DM54LS27 DM74LS27
Typ
(Note 1)
VOH High Level Output VCC e Min, IOH e Max, DM54 2.5
V
Voltage VIL e Max DM74 2.7 3.4
VOL Low Level Output VCC e Min, IOL e Max, DM54 0.4
Voltage VIH e Min DM74 0.35 0.5 V
0.1 mA
Input Voltage
mA
2 4 mA
Outputs High
3.4 6.8 mA
Outputs Low
Switching Characteristics at VCC e 5V and TA e 25§ C

DM54 DM74
RL e 2 kX
CL e 15 pF CL e 15 pF CL e 50 pF
Min Max Min Max Min Max
3 13 3 13 5 18 ns
3 13 3 10 4 15 ns
2
3

Order Number DM54LS27E

Order Number DM54LS27J
4


5
DM54LS27/DM74LS27 Triple 3-Input NOR Gates

Order Number DM54LS27W
LIFE SUPPORT POLICY
to the user.

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IMPORTANT NOTICE


54LS30/DM54LS30/DM74LS30 8-Input NAND Gate
June 1989
8-Input NAND Gate
This device contains a single gate which performs the logic Y Alternate Military/Aerospace device (54LS30) is avail-
NAND function. able. Contact a National Semiconductor Sales Office/
Connection Diagram
TL/F/6360 – 1
54LS30LMQB, DM54LS30J, DM54LS530W, DM74LS30M or DM74LS30N
Function Table
Y e ABCDEFGH
Inputs Output
A thru H Y
All Inputs H L
One or More H
Input L
L e Low Logic Level

Input Voltage 7V

DM54LS30 DM74LS30
Typ
(Note 1)
V
Voltage VIL e Max
DM74 2.7 3.4
Voltage VIH e Min
DM74 0.35 0.5 V
0.1 mA
Input Voltage
mA
DM74 b 20 b 100

0.35 0.5 mA
Outputs High
0.6 1.1 mA
Outputs Low
RL e 2 kX
Min Max Min Max
4 12 5 18 ns
4 15 5 20 ns
2
3


4


5
54LS30/DM54LS30/DM74LS30 8-Input NAND Gate

LIFE SUPPORT POLICY
to the user.

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IMPORTANT NOTICE


54LS32/DM54LS32/DM74LS32 Quad 2-Input OR Gates
May 1989
Quad 2-Input OR Gates
performs the logic OR function. able. Contact a National Semiconductor Sales Office/
Connection Diagram
TL/F/6361 – 1
Function Table
YeAaB
Inputs Output
A B Y
L L L
L H H
H L H
H H H
L e Low Logic Level

Input Voltage 7V

DM54LS32 DM74LS32
Typ
(Note 1)
V
0.1 mA
Input Voltage
mA
3.1 6.2 mA
Outputs High
4.9 9.8 mA
Outputs Low
RL e 2 kX
Min Max Min Max
3 11 4 15 ns
3 11 4 15 ns
2
3


4


5
54LS32/DM54LS32/DM74LS32 Quad 2-Input OR Gates

LIFE SUPPORT POLICY
to the user.

Fran3ais Tel: (a49) 0-180-532 93 58 Tel: (852) 2737-1600
IMPORTANT NOTICE


IMPORTANT NOTICE


IMPORTANT NOTICE


IMPORTANT NOTICE


SN5446A, ’47A, ’48, SN54LS47, ’LS48, ’LS49
SN7446A, ’47A, ’48, SN74LS47, ’LS48, ’LS49
BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS
SDLS111 – MARCH 1974 – REVISED MARCH 1988
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

SN5446A, ’47A, ’48, SN54LS47, ’LS48, ’LS49
SN7446A, ’47A, ’48, SN74LS47, ’LS48, ’LS49

SN5446A, ’47A, ’48, SN54LS47, ’LS48, ’LS49
SN7446A, ’47A, ’48, SN74LS47, ’LS48, ’LS49

SN5446A, ’47A, ’48, SN54LS47, ’LS48, ’LS49
SN7446A, ’47A, ’48, SN74LS47, ’LS48, ’LS49

SN5446A, ’47A, ’48, SN54LS47, ’LS48, ’LS49
SN7446A, ’47A, ’48, SN74LS47, ’LS48, ’LS49

SN5446A, ’47A, ’48, SN54LS47, ’LS48, ’LS49
SN7446A, ’47A, ’48, SN74LS47, ’LS48, ’LS49

SN5446A, ’47A, ’48, SN54LS47, ’LS48, ’LS49
SN7446A, ’47A, ’48, SN74LS47, ’LS48, ’LS49

SN5446A, ’47A, ’48, SN54LS47, ’LS48, ’LS49
SN7446A, ’47A, ’48, SN74LS47, ’LS48, ’LS49

SN5446A, ’47A, ’48, SN54LS47, ’LS48, ’LS49
SN7446A, ’47A, ’48, SN74LS47, ’LS48, ’LS49

SN5446A, ’47A, ’48, SN54LS47, ’LS48, ’LS49
SN7446A, ’47A, ’48, SN74LS47, ’LS48, ’LS49

SN5446A, ’47A, ’48, SN54LS47, ’LS48, ’LS49
SN7446A, ’47A, ’48, SN74LS47, ’LS48, ’LS49

SN5446A, ’47A, ’48, SN54LS47, ’LS48, ’LS49
SN7446A, ’47A, ’48, SN74LS47, ’LS48, ’LS49

SN5446A, ’47A, ’48, SN54LS47, ’LS48, ’LS49
SN7446A, ’47A, ’48, SN74LS47, ’LS48, ’LS49

IMPORTANT NOTICE
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF

DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

SN54/74LS48
BCD TO 7-SEGMENT
DECODER
The SN54 / 74LS48 is a BCD to 7-Segment Decoder consisting of NAND
gates, input buffers and seven AND-OR-INVERT gates. Seven NAND gates
and one driver are connected in pairs to make BCD data and its complement BCD TO 7-SEGMENT
available to the seven decoding AND-OR-INVERT gates. The remaining DECODER
NAND gate and three input buffers provide lamp test, blanking input/ripple-
blanking input for the LS48. LOW POWER SCHOTTKY
The circuit accepts 4-bit binary-coded-decimal (BCD) and, depending on
the state of the auxiliary inputs, decodes this data to drive other components.
The relative positive logic output levels, as well as conditions required at the
auxiliary inputs, are shown in the truth tables.
The LS48 circuit incorporates automatic leading and / or trailing edge
J SUFFIX
zero-blanking control (RBI and RBO). Lamp Test (LT) may be activated any
CERAMIC
time when the BI / RBO node is HIGH. Both devices contain an overriding CASE 620-09
blanking input (BI) which can be used to control the lamp intensity by varying 16
the frequency and duty cycle of the BI input signal or to inhibit the outputs. 1
• Lamp Intensity Modulation Capability (BI/RBO)
• Internal Pull-Ups Eliminate Need for External Resistors
• Input Clamp Diodes Eliminate High-Speed Termination Effects
N SUFFIX
PLASTIC
CASE 648-08
CONNECTION DIAGRAM DIP (TOP VIEW) 16
VCC f g a b c d e 1
16 15 14 13 12 11 10 9
D SUFFIX
SOIC
16
1 CASE 751B-03
1 2 3 4 5 6 7 8 ORDERING INFORMATION
B C LT BI / RBO RBI D A GND SN54LSXXJ Ceramic
SN74LSXXN Plastic
LOGIC DIAGRAM SN74LSXXD SOIC
A LOGIC SYMBOL
b 7 1 2 6 3 5
B
INPUT
A B C D LT RBI
C c
D SN54 / 74LS48
OUTPUT BI/
d a b c d e f g RBO
BLANKING INPUT OR
RIPPLE-BLANKING
OUTPUT e 13 12 11 10 9 15 14 4
VCC = PIN 16
GND = PIN 8
f
RIPPLE-BLANKING
INPUT
LAMP-TEST
INPUT g
FAST AND LS TTL DATA

5-1
SN54/74LS48
PIN NAMES LOADING (Note a)

HIGH LOW
A, B, C, D BCD Inputs 0.5 U.L. 0.25 U.L.
RBI Ripple-Blanking (Active Low) Input 0.5 U.L. 0.25 U.L.
LT Lamp-Test (Active Low) Input 0.5 U.L. 0.25 U.L.
BI / RBO Blanking Input or Ripple- 0.5 U.L. 0.75 U.L.
Blanking Output (Active Low) 1.2 U.L. 2(1) U.L.
BI Blanking (Active Low) Input 0.5 U.L. 0.25 U.L.
Open-Collector 3.75 (1.25) U.L. (48)
NOTES:
a) Unit Load (U.L.) = 40 µA HIGH / 1.6 mA LOW
b) Outut current measured at VOUT = 0.5 V
Output LOW drive factor is SN54LS / 74LS48: 1.25 U.L. for Military (54), 3.75 U.L. for Commercial (74).
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
NUMERICAL DESIGNATIONS — RESULTANT DISPLAYS
TRUTH TABLE
SN54 / 74LS48
INPUTS OUTPUTS
DECIMAL
OR LT RBI D C B A BI / RBO a b c d e f g NOTE
FUNCTION
0 H H L L L L H H H H H H H L 1
1 H X L L L H H L H H L L L L 1
2 H X L L H L H H H L H H L H NOTES:
3 H X L L H H H H H H H L L H (1) BI/RBO is wired-AND logic serving as blanking input (BI) and/or
4 H X L H L L H L H H L L H H ripple-blanking output (RBO). The blanking out (BI) must be open
or held at a HIGH level when output functions 0 through 15 are
5 H X L H L H H H L H H L H H
desired, and ripple-blanking input (RBI) must be open or at a HIGH
6 H X L H H L H L L H H H H H
level if blanking of a decimal 0 is not desired. X=input may be HIGH
7 H X L H H H H H H H L L L L or LOW.
8 H X H L L L H H H H H H H H (2) When a LOW level is applied to the blanking input (forced condition)
9 H X H L L H H H H H L L H H all segment outputs go to a LOW level, regardless of the state of any
other input condition.
10 H X H L H L H L L L H H L H
(3) When ripple-blanking input (RBI) and inputs A, B, C, and D are at
11 H X H L H H H L L H H L L H LOW level, with the lamp test input at HIGH level, all segment
12 H X H H L L H L H L L L H H outputs go to a HIGH level and the ripple-blanking output (RBO)
13 H X H H L H H H L L H L H H goes to a LOW level (response condition).
(4) When the blanking input/ripple-blanking output (BI/RBO) is open or
14 H X H H H L H L L L H H H H
held at a HIGH level, and a LOW level is applied to lamp-test input,
15 H X H H H H H L L L L L L L all segment outputs go to a LOW level.
BI X X X X X X L L L L L L L L 2
RBI H L L L L L L L L L L L L L 3
LT L X X X X X H H H H H H H H 4

5-2
SN54/74LS48
GUARANTEED OPERATING RANGES

Symbol Parameter Min Typ Max Unit
VCC Supply Voltage 54 4.5 5.0 5.5 V
74 4.75 5.0 5.25
TA Operating Ambient Temperature Range 54 – 55 25 125 °C
74 0 25 70
IOH Output Current — High a to g 54, 74 – 100 µA
IOH Output Current — High BI / RBO 54, 74 – 50 µA
IOL Output Current — Low a to g 54 2.0 mA
74 6.0
IOL Output Current — Low BI / RBO 54 1.6 mA
BI / RBO 74 3.2
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

Limits
S b l
Symbol P
Parameter Min Typ Max U i
Unit T
Test C
Conditions
di i
Guaranteed Input HIGH Voltage for
VIH Input HIGH Voltage 2.0 V
All Inputs
54 0.7 Guaranteed Input
p LOW Voltage
g for
VIL Input LOW Voltage V
74 0.8 All Inputs
VIK Input Clamp Diode Voltage – 1.5 V VCC = MIN, IIN = – 18 mA

VCC = MIN,, IOH = – 50 µA,
µ ,
VOH Output HIGH Voltage 24
2.4 42
4.2 µA
VIN = VIH or U.L. per Truth Table
VCC = MIN, VO = 0.85 V

IO Output Current a to g – 1.3 – 2.0 mA
Input Conditioner as for VOH
54, 74 0.4 V IOL = 2.0 mA VCC = MIN,, VIH = 2.0 V
VOL Output LOW Voltage a to g
74 0.5 V IOL = 6.0 mA VIL = VIL MAX
Output
p LOW Voltage
g 54, 74 0.4 V IOL = 1.6 mA VCC = MAX,, VIH = 2.0 V
VOL
BI / RBO 74 0.5 V IOL = 3.2 mA VIL = VIL MAX
Input
p HIGH Current 20 µA VCC = MAX, VIN = 2.7 V
IIH
(Except BI / RBO) 0.1 mA VCC = MAX, VIN = 7.0 V
Input LOW Current
IIL – 0.4 mA VCC = MAX, VIN = 0.4 V
(Except BI / RBO)
IIL Input LOW Current BI / RBO – 1.2 mA VCC = MAX, VIN = 0.4 V
ICC Power Supply Current 25 38 mA VCC = MAX
IOS Short Circuit Current BI / RBO (Note 1) – 0.3 –2.0 mA VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (VCC = 5.0 V, TA = 25°C)

Limits
S b l
Symbol P
Unit T
Test C
Conditions
di i
Propagation Delay Time, HIGH-to-LOW
tPHL 100 ns
Level Output from A Input
CL = 15 pF,
pF RL = 4.0
4 0 kΩ
Propagation Delay Time, LOW-to-HIGH
tPLH 100 ns
Level Output from A Input
Propagation Delay Time, HIGH-to-LOW
tPHL 100 ns
Level Output from RBI Input
CL = 15 pF,
pF RL = 6.0
6 0 kΩ
Propagation Delay Time, LOW-to-HIGH
tPLH 100 ns
Level Output from RBI Input

5-3
IMPORTANT NOTICE


IMPORTANT NOTICE


IMPORTANT NOTICE


IMPORTANT NOTICE


IMPORTANT NOTICE


IMPORTANT NOTICE


IMPORTANT NOTICE


IMPORTANT NOTICE


Master-Slave J-K Flip-Flops with Clear and Complementary Outputs
DM54LS73A/DM74LS73A Dual Negative-Edge-Triggered
June 1989

Master-Slave J-K Flip-Flops with Clear
and Complementary Outputs
General Description
This device contains two independent negative-edge-trig- and K inputs is allowed to change while the clock is high or
gered J-K flip-flops with complementary outputs. The J and low without affecting the outputs as long as setup and hold
K data is processed by the flip-flops on the falling edge of times are not violated. A low logic level on the clear input
the clock pulse. The clock triggering occurs at a voltage will reset the outputs regardless of the levels of the other
level and is not directly related to the transition time of the inputs.
negative going edge of the clock pulse. The data on the J
Connection Diagram
TL/F/6372 – 1
Order Number DM54LS73AJ, DM54LS73AW, DM74LS73AM or DM74LS73AN
See NS Package Number J14A, M14A, N14A or W14B
Function Table
Inputs Outputs
CLR CLK J K Q Q
L X X X L H
H v L L Q0 Q0
H v H L H L
H v L H L H
H v H H Toggle
H H X X Q0 Q0
L e Low Logic Level
v e Negative going edge of pulse.
Q0 e The output logic level before the indicated input conditions were es-
tablished.
Toggle e Each output changes to the complement of its previous level on
each falling edge of the clock pulse.

Input Voltage 7V
DM54LS b 55§ C to a 125§ C

DM54LS73A DM74LS73A
fCLK Clock Frequency (Note 2) 0 30 0 30 MHz
tW Pulse Width Clock High 20 20
(Note 2)
Preset Low 25 25 ns
Clear Low 25 25
(Note 3)
Preset Low 30 30 ns
Clear Low 30 30
tSU Setup Time (Notes 1 and 2) 20v 20v ns
tSU Setup Time (Notes 1 and 3) 25v 25v ns
tH Hold Time (Notes 1 and 2) 0v 0v ns
tH Hold Time (Notes 1 and 3) 5v 5v ns
Note 1: The symbol ( v) indicates the falling edge of the clock pulse is used for reference.
Note 2: CL e 15 pF, RL e 2 kX, TA e 25§ C and VCC e 5V.
2
Typ
(Note 1)
V
Voltage VIL e Max, VIH e Min DM74 2.7 3.4
Voltage VIL e Max, VIH e Min DM74 0.35 0.5 V
II Input Current @ Max VCC e Max J, K 0.1
Input Voltage VI e 7V Clear 0.3 mA
Clock 0.4
IIH High Level Input VCC e Max J, K 20
Current VI e 2.7V Clear 60 mA
Clock 80
IIL Low Level Input VCC e Max J, K b 0.4
Current VI e 0.4V
Clear b 0.8 mA
Clock b 0.8

mA
DM74 b 20 b 100
ICC Supply Current VCC e Max (Note 3) 4 6 mA
RL e 2 kX
From (Input)
Symbol Parameter To (Output) CL e 15 pF CL e 50 pF Units
Min Max Min Max
fMAX Maximum Clock
30 25 MHz
Frequency
tPHL Propagation Delay Time Clear
20 28 ns
High to Low Level Output to Q
tPLH Propagation Delay Time Clear
20 24 ns
Low to High Level Output to Q
tPLH Propagation Delay Time Clock to
20 24 ns
Low to High Level Output Q or Q
tPHL Propagation Delay Time Clock to
20 28 ns
High to Low Level Output Q or Q
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second. For devices, with feedback from the outputs, where
shorting the outputs to ground may cause the outputs to change logic state, an equivalent test may be performed where VO e 2.25V and 2.125V for DM54 and
DM74 series, respectively, with the minimum and maximum limits reduced by one half from their stated values. This is very useful when using automatic test
equipment.
Note 3: With all outputs open, ICC is measured with the Q and Q outputs high in turn. At the time of measurement, the clock is grounded.
3

Order Number DM54LS73AJ
4

Order Number DM74LS73AM

Order Number DM74LS73AN
5
Master-Slave J-K Flip-Flops with Clear and Complementary Outputs

Order Number DM54LS73AW
LIFE SUPPORT POLICY
to the user.

Fran3ais Tel: (a49) 0-180-532 93 58 Tel: (852) 2737-1600
D Flip-Flops with Preset, Clear and Complementary Outputs
54LS74/DM54LS74A/DM74LS74A Dual Positive-Edge-Triggered
June 1989
54LS74/DM54LS74A/DM74LS74A
Dual Positive-Edge-Triggered D Flip-Flops
with Preset, Clear and Complementary Outputs
General Description
This device contains two independent positive-edge-trig- violated. A low logic level on the preset or clear inputs will
gered D flip-flops with complementary outputs. The informa- set or reset the outputs regardless of the logic levels of the
tion on the D input is accepted by the flip-flops on the posi- other inputs.
tive going edge of the clock pulse. The triggering occurs at a
voltage level and is not directly related to the transition time Features
of the rising edge of the clock. The data on the D input may Y Alternate military/aerospace device (54LS74) is avail-
be changed while the clock is low or high without affecting able. Contact a National Semiconductor Sales Office/
the outputs as long as the data setup and hold times are not Distributor for specifications.
Connection Diagram
TL/F/6373 – 1
DM54LS74AJ, DM54LS74AW, DM74LS74AM or DM74LS74AN
Function Table
Inputs Outputs
PR CLR CLK D Q Q
L H X X H L
H L X X L H
L L X X H* H*
H H u H H L
H H u L L H
H H L X Q0 Q0
L e Low Logic Level
u e Positive-going Transition
* e This configuration is nonstable; that is, it will not persist when either the preset
and/or clear inputs return to their inactive (high) level.
Q0 e The output logic level of Q before the indicated input conditions were established.

Input Voltage 7V

DM54LS74A DM74LS74A
(Note 2)
Preset Low 15 15 ns
Clear Low 15 15
(Note 3)
Preset Low 20 20 ns
Clear Low 20 20
tSU Setup Time (Notes 1 and 2) 20u 20u ns
tSU Setup Time (Notes 1 and 3) 25u 25u ns
tH Hold Time (Note 1 and 4) 0u 0u ns
Note 1: The symbol ( u) indicates the rising edge of the clock pulse is used for reference.
Note 2: CL e 15 pF, RL e 2 kX, TA e 25§ C, and VCC e 5V.
Note 3: CL e 50 pF, RL e 2 kX, TA e 25§ C, and VCC e 5V.
Note 4: TA e 25§ C and VCC e 5V.
2
Typ
(Note 1)
V
II Input Current @ Max VCC e Max Data 0.1
Input Voltage VI e 7V Clock 0.1
mA
Preset 0.2
Clear 0.2
IIH High Level Input VCC e Max Data 20
Current VI e 2.7V Clock 20
mA
Clear 40
Preset 40
IIL Low Level Input VCC e Max Data b 0.4
Current VI e 0.4V
Clock b 0.4
mA
Preset b 0.8
Clear b 0.8

mA
DM74 b 20 b 100

Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second. For devices, with feedback from the outputs, where
shorting the outputs to ground may cause the outputs to change logic state an equivalent test may be performed where VO e 2.25V and 2.125V for DM54 and
DM74 series, respectively, with the minimum and maximum limits reduced by one half from their stated values. This is very useful when using automatic test
equipment.
Note 3: With all outputs open, ICC is measured with CLOCK grounded after setting the Q and Q outputs high in turn.
RL e 2 kX
From (Input)
Min Max Min Max
fMAX Maximum Clock Frequency 25 20 MHz
25 35 ns
30 35 ns
tPLH Propagation Delay Time Preset
25 35 ns
tPHL Propagation Delay Time Preset
30 35 ns
tPLH Propagation Delay Time Clear
25 35 ns
30 35 ns
3


Order Number 54LS74DMQB or DM54LS74AJ
4


5
54LS74/DM54LS74A/DM74LS74A Dual Positive-Edge-Triggered
D Flip-Flops with Preset, Clear and Complementary Outputs

Order Number 54LS74FMQB or DM54LS74AW
LIFE SUPPORT POLICY
to the user.

Fran3ais Tel: (a49) 0-180-532 93 58 Tel: (852) 2737-1600
IMPORTANT NOTICE


IMPORTANT NOTICE


IMPORTANT NOTICE


54LS83A/DM54LS83A/DM74LS83A 4-Bit Binary Adders with Fast Carry
May 1989
54LS83A/DM54LS83A/DM74LS83A
4-Bit Binary Adders with Fast Carry
These full adders perform the addition of two 4-bit binary Y Full-carry look-ahead across the four bits
numbers. The sum (R) outputs are provided for each bit and Y Systems achieve partial look-ahead performance with
the resultant carry (C4) is obtained from the fourth bit. the economy of ripple carry
These adders feature full internal look ahead across all four Y Typical add times
bits. This provides the system designer with partial look- Two 8-bit words 25 ns
ahead performance at the economy and reduced package Two 16-bit words 45 ns
count of a ripple-carry implementation. Y Typical power dissipation per 4-bit adder 95 mW
The adder logic, including the carry, is implemented in its Y Alternate Military/Aerospace device (54LS83A) is avail-
true form meaning that the end-around carry can be accom- able. Contact a National Semiconductor Sales Office/
plished without the need for logic or level inversion. Distributor for specifications.
Connection Diagram
TL/F/6378 – 1
Order Number 54LS83ADMQB, 54LS83AFMQB,
DM54LS83AJ, DM54LS83AW, DM74LS83AWM or DM74LS83AN
See NS Package Number J16A, M16B, N16E or W16A

Input Voltage 7V

DM54LS83A DM74LS83A
Typ
(Note 1)
V
Voltage VIL e Max, VIH e Min
DM74 2.7 3.4
DM74 0.35 0.5 V
II Input Current @ Max VCC e Max A or B 0.2
mA
Input Voltage VI e 7V
C0 0.1
IIH High Level Input VCC e Max A or B 40
mA
Current VI e 2.7V
C0 20
IIL Low Level Input VCC e Max A or B b 0.8
mA
Current VI e 0.4V
C0 b 0.4

Output Current (Note 2) mA
DM74 b 20 b 100
ICC1 Supply Current VCC e Max (Note 3) 19 34 mA

Note 3: ICC1 is measured with all outputs open, all B inputs low and all other inputs at 4.5V, or all inputs at 4.5V.
Note 4: ICC2 is measured with all outputs open and all inputs grounded.
2
RL e 2 kX
From (Input)
To (Output)
Min Max Min Max
tPLH Propagation Delay Time C0 to
24 28 ns
Low to High Level Output R1 or R2
tPHL Propagation Delay Time C0 to
24 30 ns
High to Low Level Output R1 or R2
24 28 ns
Low to High Level Output R3
24 30 ns
High to Low Level Output R3
24 28 ns
24 30 ns
tPLH Propagation Delay Time Ai, Bi
24 28 ns
Low to High Level Output to Ri
tPHL Propagation Delay Time Ai, Bi
24 30 ns
High to Low Level Output to Ri
17 24 ns
Low to High Level Output C4
17 25 ns
High to Low Level Output C4
tPLH Propagation Delay Time Ai, Bi
17 24 ns
Low to High Level Output to C4
tPHL Propagation Delay Time Ai, Bi
17 26 ns
High to Low Level Output to C4
Truth Table
H e High Level, L e Low Level TL/F/6378 – 3

Note: Input conditions at A1, B1, A2, B2, and C0 are used to determine outputs R1 and R2 and the value of the internal carry C2. The values at C2, A3, B3, A4, and
B4 are then used to determine outputs R3, R4, and C4.
3
Logic Diagram
TL/F/6378 – 2
4
5

Order Number 54LS83ADMQB or DM54LS83AJ
6
16-Lead Wide Small Outline Molded Package (M)

Order Number DM74LS83AWM
NS Package Number M16B

NS Package Number N16E
7
54LS83A/DM54LS83A/DM74LS83A 4-Bit Binary Adders with Fast Carry

Order Number 54LS83AFMQB or DM54LS83AW
NS Package Number W16A
LIFE SUPPORT POLICY
to the user.

Fran3ais Tel: (a49) 0-180-532 93 58 Tel: (852) 2737-1600
54LS85/DM54LS85/DM74LS85 4-Bit Magnitude Comparators
June 1989
4-Bit Magnitude Comparators
General Description
These 4-bit magnitude comparators perform comparison of have a high-level voltage applied to the A e B input. The
straight binary or BCD codes. Three fully-decoded decisions cascading path is implemented with only a two-gate-level
about two, 4-bit words (A, B) are made and are externally delay to reduce overall comparison times for long words.
available at three outputs. These devices are fully expand-
able to any number of bits without external gates. Words of Features
greater length may be compared by connecting compara- Y Typical power dissipation 52 mW
tors in cascade. The A l B, A k B, and A e B outputs of a Y Typical delay (4-bit words) 24 ns
stage handling less-significant bits are connected to the cor- Y Alternate Military/Aerospace device (54LS85) is avail-
responding inputs of the next stage handling more-signifi-
cant bits. The stage handling the least-significant bits must
Connection Diagram
Order Number 54LS85DMQB,

54LS85FMQB, 54LS85LMQB,
DM54LS85J, DM54LS85W,
DM74LS85M or DM74LS85N
See NS Package Number E20A,
J16A, M16A, N16E or W16A
TL/F/6379 – 1
Function Table
Comparing Cascading
Outputs
Inputs Inputs
A3, B3 A2, B2 A1, B1 A0, B0 AlB AkB AeB AlB AkB AeB
A3 l B3 X X X X X X H L L
A3 k B3 X X X X X X L H L
A3 e B3 A2 l B2 X X X X X H L L
A3 e B3 A2 k B2 X X X X X L H L
A3 e B3 A2 e B2 A1 l B1 X X X X H L L
A3 e B3 A2 e B2 A1 k B1 X X X X L H L
A3 e B3 A2 e B2 A1 e B1 A0 l B0 X X X H L L
A3 e B3 A2 e B2 A1 e B1 A0 k B0 X X X L H L
A3 e B3 A2 e B2 A1 e B1 A0 e B0 H L L H L L
A3 e B3 A2 e B2 A1 e B1 A0 e B0 L H L L H L
A3 e B3 A2 e B2 A1 e B1 A0 e B0 L L H L L H
A3 e B3 A2 e B2 A1 e B1 A0 e B0 X X H L L H
A3 e B3 A2 e B2 A1 e B1 A0 e B0 H H L L L L
A3 e B3 A2 e B2 A1 e B1 A0 e B0 L L L H H L
H e High Level, L e Low Level, X e Don’t Care

Input Voltage 7V

DM54LS85 DM74LS85
Typ
(Note 1)
V
DM74 2.7 3.4
II Input Current @ Max VCC e Max AkB 0.1
AlB 0.1 mA
Others 0.3
IIH High Level Input VCC e Max AkB 20
Current VI e 2.7V
AlB 20 mA
Others 60
IIL Low Level Input VCC e Max AkB b 0.4
Current VI e 0.4V AlB b 0.4 mA
Others b 1.2

mA

Note 3: ICC is measured with all outputs open, A e B grounded and all other inputs at 4.5V.
2
RL e 2 kX
From To Number of
Symbol Parameter Input Output Gate Levels CL e 15 pF CL e 50 pF Units
Min Max Min Max
tPLH Propagation Delay Time Any A or B A k B,
3 36 42
Low-to-High Level Output Data Input AlB ns
AeB 4 40 40
tPHL Propagation Delay Time Any A or B A k B,
3 30 40
High-to-Low Level Output Data Input AlB ns
AeB 4 30 40
tPLH Propagation Delay Time AkB
AlB 1 22 26 ns
Low-to-High Level Output or A e B
tPHL Propagation Delay Time AkB
AlB 1 17 26 ns
High-to-Low Level Output or A e B
A eB AeB 2 20 25 ns
Low-to-High Level Output
AeB AeB 2 17 26 ns
High-to-Low Level Output
tPLH Propagation Delay Time AlB
AkB 1 22 26 ns
Low-to-High Level Output or A e B
tPHL Propagation Delay Time AlB
AkB 1 17 26 ns
High-to-Low Level Output or A e B
3
Logic Diagram
TL/F/6379 – 2
4
5
Chip Carrier Package (E)


6


7
54LS85/DM54LS85/DM74LS85 4-Bit Magnitude Comparators

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DM54LS86/DM74LS86 Quad 2-Input Exclusive-OR Gates
June 1989
DM54LS86/DM74LS86
Quad 2-Input Exclusive-OR Gates
General Description
This device contains four independent gates each of which
performs the logic exclusive-OR function.
Connection Diagram
TL/F/6380 – 1
Order Number DM54LS86J, DM54LS86W, DM74LS86M or DM74LS86N
Function Table
YeA Z B e AB a AB
Inputs Output
A B Y
L L L
L H H
H L H
H H L
L e Low Logic Level

Input Voltage 7V
DM54LS b 55§ C to a 125§ C

DM54LS86 DM74LS86
Typ
(Note 1)
V
0.2 mA
Input Voltage
mA
6.1 10 mA
Outputs High (Note 3)
9 15 mA
Outputs Low (Note 4)
Note 3: ICCH is measured with all outputs open, one input at each gate at 4.5V, and the other inputs grounded.
Note 4: ICCL is measured with all outputs open and all inputs grounded.
2
RL e 2 kX
Symbol Parameter Conditions CL e 15 pF CL e 50 pF Units
Min Max Min Max
Other 18 23 ns
Input
tPHL Propagation Delay Time Low
17 21 ns
Other 10 15 ns
Input
tPHL Propagation Delay Time High
12 15 ns
3

4


5
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DM74LS90/DM74LS93 Decade and Binary Counters
June 1989
DM74LS90/DM74LS93
Decade and Binary Counters
General Description
Each of these monolithic counters contains four master- count pulses are applied to input A and the outputs are as
slave flip-flops and additional gating to provide a divide-by- described in the appropriate truth table. A symmetrical di-
two counter and a three-stage binary counter for which the vide-by-ten count can be obtained from the ’LS90 counters
count cycle length is divide-by-five for the ’LS90 and divide- by connecting the QD output to the A input and applying the
by-eight for the ’LS93. input count to the B input which gives a divide-by-ten square
All of these counters have a gated zero reset and the LS90 wave at output QA.
also has gated set-to-nine inputs for use in BCD nine’s com-
plement applications. Features
To use their maximum count length (decade or four bit bina- Y Typical power dissipation 45 mW
ry), the B input is connected to the QA output. The input Y Count frequency 42 MHz
Connection Diagrams (Dual-In-Line Packages)
TL/F/6381 – 1
TL/F/6381 – 2
Order Number DM74LS90M or DM74LS90N
See NS Package Number M14A or N14A

Input Voltage (Reset) 7V
Input Voltage (A or B) 5.5V the conditions for actual device operation.

DM74LS90
Min Nom Max
VCC Supply Voltage 4.75 5 5.25 V
VIH High Level Input Voltage 2 V
VIL Low Level Input Voltage 0.8 V
IOH High Level Output Current b 0.4 mA
IOL Low Level Output Current 8 mA
fCLK Clock Frequency (Note 1) A to QA 0 32
MHz
B to QB 0 16
MHz
B to QB 0 10
tW Pulse Width (Note 1) A 15
B 30 ns
Reset 15
B 50 ns
Reset 25
tREL Reset Release Time (Note 1) 25 ns
TA Free Air Operating Temperature 0 70 §C
’LS90 Electrical Characteristics

over recommended operating free air temperature range (unless otherwise noted)
Typ
(Note 1)
VOH High Level Output VCC e Min, IOH e Max
2.7 3.4 V
VOL Low Level Output VCC e Min, IOL e Max
Voltage VIL e Max, VIH e Min 0.35 0.5
V
(Note 4)
IOL e 4 mA, VCC e Min 0.25 0.4
II Input Current @ Max VCC e Max, VI e 7V Reset 0.1
Input Voltage
VCC e Max A 0.2 mA
VI e 5.5V B 0.4
2
over recommended operating free air temperature range (unless otherwise noted) (Continued)
Typ
(Note 1)
IIH High Level Input VCC e Max, VI e 2.7V Reset 20
Current A 40 mA
B 80
IIL Low Level Input VCC e Max, VI e 0.4V Reset b 0.4
Current A b 2.4 mA
B b 3.2
IOS Short Circuit VCC e Max (Note 2)

b 20 b 100 mA
Output Current
Note 3: ICC is measured with all outputs open, both RO inputs grounded following momentary connection to 4.5V and all other inputs grounded.
Note 4: QA outputs are tested at IOL e Max plus the limit value of IIL for the B input. This permits driving the B input while maintaining full fan-out capability.
’LS90 Switching Characteristics

at VCC e 5V and TA e 25§ C (See Section 1 for Test Waveforms and Output Load)
RL e 2 kX
From (Input)
Min Max Min Max
fMAX Maximum Clock A to QA 32 20
MHz
Frequency B to QB 16 10
A to QA 16 20 ns
A to QA 18 24 ns
A to QD 48 52 ns
A to QD 50 60 ns
B to QB 16 23 ns
B to QB 21 30 ns
B to QC 32 37 ns
B to QC 35 44 ns
B to QD 32 36 ns
B to QD 35 44 ns
tPLH Propagation Delay Time SET-9 to
30 35 ns
Low to High Level Output QA, QD
tPHL Propagation Delay Time SET-9 to
40 48 ns
High to Low Level Output QB, QC
40 52 ns
High to Low Level Output Any Q
3
DM74LS93
Min Nom Max
B to QB 0 16
MHz
B to QB 0 10
B 30 ns
Reset 15
B 50 ns
Reset 25

Typ
(Note 1)
2.7 3.4 V
Voltage VIL e Max, VIH e Min 0.35 0.5 V
(Note 4)
II Input Current @ Max VCC e Max, VI e 7V Reset 0.1
Input Voltage VCC e Max A 0.2 mA
VI e 5.5V B 0.4
IIH High Level Input VCC e Max Reset 20
Current VI e 2.7V
A 40 mA
B 80
4
Typ
(Note 1)
IIL Low Level Input VCC e Max, VI e 0.4V Reset b 0.4
Current A b 2.4 mA
B b 1.6
IOS Short Circuit VCC e Max (Note 2)

b 20 b 100 mA
Output Current
Note 3: ICC is measured with all outputs open, both RO inputs grounded following momentary connection to 4.5V and all other inputs grounded.
Note 4: QA outputs are tested at IOL e max plus the limit value of IIL for the B input. This permits driving the B input while maintaining full fan-out capability.

RL e 2 kX
From (Input)
Min Max Min Max
fMAX Maximum Clock A to QA 32 20
MHz
Frequency
B to QB 16 10
A to QA 16 20 ns
A to QA 18 24 ns
A to QD 70 85 ns
A to QD 70 90 ns
B to QB 16 23 ns
B to QB 21 30 ns
B to QC 32 37 ns
B to QC 35 44 ns
B to QD 51 60 ns
B to QD 51 70 ns
40 52 ns
5
Function Tables
LS90 LS90
BCD Count Sequence Bi-Quinary (5-2)
(See Note A) (See Note B)
Output Output
Count Count
QD QC QB QA QA QD QC QB
0 L L L L 0 L L L L
1 L L L H 1 L L L H
2 L L H L 2 L L H L
3 L L H H 3 L L H H
4 L H L L 4 L H L L
5 L H L H 5 H L L L
6 L H H L 6 H L L H
7 L H H H 7 H L H L
8 H L L L 8 H L H H
9 H L L H 9 H H L L
LS93 LS90
Count Sequence Reset/Count Truth Table
(See Note C)
Reset Inputs Output
Output
Count R0(1) R0(2) R9(1) R9(2) QD QC QB QA
QD QC QB QA
H H L X L L L L
0 L L L L H H X L L L L L
1 L L L H X X H H H L L H
2 L L H L X L X L COUNT
3 L L H H L X L X COUNT
4 L H L L L X X L COUNT
5 L H L H X L L X COUNT
6 L H H L
7 L H H H
8 H L L L LS93
9 H L L H Reset/Count Truth Table
10 H L H L
Reset Inputs Output
11 H L H H
12 H H L L R0(1) R0(2) QD QC QB QA
13 H H L H H H L L L L
14 H H H L L X COUNT
15 H H H H X L COUNT
Note A: Output QA is connected to input B for BCD count.
Note B: Output QD is connected to input A for bi-quinary count.
Note C: Output QA is connected to input B.
Note D: H e High Level, L e Low Level, X e Don’t Care.
6
Logic Diagrams
LS90 LS93
TL/F/6381 – 4
TL/F/6381 – 3
The J and K inputs shown without connection are for reference only and are functionally at a high level.
7
8

Order Number DM74LS90M or DM74LS93M
9
DM74LS90/DM74LS93 Decade and Binary Counters

Order Number DM74LS90N or DM74LS93N
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IMPORTANT NOTICE


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IMPORTANT NOTICE


with Clear and Complementary Outputs
DM74LS123 Dual Retriggerable One-Shot
March 1991

Y Compensated for VCC and temperature variations
General Description Y Triggerable from CLEAR input
The DM74LS123 is a dual retriggerable monostable multivi- Y DTL, TTL compatible
brator capable of generating output pulses from a few nano-
seconds to extremely long duration up to 100% duty cycle.
Y Input clamp diodes
Each device has three inputs permitting the choice of either
leading edge or trailing edge triggering. Pin (A) is an active- Functional Description
low transition trigger input and pin (B) is an active-high tran- The basic output pulse width is determined by selection of
sition trigger input. The clear (CLR) input terminates the out- an external resistor (RX) and capacitor (CX). Once triggered,
put pulse at a predetermined time independent of the timing the basic pulse width may be extended by retriggering the
components. The clear input also serves as a trigger input gated active-low transition or active-high transition inputs or
when it is pulsed with a low level pulse transition (ß). To be reduced by use of the active-low or CLEAR input. Retrig-
obtain the best trouble free operation from this device gering to 100% duty cycle is possible by application of an
please read the operating rules as well as the NSC one-shot input pulse train whose cycle time is shorter than the output
application notes carefully and observe recommendations. cycle time such that a continuous ‘‘HIGH’’ logic state is
maintained at the ‘‘Q’’ output.
Features
Y DC triggered from active-high transition or active-low
transition inputs
Y Retriggerable to 100% duty cycle
Connection Diagram Function Table
Dual-In-Line Package Inputs Outputs

CLEAR A B Q Q
L X X L H
X H X L H
X X L L H
H L u É ß
H v H É ß
u L H É ß
L e Low Logic Level
X e Can Be Either Low or High
u e Positive Going Transition
v e Negative Going Transition
É e A Positive Pulse
ß e A Negative Pulse
TL/F/6386 – 1
See NS Package Number M16A or N16E

Input Voltage 7V
Operating Free Air Temperature Range 0§ C to a 70§ C the conditions for actual device operation.
Storage Temperature b 65§ C to a 150§ C

Symbol Parameter Min Nom Max Units
tW Pulse Width A or B High 40
(Note 6) A or B Low 40 ns
Clear Low 40
REXT External Timing Resistor 5 260 kX
CEXT External Timing Capacitance No Restriction mF
CWIRE Wiring Capacitance
50 pF
at REXT/CEXT Terminal
Typ
(Note 1)
2.7 3.4 V
0.35 0.5
Voltage VIL e Max, VIH e Min V
0.1 mA
Input Voltage
IOS Short Circuit VCC e Max b 20 b 100 mA
ICC Supply Current VCC e Max (Notes 3,4 and 5) 12 20 mA
Note 3: Quiescent ICC is measured (after clearing) with 2.4V applied to all clear and A inputs, B inputs grounded, all outputs open, CEXT e 0.02 mF, and
REXT e 25 kX.
Note 4: ICC is measured in the triggered state with 2.4V applied to all clear and B inputs, A inputs grounded, all outputs open, CEXT e 0.02 mF, and REXT e 25 kX.
Note 5: With all outputs open and 4.5V applied to all data and clear inputs, ICC is measured after a momentary ground, then 4.5V is applied to the clock.
2
RL e 2 kX
From (Input) CL e 15pF CL e 15pF
Symbol Parameters Units
To (Output) CEXT e 0 pF, REXT e 5 kX CEXT e 1000 pF, REXT e 10 KX
Min Max Min Max
A to Q 33 ns
B to Q 44 ns
A to Q 45 ns
B to Q 56 ns
Clear to Q 45 ns
Clear to Q 27 ns
tWQ(Min) Minimum Width of Pulse
A or B to Q 200 ns
at Output Q
tW(out) Output Pulse Width A or B to Q 4 5 ms
Operating Rules
1. An external resistor (RX) and an external capacitor (CX) 3. For CX ll 1000 pF the output pulse width (TW) is de-
are required for proper operation. The value of CX may fined as follows:
vary from 0 to any necessary value. For small time con- TW e KRX CX
stants high-grade mica, glass, polypropylene, polycarbon- where [RX is in kX]
ate, or polystyrene material capacitors may be used. For
[CX is in pF]
large time constants use tantalum or special aluminum
capacitors. If the timing capacitors have leakages ap- [TW is in ns]
proaching 100 nA or if stray capacitance from either ter- K & 0.37
minal to ground is greater than 50 pF the timing equations 4. The multiplicative factor K is plotted as a function of CX
may not represent the pulse width the device generates. below for design considerations:
2. When an electrolytic capacitor is used for CX a switching
diode is often required for standard TTL one-shots to pre-
vent high inverse leakage current. This switching diode is
not needed for the ’LS123 one-shot and should not be
used. In general the use of the switching diode is not
recommended with retriggerable operation.
Furthermore, if a polarized timing capacitor is used on the
’LS123 the negative terminal of the capacitor should be
connected to the ‘‘CEXT’’ pin of the device (Figure 1 ).
TL/F/6386 – 2
FIGURE 2
TL/F/6386 – 8
FIGURE 1
3
Operating Rules (Continued)
5. For CX k 1000 pF see Figure 3 for TW vs CX family
curves with RX as a parameter:
TL/F/6386 – 7
FIGURE 7
9. Under any operating condition CX and RX must be kept
TL/F/6386 – 3 as close to the one-shot device pins as possible to mini-
FIGURE 3 mize stray capacitance, to reduce noise pick-up, and to
6. To obtain variable pulse widths by remote trimming, the reduce I-R and Ldi/dt voltage developed along their
following circuit is recommended: connecting paths. If the lead length from CX to pins (6)
and (7) or pins (14) and (15) is greater than 3 cm, for
example, the output pulse width might be quite different
from values predicted from the appropriate equations. A
non-inductive and low capacitive path is necessary to
ensure complete discharge of CX in each cycle of its
operation so that the output pulse width will be accurate.
TL/F/6386 – 4
10. The CEXT pins of this device are internally connected to
FIGURE 4 the internal ground. For optimum system performance
Note: ‘‘Rremote’’ should be as close to the device pin as possible. they should be hard wired to the system’s return ground
7. The retriggerable pulse width is calculated as shown be- plane.
low: 11. VCC and ground wiring should conform to good high-fre-
T e TW a tPLH e K c RX c CX a tPLH quency standards and practices so that switching tran-
The retriggered pulse width is equal to the pulse width sients on the VCC and ground return leads do not cause
plus a delay time period (Figure 5). interaction between one-shots. A 0.01 mF to 0.10 mF
bypass capacitor (disk ceramic or monolithic type) from
VCC to ground is necessary on each device. Further-
more, the bypass capacitor should be located as close
to the VCC-pin as space permits.
For further detailed device characteristics and output performance
please refer to the NSC one-shot application note AN-372.
TL/F/6386 – 5
FIGURE 5
8. Output pulse width variation versus VCC and tempera-
tures: Figure 6 depicts the relationship between pulse
width variation versus VCC, and Figure 7 depicts pulse
width variation versus temperatures.
TL/F/6386 – 6
FIGURE 6
4
16-Lead Small Outline Molded Package

5

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54LS125A/DM54LS125A/DM74LS125A Quad TRI-STATE Buffers
June 1989
54LS125A/DM54LS125A/DM74LS125A
Quad TRI-STATEÉ Buffers
General Description
This device contains four independent gates each of which that two outputs will attempt to take a common bus to oppo-
performs a non-inverting buffer function. The outputs have site logic levels, the disable time is shorter than the enable
the TRI-STATE feature. When enabled, the outputs exhibit time of the outputs.
the low impedance characteristics of a standard LS output
with additional drive capability to permit the driving of bus Features
lines without external resistors. When disabled, both the Y Alternate Military/Aerospace device (54LS125) is avail-
output transistors are turned off presenting a high-imped- able. Contact a National Semiconductor Sales Office/
ance state to the bus line. Thus the output will act neither as Distributor for specifications.
a significant load nor as a driver. To minimize the possibility
Connection Diagram
TL/F/6387 – 1
Order Number 54LS125ADMQB, 54LS125AFMQB, 54LS125ALMQB,
DM54LS125AJ, DM54LS125AW, DM74LS125AM or DM74LS125AN
Function Table
YeA
Inputs Output
A C Y
L L L
H L H
X H Hi-Z
L e Low Logic Level
Hi-Z e TRI-STATE (Outputs are disabled)
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.

Input Voltage 7V

DM54LS125A DM74LS125A
IOH High Level Output Current b1 b 2.6 mA
Typ
(Note 1)
2.4 3.4 V
Voltage VIL e Max
DM74 0.35 0.5 V
0.1 mA
Input Voltage
IIH High Level Input VCC e Max, VI e 2.7V 20 mA
Current
IIL Low Level Input VCC e Max, VI e 0.4V b 0.4 mA
Current
IOZH Off-State Output Current VCC e Max, VO e 2.4V
with High Level Output VIH e Min, VIL e Max 20 mA
Voltage Applied
IOZL Off-State Output Current VCC e Max, VO e 0.4V
with Low Level Output VIH e Min, VIL e Max b 20 mA
Voltage Applied
mA
DM74 b 20 b 100
Note 3: ICC is measured with the data control (C) inputs at 4.5V and the data inputs grounded.
2
RL e 667X
Min Max Min Max
tPLH Propagation Delay Time Low
15 21 ns
to High Level Output
tPHL Propagation Delay Time High
18 22 ns
to Low Level Output
tPZH Output Enable Time to
25 35 ns
High Level Output
tPZL Output Enable Time to
25 40 ns
Low Level Output
tPHZ Output Disable Time from
20 ns
High Level Output (Note 1)
tPLZ Output Disable Time from
20 ns
Low Level Output (Note 1)
Note 1: CL e 5pF.
3

Order Number 54LS125ALMQB

Order Number 54LS125ADMQB or DM54LS125AJ
4


5
54LS125A/DM54LS125A/DM74LS125A Quad TRI-STATE Buffers

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DM54LS132/DM74LS132 Quad 2-Input NAND Gates with Schmitt Trigger Inputs
June 1989
DM54LS132/DM74LS132 Quad 2-Input

NAND Gates with Schmitt Trigger Inputs
General Description
This device contains four independent gates each of which
performs the logic NAND function. Each input has hystere-
sis which increases the noise immunity and transforms a
slowly changing input signal to a fast changing, jitter free
output.
Connection Diagram
TL/F/6389 – 1
Order Number DM54LS132J, DM54LS132W, DM74LS132M or DM74LS132N
Function Table
Y e AB
Inputs Output
A B Y
L L H
L H H
H L H
H H L
L e Low Logic Level

Input Voltage 7V
DM54LS b 55§ C to a 125§ C

DM54LS132 DM74LS132
VT a Positive-Going Input
1.4 1.6 1.9 1.4 1.6 1.9 V
VTb Negative-Going Input
0.5 0.8 1 0.5 0.8 1 V
HYS Input Hysteresis (Note 1) 0.4 0.8 0.4 0.8 V
Typ
(Note 2)
V
Voltage VI e VTb Min
DM74 2.7 3.4
Voltage
VI e VT a Max DM74 0.35 0.5 V
IT a Input Current at VCC e 5V, VI e VT a
b 0.14 mA
Positive-Going Threshold
IT b Input Current at VCC e 5V, VI e VTb
b 0.18 mA
Negative-Going Threshold
0.1 mA
Input Voltage
mA
DM74 b 20 b 100

5.9 11 mA
Outputs High
8.2 14 mA
Outputs Low
Note 1: VCC e 5V
2
Switching Characteristics at VCC 5V and TA e 25§ C (See Section 1 for Test Waveforms and Output Load)
RL e 2 kX
Min Max Min Max
5 22 8 25 ns
5 22 10 33 ns


3
DM54LS132/DM74LS132 Quad 2-Input NAND Gates with Schmitt Trigger Inputs


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IMPORTANT NOTICE


54LS139/DM54LS139/DM74LS139 Decoders/Demultiplexers
54LS138/DM54LS138/DM74LS138,
June 1989
54LS138/DM54LS138/DM74LS138,
54LS139/DM54LS139/DM74LS139
Decoders/Demultiplexers
General Description
These Schottky-clamped circuits are designed to be used in Schottky diodes to suppress line-ringing and simplify system
high-performance memory-decoding or data-routing appli- design.
cations, requiring very short propagation delay times. In
high-performance memory systems these decoders can be Features
used to minimize the effects of system decoding. When Y Designed specifically for high speed:
used with high-speed memories, the delay times of these Memory decoders
decoders are usually less than the typical access time of the Data transmission systems
memory. This means that the effective system delay intro- Y LS138 3-to-8-line decoders incorporates 3 enable in-
duced by the decoder is negligible.
puts to simplify cascading and/or data reception
The LS138 decodes one-of-eight lines, based upon the con- Y LS139 contains two fully independent 2-to-4-line decod-
ditions at the three binary select inputs and the three enable ers/demultiplexers
inputs. Two active-low and one active-high enable inputs Y Schottky clamped for high performance
reduce the need for external gates or inverters when ex- Y Typical propagation delay (3 levels of logic)
panding. A 24-line decoder can be implemented with no ex-
LS138 21 ns
ternal inverters, and a 32-line decoder requires only one
LS139 21 ns
inverter. An enable input can be used as a data input for
demultiplexing applications.
Y Typical power dissipation
LS138 32 mW
The LS139 comprises two separate two-line-to-four-line de-
LS139 34 mW
coders in a single package. The active-low enable input can Y Alternate Military/Aerospace devices (54LS138,
be used as a data line in demultiplexing applications.
54LS139) are available. Contact a National Semicon-
All of these decoders/demultiplexers feature fully buffered ductor Sales Office/Distributor for specifications.
inputs, presenting only one normalized load to its driving
circuit. All inputs are clamped with high-performance
Connection Diagrams
Dual-in-Line Package
Dual-in-Line Package
TL/F/6391 – 1 TL/F/6391 – 2
Order Number 54LS138DMQB, 54LS138FMQB, Order Number 54LS139DMQB, 54LS139FMQB,
54LS138LMQB, DM54LS138J, DM54LS138W, 54LS139LMQB, DM54LS139J, DM54LS139W,
DM74LS138M or DM74LS138N DM74LS139M or DM74LS139N
See NS Package Number E20A, J16A, See NS Package Number E20A, J16A,
M16A, N16E or W16A M16A, N16E or W16A

Input Voltage 7V

DM54LS138 DM74LS138

Typ
(Note 1)
V
DM74 2.7 3.4
DM74 0.35 0.5 V
0.1 mA
Input Voltage
mA
ICC Supply Current VCC e Max (Note 3) 6.3 10 mA

Note 3: ICC is measured with all outputs enabled and open.
2
RL e 2 kX
From (Input) Levels
Symbol Parameter To (Output) of Delay CL e 15 pF CL e 50 pF Units
Min Max Min Max
tPLH Propagation Delay Time Select to
2 18 27 ns
Low to High Level Output Output
tPHL Propagation Delay Time Select to
2 27 40 ns
High to Low Level Output Output
3 18 27 ns
3 27 40 ns
tPLH Propagation Delay Time Enable to
2 18 27 ns
tPHL Propagation Delay Time Enable to
2 24 40 ns
3 18 27 ns
3 28 40 ns

DM54LS139 DM74LS139
3
Typ
(Note 1)
V
0.1 mA
Input Voltage
mA

Note 3: ICC is measured with all outputs enabled and open.

RL e 2 kX
From (Input)
Min Max Min Max
18 27 ns
27 40 ns
18 27 ns
24 40 ns
Function Tables
LS138 LS139
Inputs Inputs
Outputs Outputs
Enable Select Enable Select
G1 G2* C B A YO Y1 Y2 Y3 Y4 Y5 Y6 Y7 G B A Y0 Y1 Y2 Y3
X H X X X H H H H H H H H H X X H H H H
L X X X X H H H H H H H H L L L L H H H
H L L L L L H H H H H H H L L H H L H H
H L L L H H L H H H H H H L H L H H L H
H L L H L H H L H H H H H L H H H H H L
H L L H H H H H L H H H H H e High Level, L e Low Level, X e Don’t Care
H L H L L H H H H L H H H
H L H L H H H H H H L H H
H L H H L H H H H H H L H
H L H H H H H H H H H H L
* G2 e G2A a G2B
4
Logic Diagrams
LS138
TL/F/6391 – 3
LS139
TL/F/6391 – 4
5

Order Number 54LS138LMQB or 54LS139LMQB

Order Number 54LS138DMQB, 54LS139DMQB, DM54LS138J or DM54LS139J
6

NS Packge Number M16A

7
54LS138/DM54LS138/DM74LS138,
54LS139/DM54LS139/DM74LS139 Decoders/Demultiplexers

Order Number 54LS138FMQB, 54LS139FMQB, DM54LS138W or DM54LS139W
LIFE SUPPORT POLICY
to the user.

Fran3ais Tel: (a49) 0-180-532 93 58 Tel: (852) 2737-1600
IMPORTANT NOTICE


IMPORTANT NOTICE


IMPORTANT NOTICE


IMPORTANT NOTICE


IMPORTANT NOTICE


IMPORTANT NOTICE


DM54LS154/DM74LS154 4-Line to 16-Line Decoders/Demultiplexers
May 1989
DM54LS154/DM74LS154 4-Line to 16-Line

Decoders/Demultiplexers
Each of these 4-line-to-16-line decoders utilizes TTL circuit- Y Decodes 4 binary-coded inputs into one of 16 mutually
ry to decode four binary-coded inputs into one of sixteen exclusive outputs
mutually exclusive outputs when both the strobe inputs, G1 Y Performs the demultiplexing function by distributing data
and G2, are low. The demultiplexing function is performed from one input line to any one of 16 outputs
by using the 4 input lines to address the output line, passing Y Input clamping diodes simplify system design
data from one of the strobe inputs with the other strobe Y High fan-out, low-impedance, totem-pole outputs
input low. When either strobe input is high, all outputs are Y Typical propagation delay
high. These demultiplexers are ideally suited for implement- 3 levels of logic 23 ns
ing high-performance memory decoders. All inputs are buff- Strobe 19 ns
ered and input clamping diodes are provided to minimize Y Typical power dissipation 45 mW
transmission-line effects and thereby simplify system de-
sign.
Connection and Logic Diagrams

TL/F/6394–1
Order Number DM54LS154J,
DM74LS154WM or DM74LS154N
See NS Package Number J24A, M24B or N24A
TL/F/6394 – 2

Input Voltage 7V
DM54LS b 55§ C to a 125§ C

DM54LS154 DM74LS154
Typ
(Note 1)
V
DM74 2.7 3.4
DM74 0.35 0.5 V
0.1 mA
Input Voltage
mA
DM74 b 20 b 100
Note 3: ICC is measured with all outputs open and all inputs grounded.
RL e 2 kX
From (Input)
Min Max Min Max
tPLH Propagation Delay Time Data to
30 35 ns
tPHL Propagation Delay Time Data to
30 35 ns
tPLH Propagation Delay Time Strobe to
20 25 ns
tPHL Propagation Delay Time Strobe to
25 35 ns
2
Function Table
Inputs Outputs
G1 G2 D C B A 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
L L L L L L L H H H H H H H H H H H H H H H
L L L L L H H L H H H H H H H H H H H H H H
L L L L H L H H L H H H H H H H H H H H H H
L L L L H H H H H L H H H H H H H H H H H H
L L L H L L H H H H L H H H H H H H H H H H
L L L H L H H H H H H L H H H H H H H H H H
L L L H H L H H H H H H L H H H H H H H H H
L L L H H H H H H H H H H L H H H H H H H H
L L H L L L H H H H H H H H L H H H H H H H
L L H L L H H H H H H H H H H L H H H H H H
L L H L H L H H H H H H H H H H L H H H H H
L L H L H H H H H H H H H H H H H L H H H H
L L H H L L H H H H H H H H H H H H L H H H
L L H H L H H H H H H H H H H H H H H L H H
L L H H H L H H H H H H H H H H H H H H L H
L L H H H H H H H H H H H H H H H H H H H L
L H X X X X H H H H H H H H H H H H H H H H
H L X X X X H H H H H H H H H H H H H H H H
H H X X X X H H H H H H H H H H H H H H H H
3
4


Order Number DM74LS154WM
5
DM54LS154/DM74LS154 4-Line to 16-Line Decoders/Demultiplexers

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to the user.

Fran3ais Tel: (a49) 0-180-532 93 58 Tel: (852) 2737-1600
IMPORTANT NOTICE


IMPORTANT NOTICE


Quad 2-Line to 1-Line Data Selectors/Multiplexers
54LS157/DM54LS157/DM74LS157, 54LS158/DM54LS158/DM74LS158
June 1989
54LS157/DM54LS157/DM74LS157,
54LS158/DM54LS158/DM74LS158
These data selectors/multiplexers contain inverters and Y Buffered inputs and outputs
drivers to supply full on-chip data selection to the four out- Y Typical Propagation Time
put gates. A separate strobe input is provided. A 4-bit word LS157 9 ns
is selected from one of two sources and is routed to the four LS158 7 ns
outputs. The LS157 presents true data whereas the LS158 Y Typical Power Dissipation
presents inverted data to minimize propagation delay time. LS157 49 mW
LS158 24 mW
Applications Y Alternate Military/Aerospace device (54LS157,
Y Expand any data input point 54LS158) is available. Contact a National Semiconduc-
Y Multiplex dual data buses tor Sales Office/Distributor for specifications.
Y Generate four functions of two variables (one variable
is common)
Y Source programmable counters
Connection Diagrams
Dual-In-Line Package Dual-In-Line Package
TL/F/6396 – 1 TL/F/6396 – 2

54LS157LMQB, DM54LS157J, DM54LS157W, 54LS158LMQB, DM54LS158J, DM54LS158W,
DM74LS157M or DM74LS157N DM74LS158M or DM74LS158N
Function Table
Inputs Output Y
Strobe Select A B LS157 LS158
H X X X L H
L L L X L H
L L H X H L
L H X L L H
L H X H H L

Input Voltage 7V

DM54LS157 DM74LS157

Typ
(Note 1)
V
DM74 2.7 3.4
DM74 0.35 0.5 V
II Input Current @ Max VCC e Max S or G 0.2
mA
A or B 0.1
IIH High Level Input VCC e Max S or G 40
mA
Current VI e 2.7V
A or B 20
IIL Low Level Input VCC e Max S or G b 0.8
mA
Current VI e 0.4V
A or B b 0.4

mA

Note 3: ICC is measured with 4.5V applied to all inputs and all outputs open.
2
RL e 2 kX
From (Input)
Min Max Min Max
tPLH Propagation Delay Time Data
14 18 ns
Low to High Level Output to Y
tPHL Propagation Delay Time Data
14 23 ns
High to Low Level Output to Y
tPLH Propagation Delay Time Strobe
20 24 ns
tPHL Propagation Delay Time Strobe
21 30 ns
tPLH Propagation Delay Time Select
23 28 ns
tPHL Propagation Delay Time Select
27 32 ns

DM54LS158 DM74LS158

Typ
(Note 1)
V
DM74 2.7 3.4
DM74 0.35 0.5 V
II Input Current @ Max VCC e Max S or G 0.2
mA
A or B 0.1
IIH High Level Input VCC e Max S or G 40
mA
Current VI e 2.7V
A or B 20
IIL Low Level Input VCC e Max S or G b 0.8
mA
Current VI e 0.4V A or B b 0.4

mA

Note 3: ICC is measured with 4.5V applied to all inputs and all outputs open.
3
RL e 2 kX
From (Input)
Min Max Min Max
tPLH Propagation Delay Time Data
12 18 ns
tPHL Propagation Delay Time Data
12 21 ns
tPLH Propagation Delay Time Strobe
17 23 ns
tPHL Propagation Delay Time Strobe
18 28 ns
tPLH Propagation Delay Time Select
20 24 ns
tPHL Propagation Delay Time Select
24 36 ns
Logic Diagrams
LS157 LS158
TL/F/6396–3 TL/F/6396 – 4
4
5


Order Number 54LS157DMQB, 54LS158DMQB, DM54LS157J or DM54LS158J
6


7

LIFE SUPPORT POLICY
to the user.

Fran3ais Tel: (a49) 0-180-532 93 58 Tel: (852) 2737-1600
IMPORTANT NOTICE


SN54/74LS160A
SN54/74LS161A
BCD DECADE COUNTERS/ SN54/74LS162A
4-BIT BINARY COUNTERS SN54/74LS163A
The LS160A / 161A / 162A / 163A are high-speed 4-bit synchronous count-
ers. They are edge-triggered, synchronously presettable, and cascadable
MSI building blocks for counting, memory addressing, frequency division and
other applications. The LS160A and LS162A count modulo 10 (BCD). The BCD DECADE COUNTERS /
LS161A and LS163A count modulo 16 (binary.) 4-BIT BINARY COUNTERS
The LS160A and LS161A have an asynchronous Master Reset (Clear)
input that overrides, and is independent of, the clock and all other control LOW POWER SCHOTTKY
inputs. The LS162A and LS163A have a Synchronous Reset (Clear) input that
overrides all other control inputs, but is active only during the rising clock
edge.
BCD (Modulo 10) Binary (Modulo 16)
Asynchronous Reset LS160A LS161A J SUFFIX
CERAMIC
Synchronous Reset LS162A LS163A
CASE 620-09
16
• Synchronous Counting and Loading 1
• Two Count Enable Inputs for High Speed Synchronous Expansion

• Terminal Count Fully Decoded
• Edge-Triggered Operation
N SUFFIX
• Typical Count Rate of 35 MHz PLASTIC
• ESD > 3500 Volts CASE 648-08
16
1
CONNECTION DIAGRAM DIP (TOP VIEW)
VCC TC Q0 Q1 Q2 Q3 CET PE
16 15 14 13 12 11 10 9 D SUFFIX
NOTE: SOIC
16
The Flatpak version
1 CASE 751B-03
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
*MR for LS160A and LS161A
*SR for LS162A and LS163A SN54LSXXXJ Ceramic
1 2 3 4 5 6 7 8 SN74LSXXXN Plastic
*R CP P0 P1 P2 P3 CEP GND SN74LSXXXD SOIC
PIN NAMES LOADING (Note a) LOGIC SYMBOL

HIGH LOW 9 3 4 5 6
PE Parallel Enable (Active LOW) Input 1.0 U.L. 0.5 U.L.
P0 – P3 Parallel Inputs 0.5 U.L. 0.25 U.L.
CEP Count Enable Parallel Input 0.5 U.L. 0.25 U.L. PE P0 P1 P2 P3
7 CEP
CET Count Enable Trickle Input 1.0 U.L. 0.5 U.L.
CP Clock (Active HIGH Going Edge) Input 0.5 U.L. 0.25 U.L. 10 CET TC 15
MR Master Reset (Active LOW) Input 0.5 U.L. 0.25 U.L. 2 CP
SR Synchronous Reset (Active LOW) Input 1.0 U.L. 0.5 U.L. *R Q0 Q1 Q2 Q3
Q0 – Q3 Parallel Outputs (Note b) 10 U.L. 5 (2.5) U.L.
TC Terminal Count Output (Note b) 10 U.L. 5 (2.5) U.L.
NOTES: 1 14 13 12 11
a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. VCC = PIN 16
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) GND = PIN 8
Temperature Ranges.
*MR for LS160A and LS161A
*SR for LS162A and LS163A

5-1
SN54/74LS160A • SN54/74LS161A
SN54/74LS162A • SN54/74LS163A
STATE DIAGRAM
LS160A • LS162A LS161A • LS163A
LOGIC EQUATIONS
0 1 2 3 4 0 1 2 3 4
Count Enable = CEP • CET • PE
TC for LS160A & LS162A = CET • Q0 • Q1 • Q2 • Q3
TC for LS161A & LS163A = CET • Q0 • Q1 • Q2 • Q3
15 5 15 5 Preset = PE • CP + (rising clock edge)
Reset = MR (LS160A & LS161A)
Reset = SR • CP + (rising clock edge)
14 6 14 6 Reset = (LS162A & LS163A)
13 7 13 7 NOTE:
The LS160A and LS162A can be preset to any state,
but will not count beyond 9. If preset to state 10, 11,
12 11 10 9 8 12 11 10 9 8 12, 13, 14, or 15, it will return to its normal sequence
within two clock pulses.
FUNCTIONAL DESCRIPTION
The LS160A / 161A / 162A / 163A are 4-bit synchronous the Binary counters). Note that TC is fully decoded and will,
counters with a synchronous Parallel Enable (Load) feature. therefore, be HIGH only for one count state.
The counters consist of four edge-triggered D flip-flops with The LS160A and LS162A count modulo 10 following a
the appropriate data routing networks feeding the D inputs. All binary coded decimal (BCD) sequence. They generate a TC
changes of the Q outputs (except due to the asynchronous output when the CET input is HIGH while the counter is in state
Master Reset in the LS160A and LS161A) occur as a result of, 9 (HLLH). From this state they increment to state 0 (LLLL). If
and synchronous with, the LOW to HIGH transition of the loaded with a code in excess of 9 they return to their legitimate
Clock input (CP). As long as the set-up time requirements are sequence within two counts, as explained in the state
met, there are no special timing or activity constraints on any diagram. States 10 through 15 do not generate a TC output.
of the mode control or data inputs. The LS161A and LS163A count modulo 16 following a
Three control inputs — Parallel Enable (PE), Count Enable binary sequence. They generate a TC when the CET input is
Parallel (CEP) and Count Enable Trickle (CET) — select the HIGH while the counter is in state 15 (HHHH). From this state
mode of operation as shown in the tables below. The Count they increment to state 0 (LLLL).
Mode is enabled when the CEP, CET, and PE inputs are HIGH. The Master Reset (MR) of the LS160A and LS161A is
When the PE is LOW, the counters will synchronously load the asynchronous. When the MR is LOW, it overrides all other
data from the parallel inputs into the flip-flops on the LOW to input conditions and sets the outputs LOW. The MR pin should
HIGH transition of the clock. Either the CEP or CET can be never be left open. If not used, the MR pin should be tied
used to inhibit the count sequence. With the PE held HIGH, a through a resistor to VCC, or to a gate output which is
LOW on either the CEP or CET inputs at least one set-up time permanently set to a HIGH logic level.
prior to the LOW to HIGH clock transition will cause the The active LOW Synchronous Reset (SR) input of the
existing output states to be retained. The AND feature of the LS162A and LS163A acts as an edge-triggered control input,
two Count Enable inputs (CET • CEP) allows synchronous overriding CET, CEP and PE, and resetting the four counter
cascading without external gating and without delay accu- flip-flops on the LOW to HIGH transition of the clock. This
mulation over any practical number of bits or digits. simplifies the design from race-free logic controlled reset
The Terminal Count (TC) output is HIGH when the Count circuits, e.g., to reset the counter synchronously after
Enable Trickle (CET) input is HIGH while the counter is in its reaching a predetermined value.
maximum count state (HLLH for the BCD counters, HHHH for
MODE SELECT TABLE

*SR PE CET CEP Action on the Rising Clock Edge ( )
L X X X RESET (Clear) *For the LS162A and
H L X X LOAD (Pn → Qn) *LS163A only.
H H H H COUNT (Increment) H = HIGH Voltage Level
H H L X NO CHANGE (Hold) L = LOW Voltage Level
H H X L NO CHANGE (Hold) X = Don’t Care

5-2
SN54/74LS160A • SN54/74LS161A
SN54/74LS162A • SN54/74LS163A
GUARANTEED OPERATING RANGES

Symbol Parameter Min Typ Max Unit
VCC Supply Voltage 54 4.5 5.0 5.5 V
74 4.75 5.0 5.25
TA Operating Ambient Temperature Range 54 – 55 25 125 °C
74 0 25 70
IOH Output Current — High 54, 74 – 0.4 mA
IOL Output Current — Low 54 4.0 mA
74 8.0
LS160A and LS161A

Limits
S b l
Symbol P
Unit T
Test C
Conditions
di i
All Inputs
p LOW Voltage
g for
74 0.8 All Inputs
VIK Input Clamp Diode Voltage – 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA
54 2.5 3.5 V VCC = MIN,, IOH = MAX,, VIN = VIH
VOH Output HIGH Voltage
74 2.7 3.5 V or VIL per Truth Table
54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN,

VOL Output LOW Voltage VIN = VIL or VIH
74 0.35 0.5 V IOL = 8.0 mA per Truth Table
Input HIGH Current

MR, Data, CEP, Clock 20 µA VCC = MAX, VIN = 2.7 V
IIH PE, CET 40
MR, Data, CEP, Clock 0.1 mA VCC = MAX, VIN = 7.0 V
PE, CET 0.2
Input LOW Current
IIL MR, Data, CEP, Clock – 0.4 mA VCC = MAX, VIN = 0.4 V
PE, CET – 0.8
IOS Short Circuit Current (Note 1) – 20 – 100 mA VCC = MAX
Power Supply Current
ICC Total, Output HIGH 31 mA VCC = MAX
Total, Output LOW 32

5-3
SN54/74LS160A • SN54/74LS161A
SN54/74LS162A • SN54/74LS163A
LS162A and LS163A

Limits
S b l
Symbol P
Unit T
Test C
Conditions
di i
All Inputs
p LOW Voltage
g for
74 0.8 All Inputs
VIK Input Clamp Diode Voltage – 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA
54 2.5 3.5 V VCC = MIN,, IOH = MAX,, VIN = VIH
VOH Output HIGH Voltage
74 2.7 3.5 V or VIL per Truth Table
54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN,

VOL Output LOW Voltage VIN = VIL or VIH
74 0.35 0.5 V IOL = 8.0 mA per Truth Table
Input HIGH Current

Data, CEP, Clock 20 µA VCC = MAX, VIN = 2.7 V
IIH PE, CET, SR 40
Data, CEP, Clock 0.1 mA VCC = MAX, VIN = 7.0 V
PE, CET, SR 0.2
Input LOW Current
IIL Data, CEP, Clock, PE, SR – 0.4 mA VCC = MAX, VIN = 0.4 V
CET – 0.8
IOS Short Circuit Current (Note 1) – 20 – 100 mA VCC = MAX
Power Supply Current
ICC Total, Output HIGH 31 mA VCC = MAX
Total, Output LOW 32
AC CHARACTERISTICS (TA = 25°C)

Limits
S b l
Symbol P
Unit T
Test C
Conditions
di i
tPLH Propagation Delay 20 35
ns
tPHL Clock to TC 18 35
tPLH Propagation Delay 13 24 VCC = 5.0
50V
ns
tPHL Clock to Q 18 27 CL = 15 pF
tPLH Propagation Delay 9.0 14
ns
tPHL CET to TC 9.0 14
tPHL MR or SR to Q 20 28 ns

5-4
SN54/74LS160A • SN54/74LS161A
SN54/74LS162A • SN54/74LS163A
AC SETUP REQUIREMENTS (TA = 25°C)

Limits
S b l
Symbol P
Unit T
Test C
Conditions
di i
tWCP Clock Pulse Width Low 25 ns
tW MR or SR Pulse Width 20 ns
ts Setup Time, other* 20 ns
ts Setup Time PE or SR 25 ns VCC = 5.0
50V
th Hold Time, data 3 ns
th Hold Time, other 0 ns
trec Recovery Time MR to CP 15 ns
*CEP, CET or DATA
DEFINITION OF TERMS
SETUP TIME (ts) — is defined as the minimum time required nition. A negative HOLD TIME indicates that the correct logic
for the correct logic level to be present at the logic input prior to level may be released prior to the clock transition from LOW to
the clock transition from LOW to HIGH in order to be recog- HIGH and still be recognized.
nized and transferred to the outputs.
RECOVERY TIME (trec) — is defined as the minimum time re-
HOLD TIME (th) — is defined as the minimum time following quired between the end of the reset pulse and the clock transi-
the clock transition from LOW to HIGH that the logic level must tion from LOW to HIGH in order to recognize and transfer
be maintained at the input in order to ensure continued recog- HIGH Data to the Q outputs.
AC WAVEFORMS
tW
tW(H) tW(L) MR 1.3 V
1.3 V OTHER CONDITIONS: trec OTHER CONDITIONS:
CP 1.3 V
PE = MR (SR) = H PE = L
1.3 V
tPHL tPLH CEP = CET = H CP P0 = P1 = P2 = P3 = H
tPHL
Q 1.3 V 1.3 V
Q0 ⋅ Q1 ⋅ Q2 ⋅ Q3 1.3 V
Figure 1. Clock to Output Delays, Count Figure 2. Master Reset to Output Delay, Master Reset
Frequency, and Clock Pulse Width Pulse Width, and Master Reset Recovery Time

5-5
SN54/74LS160A • SN54/74LS161A
SN54/74LS162A • SN54/74LS163A
AC WAVEFORMS (continued)
COUNT ENABLE TRICKLE INPUT

TO TERMINAL COUNT OUTPUT DELAYS 1.3 V 1.3 V
CET
The positive TC pulse occurs when the outputs are in the tPLH tPHL
(Q0 • Q1 • Q2 • Q3) state for the LS160 and LS162 and the
(Q0 • Q1 • Q2 • Q3) state for the LS161 and LS163. TC 1.3 V 1.3 V
Figure 3 OTHER CONDITIONS: CP = PE = CEP = MR = H
CLOCK TO TERMINAL COUNT DELAYS

CP 1.3 V 1.3 V 1.3 V
The positive TC pulse is coincident with the output state tPLH tPHL
(Q0 • Q1 • Q2 • Q3) state for the LS161 and LS163 and
(Q0 • Q1 • Q2 • Q3) for the LS161 and LS163. TC 1.3 V 1.3 V
Figure 4 OTHER CONDITIONS: PE = CEP = CET = MR = H
CP 1.3 V 1.3 V
SETUP TIME (ts) AND HOLD TIME (th) ts(H) ts(L)

FOR PARALLEL DATA INPUTS th(H) = 0 th(L) = 0
The shaded areas indicate when the input is permitted to P0 • P1 • P2 • P3 1.3 V 1.3 V 1.3 V
change for predictable output performance.
Q0 • Q1 • Q2 • Q3
Figure 5 OTHER CONDITIONS: PE = L, MR = H
SETUP TIME (ts) AND HOLD TIME (th) FOR

COUNT ENABLE (CEP) AND (CET) AND
PARALLEL ENABLE (PE) INPUTS
The shaded areas indicate when the input is permitted to
change for predictable output performance.
CP 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V

CP
ts(L) ts(H) ts(H) ts(L)
th (L) = 0 th(H) = 0 th(H) = 0 th(L) = 0
SR or PE 1.3 V 1.3 V CEP 1.3 V 1.3 V
PARALLEL LOAD COUNT MODE ts(L)
(See Fig. 5) (See Fig. 7) ts(H)
th(H) = 0 th(L) = 0
Q RESPONSE TO PE 1.3 V 1.3 V
CET 1.3 V 1.3 V
RESET COUNT OR LOAD COUNT HOLD HOLD
Q RESPONSE TO SR Q
OTHER CONDITIONS: PE = H, MR = H
Figure 6 Figure 7

5-6
54LS164/DM54LS164/DM74LS164 8-Bit Serial In/Parallel Out Shift Registers
June 1989
54LS164/DM54LS164/DM74LS164
8-Bit Serial In/Parallel Out Shift Registers
These 8-bit shift registers feature gated serial inputs and an Y Gated (enable/disable) serial inputs
asynchronous clear. A low logic level at either input inhibits Y Fully buffered clock and serial inputs
entry of the new data, and resets the first flip-flop to the low Y Asynchronous clear
level at the next clock pulse, thus providing complete con- Y Typical clock frequency 36 MHz
trol over incoming data. A high logic level on either input Y Typical power dissipation 80 mW
enables the other input, which will then determine the state Y Alternate Military/Aerospace device (54LS164) is avail-
of the first flip-flop. Data at the serial inputs may be changed
while the clock is high or low, but only information meeting
the setup and hold time requirements will be entered. Clock-
ing occurs on the low-to-high level transition of the clock
input. All inputs are diode-clamped to minimize transmis-
sion-line effects.

Inputs Outputs
Clear Clock A B QA QB ... QH
L X X X L L ... L
H L X X QA0 QB0 ... QH0
H u H H H QAn ... QGn
H u L X L QAn ... QGn
H u X L L QAn ... QGn
H e High Level (steady state), L e Low Level (steady state)
X e Don’t Care (any input, including transitions)
u e Transition from low to high level
QA0, QB0, QH0 e The level of QA, QB, or QH, respectively, before the
indicated steady-state input conditions were established.
QAn, QGn e The level of QA or QG before the most recent u transition of
the clock; indicates a one-bit shift.
TL/F/6398 – 1
54LS164LMQB, DM54LS164J, DM54LS164W,
DM74LS164M or DM74LS164N
See NS Package Number E20A,
J14A, M14A, N14A or W14B
Logic Diagram
TL/F/6398 – 2

Input Voltage 7V
The ‘‘Recommended Operating Conditions’’ tables will de-
Operating Free Air Temperature Range fine the conditions for actual device operation.

DM54LS164 DM74LS164
tW Pulse Width Clock 20 20
ns
(Note 4) Clear 20 20
tSU Data Setup Time (Note 4) 17 17 ns
tH Data Hold Time (Note 4) 5 5 ns
tREL Clear Release Time (Note 4) 30 30 ns
Typ
(Note 1)
V
0.1 mA
Input Voltage
mA
Note 3: ICC is measured with all outputs open, the SERIAL input grounded, the CLOCK input at 2.4V, and a momentary ground, then 4.5V, applied to the CLEAR
input.
2
RL e 2 kX
From (Input)
Min Max Min Max
fMAX Maximum Clock Frequency 25 MHz
27 30 ns
32 40 ns
tPHL Propagation Delay Time Clear to
36 45 ns
Timing Diagram
TL/F/6398 – 3
3


4


5
54LS164/DM54LS164/DM74LS164 8-Bit Serial In/Parallel Out Shift Registers

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IMPORTANT NOTICE


IMPORTANT NOTICE


Hex/Quad D Flip-Flops with Clear
June 1989
54LS174/DM54LS174/DM74LS174,
54LS175/DM54LS175/DM74LS175
These positive-edge-triggered flip-flops utilize TTL circuitry Y LS174 contains six flip-flops with single-rail outputs
to implement D-type flip-flop logic. All have a direct clear Y LS175 contains four flip-flops with double-rail outputs
input, and the quad (175) versions feature complementary Y Buffered clock and direct clear inputs
outputs from each flip-flop. Y Individual data input to each flip-flop
Information at the D inputs meeting the setup time require- Y Applications include:
ments is transferred to the Q outputs on the positive-going Buffer/storage registers
edge of the clock pulse. Clock triggering occurs at a particu- Shift registers
lar voltage level and is not directly related to the transition Pattern generators
time of the positive-going pulse. When the clock input is at Y Typical clock frequency 40 MHz
either the high or low level, the D input signal has no effect Y Typical power dissipation per flip-flop 14 mW
at the output. Y Alternate Military/Aerospace device (54LS174,
54LS175) is available. Contact a National Semiconduc-
tor Sales Office/Distributor for specifications.
Connection Diagrams
TL/F/6404 – 1 TL/F/6404 – 2
54LS174LMQB, DM54LS174J, 54LS175LMQB, DM54LS175J
DM54LS174W, DM74LS174M or DM74LS174N DM54LS175W, DM74LS175M or DM74LS175N
Function Table (Each Flip-Flop)

H e High Level (steady state)
Inputs Outputs
L e Low Level (steady state)
Clear Clock D Q Q² X e Don’t Care
L X X L H u e Transition from low to high level

Q0 e The level of Q before the indicated steady-state input conditions were
H u H H L
established.
H u L L H ² e LS175 only
H L X Q0 Q0

Input Voltage 7V

DM54LS174 DM74LS174
ns

Typ
(Note 3)
V
0.1 mA
Input Voltage
IIL Low Level Input VCC e Max Clock b 0.4
Current VI e 0.4V Clear b 0.4 mA
Data b 0.36
mA
Note 5: With all outputs open and 4.5V applied to all data and clear inputs, ICC is measured after a momentary ground, then 4.5V applied to the clock.
2
RL e 2 kX
From (Input)
Min Max Min Max
30 32 ns
30 36 ns
35 42 ns

DM54LS175 DM74LS175
ns
(Note 3)
Clear 20 20
3
Typ
(Note 1)
V
0.1 mA
Input Voltage
IIL Low Level Input VCC e Max Clock b 0.4
Current VI e 0.4V Clear b 0.4 mA
Data b 0.36

mA
DM74 b 20 b 100

RL e 2 kX
From (Input)
Min Max Min Max
30 32 ns
30 36 ns
tPLH Propagation Delay Time Clear to
25 29 ns
Low to High Level Output Q
35 42 ns
High to Low Level Output Q
Note 3: With all outputs open and 4.5V applied to all data and clear inputs, ICC is measured after a momentary ground, then 4.5V applied to the clock input.
4
Logic Diagrams
LS174 LS175
TL/F/6404 – 4
TL/F/6404 – 3
5


Order Number DM54LS174DMQB, 54LS175DMQB, DM54LS174J or DM54LS175J
6


7

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IMPORTANT NOTICE


IMPORTANT NOTICE


54LS193/DM54LS193/DM74LS193 Synchronous 4-Bit Up/Down Counters with Dual Clock
June 1989
54LS193/DM54LS193/DM74LS193
Synchronous 4-Bit Up/Down Binary
Counters with Dual Clock
General Description
This circuit is a synchronous up/down 4-bit binary counter. These counters were designed to be cascaded without the
Synchronous operation is provided by having all flip-flops need for external circuitry. Both borrow and carry outputs
clocked simultaneously, so that the outputs change togeth- are available to cascade both the up and down counting
er when so instructed by the steering logic. This mode of functions. The borrow output produces a pulse equal in
operation eliminates the output counting spikes normally as- width to the count down input when the counter underflows.
sociated with asynchronous (ripple-clock) counters. Similarly, the carry output produces a pulse equal in width to
The outputs of the four master-slave flip-flops are triggered the count down input when an overflow condition exists.
by a low-to-high level transition of either count (clock) input. The counters can then be easily cascaded by feeding the
The direction of counting is determined by which count input borrow and carry outputs to the count down and count up
is pulsed while the other count input is held high. inputs respectively of the succeeding counter.
The counter is fully programmable; that is, each output may
be preset to either level by entering the desired data at the Features
inputs while the load input is low. The output will change Y Fully independent clear input
independently of the count pulses. This feature allows the Y Synchronous operation
counters to be used as modulo-N dividers by simply modify- Y Cascading circuitry provided internally
ing the count length with the preset inputs. Y Individual preset each flip-flop
A clear input has been provided which, when taken to a high Y Alternate Military/Aerospace device (54LS193) is avail-
level, forces all outputs to the low level; independent of the able. Contact a National Semiconductor Sales Office/
count and load inputs. The clear, count, and load inputs are Distributor for specifications.
buffered to lower the drive requirements of clock drivers,
etc., required for long words.
Connection Diagram
TL/F/6406 – 1
See NS Package Number E20A, J16A, M16A, N16E or W16A

Input Voltage 7V

DM54LS193 DM74LS193
Clock Frequency (Note 2) 0 20 0 20 MHz
tW Pulse Width of Any Input (Note 6) 20 20 ns
tREL Release Time (Note 6) 40 40 ns
Typ
(Note 3)
V
DM74 2.7 3.4
DM74 0.35 0.5 V
0.1 mA
Input Voltage
mA

Note 1: CL e 15 pF, RL e 2 kX, IA e 25§ C and VCC e 5V.
Note 2: CL e 50 pF, RL e 2 kX, IA e 25§ C and VCC e 5V.
Note 5: ICC is measured with all outputs open, CLEAR and LOAD inputs grounded, and all other inputs at 4.5V.
2
RL e 2 kX
From (Input)
Min Max Min Max

tPLH Propagation Delay Time Count Up
26 30 ns
Low to High Level Output to Carry
tPHL Propagation Delay Time Count Up
24 36 ns
High to Low Level Output to Carry
tPLH Propagation Delay Time Count Down
24 29 ns
Low to High Level Output to Borrow
tPHL Propagation Delay Time Count Down
24 32 ns
High to Low Level Output to Borrow
tPLH Propagation Delay Time Either Count
38 45 ns
Low to High Level Output to Any Q
tPHL Propagation Delay Time Either Count
47 54 ns
High to Low Level Output to Any Q
tPLH Propagation Delay Time Load to
40 41 ns
Low to High Level Output Any Q
tPHL Propagation Delay Time Load to
40 47 ns
35 44 ns
3
Logic Diagram
TL/F/6406 – 2
4
Timing Diagrams
Typical Clear, Load, and Count Sequences
TL/F/6406 – 3
Note A: Clear overrides load, data, and count inputs.
Note B: When counting up, count-down input must be high; when counting down, count-up input must be high.
5


6


7
54LS193/DM54LS193/DM74LS193 Synchronous 4-Bit Up/Down Counters with Dual Clock

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DM74LS221 Dual Non-Retriggerable One-Shot with Clear and Complementary Outputs
February 1992
DM74LS221 Dual Non-Retriggerable One-Shot

Y Pin-out identical to ’LS123 (Note 1)
General Description Y Output pulse width range from 30 ns to 70 seconds
The DM74LS221 is a dual monostable multivibrator with Y Hysteresis provided at (B) input for added noise
Schmitt-trigger input. Each device has three inputs permit-
immunity
ting the choice of either leading-edge or trailing-edge trig-
gering. Pin (A) is an active-low trigger transition input and
Y Direct reset terminates output pulse
pin (B) is an active-high transition Schmitt-trigger input that Y Triggerable from CLEAR input
allows jitter free triggering for inputs with transition rates as Y DTL, TTL compatible
slow as 1 volt/second. This provides the input with excellent Y Input clamp diodes
noise immunity. Additionally an internal latching circuit at the Note 1: The pin-out is identical to ’LS123 but, functionally it is not; refer to
input stage also provides a high immunity to VCC noise. The Operating Rules Ý10 in this datasheet.
clear (CLR) input can terminate the output pulse at a prede-
termined time independent of the timing components. This Functional Description
(CLR) input also serves as a trigger input when it is pulsed The basic output pulse width is determined by selection of
with a low level pulse transition (ß). To obtain the best an external resistor (RX) and capacitor (CX). Once triggered,
and trouble free operation from this device please read op- the basic pulse width is independent of further input tran-
erating rules as well as the NSC one-shot application notes sitions and is a function of the timing components, or it may
carefully and observe recommendations. be reduced or terminated by use of the active low CLEAR
input. Stable output pulse width ranging from 30 ns to 70
Features seconds is readily obtainable.
Y A dual, highly stable one-shot
Y Compensated for VCC and temperature variations

Dual-In-Line Package Inputs Outputs
CLEAR A B Q Q
L X X L H
X H X L H
X X L L H
H L u É ß
H v H É ß
* u L H É ß
L e Low Logic Level
X e Can Be Either Low or High
u e Positive Going Transition
v e Negative Going Transition
É e A Positive Pulse
ß e A Negative Pulse
*This mode of triggering requires first the B input be set from a low to high
level while the CLEAR input is maintained at logic low level. Then with the B
input at logic high level, the CLEAR input whose positive transition from low
to high will trigger an output pulse.
TL/F/6409 – 1
TL/F/6409 – 2

Input Voltage 7V

DM74LS221
Min Nom Max
VT a Positive-Going Input Threshold Voltage
1 2 V
at the A Input (VCC e Min)
VTb Negative-Going Input Threshold Voltage
0.8 1 V
at the A Input (VCC e Min)
VT a Positive-Going Input Threshold Voltage
1 2 V
at the B Input (VCC e Min)
VTb Negative-Going Input Threshold Voltage
0.8 0.9 V
at the B Input (VCC e Min)
tW Pulse Width Data 40
ns
(Note 1)
Clear 40
tREL Clear Release Time (Note 1) 15 ns
dV Rate of Rise or Fall of V
1
dt Schmitt Input (B) (Note 1) s
dV Rate of Rise or Fall of V
1
dt Logic Input (A) (Note 1) ms
REXT External Timing Resistor (Note 1) 1.4 100 kX
CEXT External Timing Capacitance (Note 1) 0 1000 mF
DC Duty Cycle RT e 2 kX 50
%
(Note 1)
RT e REXT (Max) 60
Typ
(Note 1)
2.7 3.4 V
0.35 0.5
Voltage VIL e Max, VIH e Min V
VCC e Min, IOL e 4 mA 0.4
0.1 mA
Input Voltage
2
Electrical Characteristics
Typ
(Note 1)
IIL Low Level Input VCC e Max A1, A2 b 0.4
Current VI e 0.4V B b 0.8 mA
Clear b 0.8
IOS Short Circuit VCC e Max

b 20 b 100 mA
ICC Supply Current VCC e Max Quiescent 4.7 11
mA
Triggered 19 27
Switching Characteristics
at VCC e 5V and TA e 25§ C
From (Input)
To (Output)
tPLH Propagation Delay Time A1, A2 CEXT e 80 pF
70 ns
Low to High Level Output to Q REXT e 2 kX
CL e 15 pF
tPLH Propagation Delay Time B
RL e 2 kX 55 ns
tPHL Propagation Delay Time A1, A2
80 ns
tPHL Propagation Delay Time B
65 ns
tPLH Propagation Delay Time Clear to
65 ns
55 ns
tW(out) Output Pulse A1, A2 CEXT e 0
Width Using Zero to Q, Q REXT e 2 kX
20 70 ns
Timing Capacitance RL e 2 kX
CL e 15 pF
tW(out) Output Pulse A1, A2 CEXT e 100 pF
Width Using External to Q, Q REXT e 10 kX
600 750 ns
Timing Resistor RL e 2 kX
CL e 15 pF
CEXT e 1 mF
REXT e 10 kX
6 7.5 ms
RL e 2 kX
CL e 15 pF
CEXT e 80 pF
REXT e 2 kX
70 150 ns
RL e 2 kX
CL e 15 pF
3
Operating Rules
1. An external resistor (RX) and an external capacitor (CX) 5. For CX k 1000 pF see Figure 3 for TW vs CX family
are required for proper operation. The value of CX may curves with RX as a parameter:
vary from 0 to approximately 1000 mF. For small time
constants high-grade mica, glass, polypropylene, polycar-
bonate, or polystyrene material capacitor may be used.
For large time constants use tantalum or special alumi-
num capacitors. If timing capacitor has leakages ap-
proaching 100 nA or if stray capacitance from either ter-
minal to ground is greater than 50 pF the timing equations
may not represent the pulse width the device generates.
2. When an electrolytic capacitor is used for CX a switching
diode is often required for standard TTL one-shots to pre-
vent high inverse leakage current. This switching diode is
not needed for the ’LS221 one-shot and should not be
used.
TL/F/6409 – 4
Furthermore, if a polarized timing capacitor is used on the FIGURE 3
’LS221, the positive side of the capacitor should be con-
6. To obtain variable pulse widths by remote trimming, the
nected to the ‘‘CEXT’’ pin (Figure 1 ) .
following circuit is recommended:
TL/F/6409 – 5
Note: ‘‘Rremote’’ should be as close to the one-shot as possible.
FIGURE 4
TL/F/6409 – 8
7. Output pulse width versus VCC and temperatures: Figure
FIGURE 1 5 depicts the relationship between pulse width variation
3. For CX ll 1000 pF, the output pulse width (TW) is de- versus VCC. Figure 6 depicts pulse width variation versus
fined as follows: temperatures.
TW e KRX CX
where [RX is in kX]
[CX is in pF]
[TW is in ns]
K & Ln2 e 0.70
4. The multiplicative factor K is plotted as a function of CX
below for design considerations:
TL/F/6409 – 6
FIGURE 5
TL/F/6409 – 3
FIGURE 2
TL/F/6409 – 7
FIGURE 6
4
Operating Rules (Continued)
8. Duty cycle is defined as TW/T c 100 in percentage, if it 10. Although the ’LS221’s pin-out is identical to the ’LS123
goes above 50% the output pulse width will become it should be remembered that they are not functionally
shorter. If the duty cycle varies between low and high identical. The ’LS123 is a retriggerable device such that
values, this causes output pulse width to vary, or jitter (a the output is dependent upon the input transitions when
function of the REXT only). To reduce jitter , REXT should its output ‘‘Q’’ is at the ‘‘High’’ state. Furthermore, it is
be as large as possible, for example, with REXT e 100k recommended for the ’LS123 to externally ground the
jitter is not appreciable until the duty cycle approaches CEXT pin for improved system performance. However,
90%. this pin on the ’LS221 is not an internal connection to
9. Under any operating condition CX and RX must be kept the device ground. Hence, if substitution of an ’LS221
as close to the one-shot device pins as possible to mini- onto an ’LS123 design layout where the CEXT pin is
mize stray capacitance, to reduce noise pick-up, and to wired to the ground, the device will not function.
reduce I-R and Ldi/dt voltage developed along their con- 11. VCC and ground wiring should conform to good high-
necting paths. If the lead length from CX to pins (6) and frequency standards and practices so that switching
(7) or pins (14) and (15) is greater than 3 cm, for exam- transients on the VCC and ground return leads do not
ple, the output pulse width might be quite different from cause interaction between one-shots. A 0.01 mF to 0.10
values predicted from the appropriate equations. A non- mF bypass capacitor (disk ceramic or monolithic type)
inductive and low capacitive path is necessary to ensure from VCC to ground is necessary on each device. Fur-
complete discharge of CX in each cycle of its operation thermore, the bypass capacitor should be located as
so that the output pulse width will be accurate. close to the VCC-pin as space permits.
For further detailed device characteristics and output performance,
please refer to the NSC one-shot application note AN-372.

5
DM74LS221 Dual Non-Retriggerable One-Shot with Clear and Complementary Outputs

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Octal TRI-STATE Buffers/Line Drivers/Line Receivers
DM54LS240/DM74LS240, DM54LS241/DM74LS241
April 1992
DM54LS240/DM74LS240,
DM54LS241/DM74LS241
Octal TRI-STATEÉ Buffers/Line Drivers/Line Receivers
Y Typical IOL (sink current)
General Description 54LS 12 mA
These buffers/line drivers are designed to improve both the 74LS 24 mA
performance and PC board density of TRI-STATE buffers/ Y Typical IOH (source current)
drivers employed as memory-address drivers, clock drivers,
54LS b 12 mA
and bus-oriented transmitters/receivers. Featuring 400 mV
74LS b 15 mA
of hysteresis at each low current PNP data line input, they Y Typical propagation delay times
provide improved noise rejection and high fanout outputs
Inverting 10.5 ns
and can be used to drive terminated lines down to 133X.
Noninverting 12 ns
Features Y Typical enable/disable time 18 ns
Y TRI-STATE outputs drive bus lines directly
Y Typical power dissipation (enabled)
Inverting 130 mW
Y PNP inputs reduce DC loading on bus lines
Noninverting 135 mW
Y Hysteresis at data inputs improves noise margins
Connection Diagrams
TL/F/6411 – 1
TL/F/6411 – 2
Order Number DM54LS240J, Order Number DM54LS241J,
DM54LS240W, DM54LS240E, DM54LS241W, DM54LS241E,
DM74LS240WM or DM74LS240N DM74LS241WM or DM74LS241N
M20B, N20A or W20A M20B, N20A or W20A
Function Tables
LS240 LS241
Inputs Output Inputs Outputs
G A Y G G 1A 2A 1Y 2Y
L L H X L L X L
L H L X L H X H
H X Z X H X X Z
H X X L L
H X X H H
L X X X Z
L e Low Logic Level
Z e High Impedance

Input Voltage 7V
DM54LS, 54LS b 55§ C to a 125§ C

DM54LS240, 241 DM74LS240, 241
IOH High Level Output Current b 12 b 15 mA
Typ
(Note 1)
HYS Hysteresis (VT a b VTb) VCC e Min
0.2 0.4 V
Data Inputs Only
VOH High Level Output Voltage VCC e Min, VIH e Min DM74
2.7
VIL e Max, IOH e b1 mA
VCC e Min, VIH e Min DM54/DM74
2.4 3.4 V
2
VIL e 0.5V, IOH e Max
VOL Low Level Output Voltage VCC e Min IOL e 12 mA DM74 0.4
VIL e Max
IOL e Max DM54 0.4 V
VIH e Min
DM74 0.5
IOZH Off-State Output Current, VCC e Max VO e 2.7V
20 mA
High Level Voltage Applied VIL e Max
VIH e Min
IOZL Off-State Output Current, VO e 0.4V b 20 mA
Low Level Voltage Applied
II Input Current at Maximum VCC e Max, VI e 7V (DM74)
0.1 mA
Input Voltage VI e 10V (DM54)
IOS Short Circuit Output Current VCC e Max (Note 2) b 40 b 225 mA
ICC Supply Current VCC e Max, Outputs High LS240, LS241 13 23
Outputs Open Outputs Low LS240 26 44
LS241 27 46 mA
Outputs Disabled LS240 29 50
LS241 32 54
2
DM54LS DM74LS
Symbol Parameter Conditions Units
Max Max
tPLH Propagation Delay Time CL e 45 pF LS240 18 14
ns
Low to High Level Output RL e 667X LS241 18 18
tPHL Propagation Delay Time CL e 45 pF LS240 18 18
ns
High to Low Level Output RL e 667X LS241 18 18
tPZL Output Enable Time to CL e 45 pF LS240 30 30
ns
Low Level RL e 667X LS241 30 30
tPZH Output Enable Time to CL e 45 pF LS240 23 23
ns
High Level RL e 667X LS241 23 23
tPLZ Output Disable Time CL e 5 pF LS240 25 25
ns
from Low Level RL e 667X LS241 25 25
tPHZ Output Disable Time CL e 5 pF LS240 18 18
ns
from High Level RL e 667X LS241 18 18
tPLH Propagation Delay Time CL e 150 pF LS240 18
ns
Low to High Level Output RL e 667X
LS241 21
tPHL Propagation Delay Time CL e 150 pF LS240 22
ns
High to Low Level Output RL e 667X
LS241 22
tPZL Output Enable Time to CL e 150 pF LS240 33
ns
Low Level RL e 667X
LS241 33
tPZH Output Enable Time to CL e 150 pF LS240 26
ns
High Level RL e 667X
LS241 26
Note: 54LS Output load is CL e 50 pF for tPLH, tPHL, tPZL and tPZH.
3

Order Number DM74LS240WM or DM74LS241WM

5
Octal TRI-STATE Buffers/Line Drivers/Line Receivers

Order Number DM54LS240W or DM54LS241W
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54LS244/DM74LS244 Octal TRI-STATE Buffers/Line Drivers/Line Receivers
August 1989
54LS244/DM74LS244 Octal TRI-STATEÉ

Buffers/Line Drivers/Line Receivers
Y Typical IOL (sink current)
General Description 54LS 12 mA
These buffers/line drivers are designed to improve both the 74LS 24 mA
performance and PC board density of TRI-STATE buffers/ Y Typical IOH (source current)
drivers employed as memory-address drivers, clock drivers,
54LS b 12 mA
and bus-oriented transmitters/receivers. Featuring 400 mV
74LS b 15 mA
of hysteresis at each low current PNP data line input, they Y Typical propagation delay times
provide improved noise rejection and high fanout outputs
Inverting 10.5 ns
and can be used to drive terminated lines down to 133X.
Noninverting 12 ns
Y Typical enable/disable time 18 ns
Features Y Typical power dissipation (enabled)
Inverting 130 mW
Y PNP inputs reduce DC loading on bus lines Noninverting 135 mW
Y Hysteresis at data inputs improves noise margins
Connection Diagram
TL/F/8442 – 1
See NS Package Number E20A, J20A, M20B, N20A or W20A
Function Table
Inputs Output
G A Y
L L L
L H H
H X Z
L e Low Logic Level
Z e High Impedance

Input Voltage 7V table are not guaranteed at the absolute maximum ratings.
Operating Free Air Temperature Range The ‘‘Recommended Operating Conditions’’ table will define
54LS b 55§ C to a 125§ C the conditions for actual device operation.

54LS244 DM74LS244
Typ
(Note 1)
HYS Hysteresis (VT a b VTb) VCC e Min
0.2 0.4 V
Data Inputs Only
2.7
VCC e Min, VIH e Min 54LS/DM74
2.4 3.4 V
VCC e Min, VIH e Min 54LS/DM74
2
VOL Low Level Output Voltage VCC e Min IOL e 12 mA 54LS/DM74 0.4
VIL e Max V
IOL e Max DM74 0.5
VIH e Min
20 mA
VIH e Min
IOZL Off-State Output Current, VO e 0.4V
b 20 mA
II Input Current at Maximum VCC e Max VI e 7V (DM74)
0.1 mA
Input Voltage VI e 10V (54LS)
IIH High Level Input Current VCC e Max VI e 2.7V 20 mA
IIL Low Level Input Current VCC e Max VI e 0.4V b 0.5 b 200 mA
54LS b 50
IOS Short Circuit Output Current VCC e Max (Note 2) b 225 mA
DM74 b 40
ICC Supply Current VCC e Max, Outputs High 13 23

Outputs Open Outputs Low 27 46 mA
Outputs Disabled 32 54
2
Switching Characteristics at VCC e 5V, TA e 25§ C (see Section 1 for Test Waveforms and Output Load)
Symbol Parameter Conditions 54LS Max DM74LS Max Units
tPLH Propagation Delay Time CL e 45 pF
18 18 ns
tPHL Propagation Delay Time CL e 45 pF
18 18 ns
tPZL Output Enable Time to CL e 45 pF
30 30 ns
Low Level RL e 667X
tPZH Output Enable Time to CL e 45 pF
23 23 ns
tPLZ Output Disable Time CL e 5 pF
25 25 ns
from Low Level RL e 667X
tPHZ Output Disable Time CL e 5 pF
18 18 ns
from High Level RL e 667X
tPLH Propagation Delay Time CL e 150 pF
21 ns
tPHL Propagation Delay Time CL e 150 pF
22 ns
tPZL Output Enable Time to CL e 150 pF
33 ns
Low Level RL e 667X
tPZH Output Enable Time to CL e 150 pF
26 ns
Note: 54LS Output Load is CL e 50 pF for tPLH, tPHL, tPZL and tPZH.
3


Order Number 54LS244DMQB
4


5
54LS244/DM74LS244 Octal TRI-STATE Buffers/Line Drivers/Line Receivers

Order Number 54LS244FMQB
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54LS245/DM54LS245/DM74LS245 TRI-STATE Octal Bus Transceiver
June 1989
54LS245/DM54LS245/DM74LS245
TRI-STATEÉ Octal Bus Transceiver
General Description
These octal bus transceivers are designed for asynchro- Y PNP inputs reduce DC loading on bus lines
nous two-way communication between data buses. The Y Hysteresis at bus inputs improve noise margins
control function implementation minimizes external timing Y Typical propagation delay times, port-to-port 8 ns
requirements. Y Typical enable/disable times 17 ns
The device allows data transmission from the A bus to the B Y IOL (sink current)
bus or from the B bus to the A bus depending upon the logic 54LS 12 mA
level at the direction control (DIR) input. The enable input 74LS 24 mA
(G) can be used to disable the device so that the buses are Y IOH (source current)
effectively isolated. 54LS b 12 mA
74LS b 15 mA
Features Y Alternate Military/Aerospace device (54LS245) is avail-
Y Bi-Directional bus transceiver in a high-density 20-pin able. Contact a National Semiconductor Sales Office/
package Distributor for specifications.
Connection Diagram
TL/F/6413 – 1
DM54LS245J, DM54LS245W, DM74LS245WM or DM74LS245N
See NS Package Number E20A, J20A, M20B, N20A or W20A
Function Table
Direction
Enable Operation
Control
G
DIR
L L B data to A bus
L H A data to B bus
H X Isolation
H e High Level, L e Low Level, X e Irrelevant

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Note: The ‘‘Absolute Maximum Ratings’’ are those values
Office/Distributors for availability and specifications. beyond which the safety of the device cannot be guaran-
teed. The device should not be operated at these limits. The
Supply Voltage 7V
parametric values defined in the ‘‘Electrical Characteristics’’
Input Voltage
DIR or G 7V
A or B 5.5V

DM54LS245 DM74LS245
Typ
(Note 1)
HYS Hysteresis (VT a b VTb) VCC e Min 0.2 0.4 V
2.7
VCC e Min, VIL e Min DM54/DM74
2.4 3.4 V
2
VOL Low Level Output Voltage VCC e Min IOL e 12 mA DM74 0.4
VIL e Max
IOL e Max DM54 0.4 V
VIH e Min
DM74 0.5
20 mA
IOZL Off-State Output Current, VIH e Min
VO e 0.4V
b 200 mA
II Input Current at Maximum VCC e Max A or B VI e 5.5V 0.1
mA
Input Voltage DIR or G VI e 7V 0.1
IOS Short Circuit Output Current VCC e Max (Note 2) b 40 b 225 mA
ICC Supply Current Outputs High VCC e Max 48 70
Outputs Low 62 90 mA
Outputs at Hi-Z 64 95
Note 2: Not more than one output should be shorted at a time, not to exceed one second duration
2
Switching Characteristics VCC e 5V, TA e 25§ C (See Section 1 for Test Waveforms and Output Load)
DM54/74
Symbol Parameter Conditions LS245 Units
Min Max
tPLH Propagation Delay Time, Low-to-High-Level Output 12 ns
tPHL Propagation Delay Time, High-to-Low-Level Output CL e 45 pF 12 ns
tPZL Output Enable Time to Low Level RL e 667X 40 ns
tPZH Output Enable Time to High Level 40 ns
tPLZ Output Disable Time from Low Level CL e 5 pF 25 ns
tPHZ Output Disable Time from High Level RL e 667X 25 ns
tPLH Propagation Delay Time, Low-to-High-Level Output 16 ns
tPHL Propagation Delay Time, High-to-Low-Level Output CL e 150 pF 17 ns
tPZL Output Enable Time to Low Level RL e 667X
45 ns
tPZH Output Enable Time to High Level 45 ns
3


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54LS245/DM54LS245/DM74LS245 TRI-STATE Octal Bus Transceiver

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DM54LS259/DM74LS259 8-Bit Addressable Latches
May 1992

These 8-bit addressable latches are designed for general Y 8-Bit parallel-out storage register performs serial-to-par-
purpose storage applications in digital systems. Specific allel conversion with storage
uses include working registers, serial-holding registers, and Y Asynchronous parallel clear
active-high decoders or demultiplexers. They are multifunc- Y Active high decoder
tional devices capable of storing single-line data in eight Y Enable/disable input simplifies expansion
addressable latches, and being a 1-of-8 decoder or demulti- Y Direct replacement for Fairchild 9334
plexer with active-high outputs. Y Expandable for N-bit applications
Four distinct modes of operation are selectable by control- Y Four distinct functional modes
ling the clear and enable inputs as enumerated in the func- Y Typical propagation delay times:
tion table. In the addressable-latch mode, data at the data-
Enable-to-output 18 ns
in terminal is written into the addressed latch. The ad-
Data-to-output 16 ns
dressed latch will follow the data input with all unaddressed
Address-to-output 21 ns
latches remaining in their previous states. In the memory
Clear-to-output 17 ns
mode, all latches remain in their previous states and are
unaffected by the data or address inputs. To eliminate the
Y Fan-out
possibility of entering erroneous data in the latches, the en- IOL (sink current)
able should be held high (inactive) while the address lines 54LS259 4 mA
are changing. In the 1-of-8 decoding or demultiplexing 74LS259 8 mA
mode, the addressed output will follow the level of the D IOH (source current) b0.4 mA
input with all other outputs low. In the clear mode, all out-
Y Typical ICC 22 mA
puts are low and unaffected by the address and data inputs.
Dual-In-Line Package Inputs Output of Each

Addressed Other Function
Clear E Latch Output
H L D Qi0 Addressable Latch

H H Qi0 Qi0 Memory
L L D L 8-Line Demultiplexer
L H L L Clear
Latch Selection Table

Select Inputs
Latch
C B A Addressed
L L L 0
L L H 1
L H L 2
L H H 3
H L L 4
TL/F/6418 – 1 H L H 5
Order Number DM54LS259E, DM54LS259J, H H L 6
DM54LS259W, DM74LS259M, H H H 7
H e High Level, L e Low Level
See NS Package Number E20A, J16A,
D e the Level of the Data Input
M16A, M16B, N16E or W16A
Qi0 e the Level of Qi (i e 0, 1, . . . 7, as Appropriate) before the Indicated
Steady-State Input Conditions Were Established.

Input Voltage 7V
DM54 b 55§ C to a 125§ C

DM54LS259 DM74LS259
tW Pulse Width Enable 17 15
ns
tSU Setup Time Data 20u 15u
ns
(Notes 1, 2, 3 & 7) Select 15v 15v
tH Hold Time Data 5u 2.5u
ns
(Notes 1, 2 & 7) Select 0u 2.5u
Typ
(Note 4)
VOH High Level Output VCC e Min, IOH e Max DM54 2.5
V
VOL Low Level Output VCC e Min, IOL e Max DM54 0.4
II Input Current @ Max VCC e Max, VI e 7V DM74
0.1 mA
Input Voltage VI e 10V DM54
IIH High Level Input VCC e Max, VI e 2.7V
20 mA
Current
IIL Low Level Input VCC e Max, VI e 0.4V b 0.4
Current mA
Enable VCC e Max, VI e 0.4V b 0.8
mA
Note 1: The symbols ( v, u) indicate the edge of the clock pulse used for reference: u for rising edge, v for falling edge.
Note 2: Setup and hold times are with reference to the enable input.
Note 3: The select-to-enable setup time is the time before the High-to-Low enable transition that the select must be stable so that the correct latch is selected and
the others not affected.
Note 6: ICC is measured with all inputs at 4.5V, and all outputs open.
2
DM54LS DM74LS
From (Input) CL e 50 pF
Symbol Parameter CL e 15 pF Units
To (Output) RL e 2 kX
Min Max Min Max
27 38 ns
24 32 ns
tPLH Propagation Delay Time Data to
30 35 ns
tPHL Propagation Delay Time Data to
20 30 ns
30 41 ns
29 38 ns
18 36 ns

3

16-Lead Molded Package Small Outline (SO)

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DM54LS260/DM74LS260 Dual 5-Input NOR Gate
April 1992
DM54LS260/DM74LS260
Dual 5-Input NOR Gate
General Description
This device contains two individual five input gates, each of
which perform the logic NOR function.
Connection Diagram
TL/F/9824 – 1
Order Number DM54LS260J, DM54LS260W,
DN54LS260E, DM74LS260M or DM74LS260N
Truth Table
AaBaCaDaEeY
Inputs Outputs
A B C D E Y
L L L L L H
X X X X H L
X X X H X L
X X H X X L
X H X X X L
H X X X X L

Input Voltage 7V table are not guaranteed at the absolute maximum ratings.
DM54LS b 55§ C to a 125§ C

DM54LS260 DM74LS260
Typ
(Note 1)
VI Input Clamp Voltage VCC e Min, II e b 18 mA b 1.5 V
VOH High Level Output VCC e Min, IOH e Max DM54 2.5
V
Voltage VIL e Max
DM74 2.7
VOL Low Level Output VCC e Min, IOL e Max DM54 0.4
Voltage VIH e Min
DM74 0.5 V
IOL e 4 mA, VCC e Min DM74 0.4
0.1 mA
Input Voltage VI e 10V DM54
IIL Low Level Input Current VCC e Max, VI e 0.4V DM54 b 0.40
mA
DM74 b 0.36

mA
DM74 b 20 b 100
ICCH Supply Current with Outputs High VCC e Max, VIN e GND 4.0 mA
ICCL Supply Current with Outputs Low VCC e Max, VIN e Open 5.5 mA
Switching Characteristics VCC e a 5V, TA e a 25§ C

RL e 2 kX, CL e 15 pF
Min Max
10 ns
12 ns
2
3


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DM54LS273/DM74LS273 8-Bit Register with Clear
April 1992
DM54LS273/DM74LS273
8-Bit Register with Clear
The ’LS273 is a high speed 8-bit register, consisting of eight Y Edge-triggered
D-type flip-flops with a common Clock and an asynchronous Y 8-bit high speed register
active LOW Master Reset. This device is supplied in a 20- Y Parallel in and out
pin package featuring 0.3 inch row spacing. Y Common clock and master reset
Connection Diagram
TL/F/9825 – 1
Order Number DM54LS273E, DM54LS273J,
DM54LS273W, DM74LS273M or DM74LS273N
See NS Package Number E20A, J20A, M20B,
N20A or W20A
Pin Names Description

CP Clock Pulse Input (Active Rising Edge)
D0–D7 Data Inputs
MR Asynchronous Master Reset Input
(Active LOW)
Q0–Q7 Flip-Flop Outputs

Input Voltage 7V
DM54LS b 55§ C to a 125§ C

DM54LS273 DM74LS273
ts(H) Setup Time HIGH or LOW 15 15
ns
ts(L) Dn to CP 15 15
th(H) Hold Time HIGH or LOW 5 5
ns
th(L) Dn to CP 5 5
tw(H) CP Pulse Width HIGH or LOW 20 20
ns
tw(L) 20 20
tw(L) MR Pulse Width LOW 20 20 ns
trec Recovery Time
15 15 ns
MR to CP
Electrical Characteristics
Over recommended operating free air temperature range (unless otherwise noted)
Typ
(Note 1)
VOH High Level Output VCC e Min, IOH e Max, DM54 2.5
V
Voltage VIL e Max
DM74 2.7 3.4
VOL Low Level Output VCC e Min, IOL e Max, DM54 0.4
Voltage VIH e Min
DM74 0.35 0.5 V
0.1 mA
Input Voltage VI e 10V (DM54)
mA
ICC Supply Current VCC e Max 27 mA

2
Switching Characteristics VCC e a 5.0V, TA e a 25§ C
CL e 15 pF
DM74LS
Symbol Parameter DM54LS Units
RL e 2 kX
Min Max Min Max
fmax Maximum Clock Frequency 30 30 MHz
tPLH Propagation Delay 24 24
ns
tPHL CP to Qn 24 24
tPLH Propagation Delay
27 27 ns
MR to Qn
Functional Description Truth Table

The ’LS273 is an 8-bit parallel register with a common Clock
Inputs Outputs
and common Master Reset. When the MR input is LOW, the
Q outputs are LOW, independent of the other inputs. Infor- MR CP Dn Qn
mation meeting the setup and hold time requirements of the L X X L
D inputs is transferred to the Q outputs on the LOW-to- H L H H
HIGH transition of the clock input.
H L L L
H e HIGH Voltage Level
L e LOW Voltage Level
X e Immaterial
Logic Symbol
TL/F/9825 – 2
VCC e Pin 20
GND e Pin 10
Logic Diagram
TL/F/9825 – 3
3


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54LS279/DM54LS279/DM74LS279 Quad S-R Latches
May 1989
54LS279/DM54LS279/DM74LS279
Quad S-R Latches
General Description
The ’LS279 consists of four individual and independent Set- to be indeterminate. Both inputs are voltage level triggered
Reset Latches with active low inputs. Two of the four latch- and are not affected by transition time of the input data.
es have an additonal S input ANDed with the primary S
input. A low on any S input while the R input is high will be Features
stored in the latch and appear on the corresponding Q out- Y Alternate military/aerospace device (54LS279) is avail-
put as a high. A low on the R input while the S input is high able. Contact a National Semiconductor Sales Office/
will clear the Q output to a low. Simultaneous transistion of Distributor for specifications.
the R and S inputs from low to high will cause the Q output
Connection Diagram
TL/F/6420 – 1
DM54LS279J, DM74LS279M or DM74LS279N
Function Table
Inputs Output
S(1) R Q
L L H*
L H H
H L L
H H Q0
H e High Level
L e Low Level
Q0 e The Level of Q before the indicated input conditions were established.
*This output level is pseudo stable; that is, it may not persist when the S and R
inputs return to their inactive (high) level.
Note 1: For latches with double S inputs:
H e both S inputs high
L e one or both S inputs low

Input Voltage 7V

DM54LS279 DM74LS279
Typ
(Note 1)
V
Voltage
VIL e Max, VIH e Min DM74 2.7 3.5
DM74 0.35 0.5 V
0.1 mA
Input Voltage
IIH High Level Input VCC e Max, VI e 2.7V
20 mA
Current
IIL Low Level Input VCC e Max, VI e 0.4V
b 0.4 mA
Current
mA

Note 3: ICC is measured with all R inputs grounded, all S inputs at 4.5V and all outputs open.
2
RL e 2 kX
From (Input)
Min Max Min Max
tPLH Propagation Delay Time S to
22 25 ns
tPHL Propagation Delay Time S to
15 23 ns
tPHL Propagation Delay Time R to
27 33 ns
3


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54LS283/DM54LS283/DM74LS283 4-Bit Binary Adders with Fast Carry
June 1989
54LS283/DM54LS283/DM74LS283
4-Bit Binary Adders with Fast Carry
These full adders perform the addition of two 4-bit binary Y Full-carry look-ahead across the four bits
numbers. The sum (R) outputs are provided for each bit and Y Systems achieve partial look-ahead performance with
the resultant carry (C4) is obtained from the fourth bit. the economy of ripple carry
These adders feature full internal look ahead across all four Y Typical add times
bits. This provides the system designer with partial look- Two 8-bit words 25 ns
ahead performance at the economy and reduced package Two 16-bit words 45 ns
count of a ripple-carry implementation. Y Typical power dissipation per 4-bit adder 95 mW
The adder logic, including the carry, is implemented in its Y Alternate Military/Aerospace device (54LS283) is avail-
true form meaning that the end-around carry can be accom- able. Contact a National Semiconductor Sales Office/
plished without the need for logic or level inversion. Distributor for specifications.
Connection Diagram
TL/F/6421 – 1

Input Voltage 7V

DM54LS283 DM74LS283
Typ
(Note 1)
V
DM74 2.7 3.4
DM74 0.35 0.5 V
II Input Current @ Max VCC e Max A, B 0.2
mA
C0 0.1
IIH High Level Input VCC e Max A, B 40
mA
Current VI e 2.7V
C0 20
IIL Low Level Input VCC e Max A, B b 0.8
mA
Current VI e 0.4V
C0 b 0.4

mA
DM74 b 20 b 100

Note 3: ICC1 is measured with all outputs open, all B inputs low and all other inputs at 4.5V, or all inputs at 4.5V.
Note 4: ICC2 is measured with all outputs open and all inputs grounded.
2
RL e 2 kX
From (Input)
To (Output)
Min Max Min Max
24 28 ns
Low to High Level Output R1, R2
24 30 ns
High to Low Level Output R1, R2
24 28 ns
24 30 ns
24 28 ns
24 30 ns
tPLH Propagation Delay Time Ai or Bi
24 28 ns
Low to High Level Output to Ri
tPHL Propagation Delay Time Ai or Bi
24 30 ns
High to Low Level Output to Ri
17 24 ns
Low to High Level Output C4
17 25 ns
High to Low Level Output C4
tPLH Propagation Delay Time Ai or Bi
17 24 ns
Low to High Level Output to C4
tPHL Propagation Delay Time Ai or Bi
17 26 ns
High to Low Level Output to C4
Function Table
TL/F/6421 – 3
H e High Level, L e Low Level
Note: Input conditions at A1, B1, A2, B2, and C0 are used to determine outputs R1 and R2 and the value of the internal carry C2. The values at C2, A3, B3, A4, and
B4 are then used to determine outputs R3, R4, and C4.
3
Logic Diagram
LS283
TL/F/6421 – 2
4
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TRI-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops
May 1992
DM54LS373/DM74LS373,
DM54LS374/DM74LS374
TRI-STATEÉ Octal D-Type Transparent
Latches and Edge-Triggered Flip-Flops
These 8-bit registers feature totem-pole TRI-STATE outputs Y Choice of 8 latches or 8 D-type flip-flops in a single
designed specifically for driving highly-capacitive or relative- package
ly low-impedance loads. The high-impedance state and in- Y TRI-STATE bus-driving outputs
creased high-logic level drive provide these registers with Y Full parallel-access for loading
the capability of being connected directly to and driving the Y Buffered control inputs
bus lines in a bus-organized system without need for inter- Y P-N-P inputs reduce D-C loading on data lines
face or pull-up components. They are particularly attractive
for implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers. (Continued)
Connection Diagrams
Dual-In-Line Packages
’LS373
Order Number
DM54LS373J,
DM54LS373W,
DM74LS373N or
DM74LS373WM
See NS Package Number
J20A, M20B, N20A or
W20A
TL/F/6431 – 1
’LS374
Order Number
DM54LS374J,
DM54LS374W,
DM74LS374WM or
DM74LS374N
See NS Package Number
J20A, M20B, N20A or
W20A
TL/F/6431 – 2
TRI-STATEÉ is a registered trademark of National Semiconductor Corp.

General Description (Continued)
The eight latches of the DM54/74LS373 are transparent D- A buffered output control input can be used to place the
type latches meaning that while the enable (G) is high the Q eight outputs in either a normal logic state (high or low logic
outputs will follow the data (D) inputs. When the enable is levels) or a high-impedance state. In the high-impedance
taken low the output will be latched at the level of the data state the outputs neither load nor drive the bus lines signifi-
that was set up. cantly.
The eight flip-flops of the DM54/74LS374 are edge-trig- The output control does not affect the internal operation of
gered D-type flip flops. On the positive transition of the the latches or flip-flops. That is, the old data can be retained
clock, the Q outputs will be set to the logic states that were or new data can be entered even while the outputs are off.
set up at the D inputs.
Function Tables
DM54/74LS373 DM54/74LS374
Output Enable Output

D Output Clock D Output
Control G Control
L H H H L u H H
L H L L L u L L
L L X Q0 L L X Q0
H X X Z H X X Z
H e High Level (Steady State), L e Low Level (Steady State), X e Don’t Care
u e Transition from low-to-high level, Z e High Impedance State
Q0 e The level of the output before steady-state input conditions were established.
Logic Diagrams
DM54/74LS373 DM54/74LS374
Transparent Latches Positive-Edge-Triggered Flip-Flops
TL/F/6431–3 TL/F/6431 – 4
2
Absolute Maximum Ratings (See Note)
Input Voltage 7V
DM54LS b 55§ C to a 125§ C

DM54LS373 DM74LS373
VIH High Level Input Votage 2 2 V
tW Pulse Width Enable High 15 15
ns
(Note 2) Enable Low 15 15
tSU Data Setup Time (Notes 1 & 2) 5v 5v ns
tH Data Hold Time (Notes 1 & 2) 20v 20v ns
Note 1: The symbol ( v) indicates the falling edge of the clock pulse is used for reference.

Typ
(Note 1)
VOH High Level Output Voltage VCC e Min DM54
2.4 3.4
IOH e Max
V
VIL e Max
DM74
VIH e Min 2.4 3.1
VOL Low Level Output Voltage VCC e Min DM54

0.25 0.4
IOL e Max
VIL e Max
DM74
VIH e Min 0.35 0.5 V
IOL e 12 mA DM74
0.4
VCC e Min
0.1 mA
Input Voltage
IOZH Off-State Output Current VCC e Max, VO e 2.7V
with High Level Output VIH e Min, VIL e Max
20 mA
Voltage Applied
IOZL Off-State Output Current VCC e Max, VO e 0.4V
with Low Level Output VIH e Min, VIL e Max b 20 mA
Voltage Applied
mA
ICC Supply Current VCC e Max, OC e 4.5V,
24 40 mA
Dn, Enable e GND
3
‘LS373 Switching Characteristics at VCC e 5V and TA e 25§ C
(See Section 1 for Test Waveforms and Output Load)
From RL e 667X
Symbol Parameter (Input) CL e 45 pF CL e 150 pF Units
To
(Output) Min Max Min Max
tPLH Propagation Delay Data

Time Low to High to 18 26 ns
Level Output Q
tPHL Propagation Delay Data
Time High to Low to 18 27 ns
Level Output Q
tPLH Propagation Delay Enable
Time Low to High to 30 38 ns
Level Output Q
tPHL Propagation Delay Enable
Time High to Low to 30 36 ns
Level Output Q
tPZH Output Enable Output
Time to High Control 28 36 ns
Level Output to Any Q
tPZL Output Enable Output
Time to Low Control 36 50 ns
Level Output to Any Q
tPHZ Output Disable Output
Time from High Control 20 ns
Level Output (Note 3) to Any Q
tPLZ Output Disable Output
Time from Low Control 25 ns
Level Output (Note 3) to Any Q
Note 3: CL e 5 pF.

DM54LS374 DM74LS374
ns
(Note 4) Clock Low 15 15
tSU Data Setup Time (Notes 1 & 4) 20u 20u ns
tH Data Hold Time (Notes 1 & 4) 1u 1u ns
u
Note 1: The symbol ( ) indicates the rising edge of the clock pulse is used for reference.
4
Typ
(Note 1)
VOH High Level Output Voltage VCC e Min DM54 2.4 3.4
IOH e Max DM74 2.4 3.1
VIL e Max V
VIH e Min
VOL Low Level Output Voltage VCC e Min DM54 0.25 0.4
IOL e Max DM74 0.35 0.5
VIL e Max
VIH e Min V
IOL e 12 mA DM74
0.25 0.4
VCC e Min
0.1 mA
Input Voltage
IOZH Off-State Output VCC e Max, VO e 2.7V
Current with High VIH e Min, VIL e Max
20 mA
Level Output
Voltage Applied
IOZL Off-State Output VCC e Max, VO e 0.4V
Current with Low VIH e Min, VIL e Max b 20 mA
Level Output
Voltage Applied
mA
DM74 b 50 b 225
ICC Supply Current VCC e Max, Dn e GND, OC e 4.5V 27 45 mA
’LS374 Switching Characteristics at VCC e 5V and TA e 25§ C

(See Section 1 for Test Waveforms and Output Load)
RL e 667X
Min Max Min Max
28 32 ns
28 38 ns
tPZH Output Enable Time
28 44 ns
to High Level Output
tPZL Output Enable Time
28 44 ns
to Low Level Output
tPHZ Output Disable Time
20 ns
from High Level Output (Note 3)
tPLZ Output Disable Time
25 ns
from Low Level Output (Note 3)
Note 3: CL e 5 pF.
5

Order Number DM54LS373J or DM54LS374J
6

Order Number DM74LS373WM or DM74LS374WM

Order Number DM74LS373N and DM74LS374N
7
TRI-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops

Order Number DM54LS373W or DM54LS374W
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IMPORTANT NOTICE


IMPORTANT NOTICE


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Datasheet IC 74LS Series-National-Semiconductor

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54LS00/DM54LS00/DM74LS00 Quad 2-Input NAND Gates

C1995 National Semiconductor Corporation TL/F/6439 RRD-B30M105/Printed in U. S. A.

Recommended Operating Conditions

ICCH Supply Current with VCC e Max

Ceramic Leadless Chip Carrier Package (E)

14-Lead Ceramic Dual-In-Line Package (J)

14-Lead Small Outline Molded Package (M)

14-Lead Molded Dual-In-Line Package (N)

14-Lead Ceramic Flat Package (W)

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Copyright  1996, Texas Instruments Incorporated

C1995 National Semiconductor Corporation TL/F/6441 RRD-B30M105/Printed in U. S. A.

Recommended Operating Conditions

ICCH Supply Current with VCC e Max

Ceramic Leadless Chip Carrier Package (E)

14-Lead Ceramic Dual-In-Line Package (J)

14-Lead Small Outline Molded Package (M)

14-Lead Molded Dual-In-Line Package (N)

14-Lead Ceramic Flat Package (W)

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C1995 National Semiconductor Corporation TL/F/6344 RRD-B30M105/Printed in U. S. A.

Recommended Operating Conditions

Ceramic Leadless Chip Carrier Package (E)

14-Lead Ceramic Dual-In-Line Package (J)

14-Lead Small Outline Molded Package (M)

14-Lead Molded Dual-In-Line Package (N)

14-Lead Ceramic Flat Package (W)

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D Dependable Texas Instruments Quality and SN5404 . . . J PACKAGE

SN54LS04, SN54S04 . . . FK PACKAGE

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic diagram (positive logic)

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schematics (each gate)

Resistor values shown are nominal.

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

recommended operating conditions

electrical characteristics over recommended operating free-air temperature range (unless

switching characteristics, VCC = 5 V, TA = 25°C (see Figure 1)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

recommended operating conditions

electrical characteristics over recommended operating free-air temperature range (unless

switching characteristics, VCC = 5 V, TA = 25°C (see Figure 2)

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

recommended operating conditions

electrical characteristics over recommended operating free-air temperature range (unless

switching characteristics, VCC = 5 V, TA = 25°C (see Figure 1)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7

PARAMETER MEASUREMENT INFORMATION

LOAD CIRCUIT LOAD CIRCUIT LOAD CIRCUIT

NOTES: A. CL includes probe and jig capacitance.

Figure 1. Load Circuits and Voltage Waveforms

8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

LOAD CIRCUIT LOAD CIRCUIT LOAD CIRCUIT

Figure 2. Load Circuits and Voltage Waveforms

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Copyright  2002, Texas Instruments Incorporated

54LS05/DM54LS05/DM74LS05 Hex Inverters