Built-In Logic Block Observer - Organization

z Architecture
z Operation
z Test Session Scheduling
z BIST Controller
z Concurrent BILBO
z Benefits & Limitations

C. Stroud 10/06 BILBO 1

 Built-In Logic Block Observer (BILBO)
z by Koenemann & Mucha, 1979 BILBO
™ 1st BIST approach proposed
Q
z BIST logic added to all FFs
™ plus logic for characteristic polynomial B1 Comb
B2 Logic
z BILBO control leads B1 & B2 facilitate
™ system mode - normal operation Z
™ reset mode - initialization
BILBO
™ LFSR mode - TPG
™ MISR mode – ORA
¾ Scan mode needed Zi Comb BILBO FF
‰ BIST results retrieval B1 Logic
D Q Qi
‰ Initialization of TPGs B2 added
9 to non-0 values Qi-1 to FF CK Q Qi
z Test-per-clock BIST
™ Exhaustive testing of combinational logic
C. Stroud 10/06 BILBO 2
 BILBO Evolution
z Original implementation
™ Required mode pin B1
to control TPG vs.
MISR mode during
testing
¾ Forcing logic 0s on Z
inputs causes MISR to
function as LSFR for
TPG
™ Used external FB LFSR
z Later implementation added
control signal B3
™ To control TPG vs.
MISR modes
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 BILBO Evolution
z Modified BILBO was
introduced for practical
ASIC implementations
™ NAND gates used
for CMOS “friendly”
standard cells
™ Only two control
signals needed
™ Minimizes area
overhead
™ Most frequently used
BILBO approach
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 BILBO Operation
Scan In
z At least 2 test sessions required
™ Test session 1: Test
LFSR
Test
¾ Ckts A & C are CUTs Session Session
¾ BILBO 1 = MISR 1 CUT A 2
¾ BILBO 2 = LFSR
™ Test session 2: MISR BILBO 1 LFSR
¾ Ckt B is CUT
¾ BILBO 1 = LFSR CUT B
¾ BILBO 2 = MISR
z Need scan mode to LFSR BILBO 2 MISR
™ Retrieve BIST results from MISRs
™ Initialize LFSRs to non-0 values CUT C
z Works well for pipelined architectures
MISR
z Otherwise, problems with feedback Scan Out
™ Requires test session scheduling
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 Test Session Scheduling
z Practical application
of BILBO typically
requires scheduling
of multiple test
sessions based on
interconnection of
registers and
combinational logic

C. Stroud 10/06 BILBO 6

 Register Self-Adjacency
z Common in FSMs
™ Next state is function of current state
z BILBO must simultaneously function as TPG and ORA
™ Signatures act as test vectors
™ Loose pseudo-exhaustive nature of test vectors
z One solution – the Concurrent BILBO (CBILBO)
™ Doubles #FFs to create independent TPG and ORA
Register R1 R1=TPG(LFSR) R1=TPG(LFSR)

Combinational Combinational Combinational

Logic Logic Logic

Register R2 R2=ORA(MISR) R2=ORA R2=TPG

system operation BILBO operation CBILBO operation

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 Concurrent BILBO
z Adds additional register to allow TPG and MISR to operate
independently in cases of register self-adjacency

C. Stroud 10/06 BILBO 8

 BILBO Summary
z Not practical but historically significant since it got BIST started
™ Led to pseudo-exhaustive self-test (PEST)
™ Led to Circular BIST

C. Stroud 10/06 BILBO 9

 BILBO Summary
Advantages
z Test-per-clock archtecture
z Pseudo-exhaustive testing
™ No need for fault simulation
z Works well for pipelined applications
Disadvantages
z Difficult to implement in practical applications
™ Multiple test sessions require
¾ Test session scheduling can be difficult
™ Requires multiple primitive polynomials of varying degrees
™ Register self-adjacency difficult to overcome
z Higher area overhead than other BIST approaches
™ More than two gate delays in every critical path
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