FULL ADDER USING HALF ADDER COMPONETS VERILOG CODE AND

ITS TESTBENCH:
HALF ADDER:
module Half_Adder( a, b, cout, sum);
input a, b;
output cout, sum;
and #2 (cout, a, b);
xor #3 (sum, a, b);
endmodule

FULL ADDER:
module Full_Adder (a, b, c, cout, sum);
input a, b, c;
output cout, sum;
wire w1, w2, w3;
// Instantiate two Half Adders
Half_Adder HA1 (a, b, w1, w2);
Half_Adder HA2 (w2, c, w3, sum);
or #2 (cout, w1, w3);
endmodule

TESTBENCH:
module Test_Full_Adder;
reg a, b, c;
wire sum, cout;
// Instantiate the module to be tested
Full_Adder FA (a, b, c, cout, sum);

initial begin
$dumpfile("Test_Full_Adder.vcd");
$dumpvars(1, FA);
a=0; b=0; c=0; // at t=0 time units
#10 a=1; b=1; // at t=10 time units
#10 a=0; b=0; c=1;// at t=20 time units
#10 a=1; c=0; // at t=30 time units
#10 $finish; // at t=40 finish simulation
end
endmodule