module ALU(result, a,b,op);

input [15:0] a;
input [15:0] b;
wire [15:0] alu_control;

output reg [15:0] result;

input [7:0] op;

parameter ADD= 8'b00001000;

parameter SUB=8'b00001001;
parameter MOV=8'b00001010;
parameter AND=8'b00001011;
parameter OR=8'b00001100;
parameter SHR=8'b00001101;
parameter SHL=8'b00001110;
parameter XOR=8'b00001111;

always @(a,b,op)
begin
case(op)
ADD: result = a + b;
SUB: result = a - b;
SHL: result = a<<b;
SHR: result = a>>b;
AND: result = a & b;
OR: result = a | b;
XOR: result = a ^ b;
default:result = 0;
endcase
end

endmodule
module testbench;

reg[15:0] tA, tB; //input testbench

reg[7:0] topcode;
wire [15:0] tresult;

parameter totaltime=300;

ALU M3(tresult,tA,tB,topcode);
initial #totaltime $finish;

initial
begin
tbA=9312;tB=9234;topcode=8;
#10 tA=tresult; tB=5872;topcode=9;
#20 tA=tresult;tB=7234;topcode=12;
#30 tA=tresult;tB=7121;topcode=11;
#45 tA=tresult;tB=1111;topcode=10;
#55 tA=tresult;tB=1111;topcode=8;
#60 tA=tresult;tB=3;topcode=13;

end
endmodule