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Complete address, phone number fax number & email address of corresponding author
Nikos Petrellis
Assistant professor
Computer Science and Telecommunications Dept.
TEI of Larisa
TEI campus,
Larisa 41110, Greece
Tel: +302410684542
Fax: +302410684573
Email: npetrellis@teilar.gr
Keywords
1. Introduction
Biosensors often allow chemical reactions that influence their capacitance [1]. Such biosensors are used for example in
Deoxyribonucleic acid (DNA) analysis as described in [2]. Although the capacitance variation is usually slow and does not
require fast digitisation, a high ADC resolution is necessary to observe small capacitance changes starting from an arbitrary
high initial value within a range of e.g., 1000pF. The DNA used in these sensors can be retrieved from tissues, blood, saliva
etc. Genotype or expression analysis can be based on genomic or complementary DNA respectively. The single stranded
DNA binds to a complementary stranded DNA on a biosensor array. Reactions of this type are often called “hybridisation”
and a biosensor capacitance change occurs as a result.
A hybridisation requires often several minutes or even hours to complete. Although, the monitoring of each individual
biosensor is slow, a large number of biosensors (e.g., 64 or 256) may have to be read at regular time intervals. It is essential
in this case to achieve a sensitivity of a few fF although the initial capacitance of a biosensor may start from an arbitrary high
value (up to 1nF). The target in such applications is to accurately monitor how the biosensor capacitance changes rather than
recording its absolute capacitance values.
Capacitive sensors are also used in several other applications like humidity [3] and pressure [4] measurement,
gyroscopes [5] etc. The most popular method for capacitance measurement is the use of Charge Sensitive Amplifiers (CSA)
[2] or Switched Capacitance Interface (SCI) [6] or Capacitance to Voltage Amplifier [7]. In the Charge Sensitive Amplifiers
a voltage pulse is applied to the capacitor under test and the charge stored there is distributed to a reference capacitor when
the input pulse ends. An operational amplifier is used to integrate the voltage accross the reference capacitor and the output of
this amplifier may be either a sawtooth curve or a voltage level. In the first case a low threshold comparator may convert the
sawtooth curve to a digital pulse whose duration is proportional to the measured capacitance. A counter enabled by the output
of the comparator may provide a digital representation of the measured capacitance [2]. If the CSA output is a voltage level,
then an ADC like Sigma-Delta, Successive Approximation, Pipelined etc, with appropriate resolution may convert this
voltage indication to a digital representation of the capacitance. Switched Capacitance Interface circuits are actually CSAs
that use several switches to charge/discharge the reference and the measured capacitor rather than accepting a voltage pulse at
their input. In [8] a feedback path connects the output of a CSA or SCI stage to the parasitic capacitances minimizing their
effect in linearity and accuracy.
Differential Capacitance (i.e., the difference between two unknown capacitors) can be measured by circuits like the one
presented in [9] or [10]. In non-differential capacitance applications the difference between a reference and the unknown
capacitor is estimated [6]. The closer the reference capacitor to the unknown one is, the higher the accuracy that can be
achieved. For this reason, a configurable reference capacitor has been proposed in [11] where 6 input sensors are multiplexed
and a combination of 3 capacitors forms a reference value. The first author of [11] has also presented a hummidity and
temperature sensor control method based on switching elements that produce pulse series that can be integrated in order to
estimate the sensor values [12]. The output of the employed CSA is digitally processed. Configurable on-chip reference
capacitor has also been used in [6]. The reference capacitance can be configured in the range of 250fF to 15pF in steps of
250fF.
In a recent patent [13] an appropriate readout system for strain and accelerometer capacitive sensors used in Micro-
Electro-Mechanical Systems (MEMS) is presented. In this approach a specific number of actuator voltage pulses with the
same polarity are applied to the sensors and integrated by an SCI circuit that requires a number of switching clock signals
(for the Integrate, Reset, Sample stage) leading to a final voltage level that is measured by an ADC. Using multiple actuator
voltage pulses instead of a single one and integrating the measured capacitor output, compensates potential noise problems (it
can be viewed as a kind of averaging) and adjusts the final output voltage to a desired range eliminating the need of a gain
control mechanism. Moreover, the approach presented in [13] does not need actuator voltage pulses with alternating
polarities to be applied in order to avoid an asymmetric positioning of the sensor. These are the advantages of the approach
presented in [13] compared to a similar read out system presented in [14]. Nevertheless, the accumulation of multiple
measurements through the integration performed by a SCI circuit like the one presented in [12] increases the latency of a
single sensor read. Using the suggested clock frequency of 10.8kHz the strain sensors can be read with a 20Hz rate and a
±1% error. A very accurate capacitance measurement is performed in [15] based on a delta-sigma converter and a high
precision calibration stage.
The specific system described in this paper can cover a very broad capacitance range of 640pF with an accuracy of up to
2.44fF. It will be made clear however, that different ranges and resolutions can also be supported based on the proposed
architecture. None of the approaches referenced above can cover such a wide range with this accuracy. Moreover, the system
can be implemented using low die area mainly due to the small size of the used ADC. The system described in this paper has
been partially implemented and evaluated for the read-out of sensors like the ones described in [1]. More specifically, an
address decoder that selects one of 64 biosensors has been implemented along with a CSA like the one presented in [6] or
[11] to the input of which the selected biosensor is connected. These modules have been implemented using TSCM90nm
CMOS technology. A digitally implemented Finite State Machine (FSM) was described in VHSIC Hardware Description
Language (VHDL) and evaluated seperately using an extremely low cost Altera EPM7064SLC44-10 CPLD that can connect
to the CSA, an appropriate combination of external reference capacitors that can provide a reference value between 0 and
630pF in steps of 10pF. Of course the choice of the specifc hardware description language and CPLD component is not
restrictive. They were employed just to demonstrate the low complexity of an FSM like the one required by the proposed
system. The CSA output can be measured using an appropriate ADC according to the application sensitivity specifications.
The authors have proposed a low area/power ADC with a configurable resolution of 4 to 12 bits that could have been
employed [16][17].
The CSA used and its simulated output is presented in Section 2. The biosensor array readout system and the
implementation of the FSM used for the self-configuration of the reference capacitance are presented in Section 3. Finally,
the readout speed and the resolution that can be achieved are discussed in Section 4 along with a comparison with the
referenced approaches that provide information about the input capacitance range and the accuracy that they achieve.
- CSA Output
Cx Cref
+ Vout
Φ VA
GND or
Φ Φ~ V
ref reset
Fig. 1. Charge Sensitive Amplifier.
The simplest implementation of the CSA front end appears in Fig. 1.The unknown capacitance Cx is compared to the parallel
reference capacitor Cref and the output of the integrator is given by equation (1) when the integration is complete [6].
C x C ref
Vout V A (1)
Cf
The voltage VA is the Φ signal amplitude. The reset signal has the same period with Φ or Φ~ but lower duty cycle and is
used to discharge Cf when Φ is high. Appropriate shifting of the output voltage can be performed if the non-inverting input of
the operational amplifier of Fig. 1 is connected to a reference voltage V ref instead of ground. In this case, the output Vout is
incremented by Vref.
Using a voltage indication that is linearly proportional to the capacitance under test is very important. In [2], no reference
capacitor Cref is used and the feedback one is discharged through a resistance Rdis that is used in place of the reset switch of
Fig. 1. In this case, the varying current that discharges a feedback capacitor like C f of Fig. 1 leads to an integrator output of
the form:
Q t /
Vout e (2)
Cf
where Q is the charge integrated by Cf during each pulse period and τ=CfRdis. The authors in [2] use a special technique with
schottky diodes to keep the discharge current stable and make the CSA output linear for broader capacitive input ranges.
In the present work, the approach of Fig. 1 is used due to its robustness and simplicity since no special components like
schottky diodes are needed. The integrator is implemented by the operational amplifier presented in [11] that does not require
additional bias voltages. In Fig. 2, the shape of the Fig. 1 CSA circuit signals is shown. A parametric post-layout simulation
has been performed for the CSA output by the Spectre simulator in Cadence environment for Cx values between 150pF and
160pF in Fig. 3. The linearity behavior of the CSA circuit in this range has been experimentally verified using external
commercial capacitors of 150, 156 and 160pF. A 150pF value has been chosen for the capacitors Cref and Cf of the CSA
circuit shown in Fig. 1. A similar parametric post-layout simulation for Cx values between 500pF and 510pF is shown in Fig.
4. The linearity behavior of the CSA circuit in this case has also been experimentally verified using combinations of
commercial capacitors and a 500pF value has been chosen for the capacitors Cref and Cf. The signals Φ and Φ~ have a period
of 200usec but it is obvious from Fig. 3 and Fig. 4 that a significantly shorter period could have been used since the critical
transient interval at the beginning of Φ pulse is quite shorter. More specifically a 10usec period is adequate for these signals.
The duty cycle of Φ (or Φ~) and the reset signal is 50% and 25% respectively. The output of the CSA for a capacitance
difference between 0 and +10pF is quite linear as can be seen by Fig. 3 and 4. Linearity issues will be discussed in more
detail in Section 4. The appropriate time to sample the CSA output is when Φ is high. At this time interval an ADC with
appropriate resolution can convert the analog CSA output to a digital representation of the measured capacitance.
CSA Signals
390
380
150pF
370
151pF
360 152pF
CSA Output (mV)
153pF
350
154pF
340
155pF
330 156pF
157pF
320
158pF
310 159pF
300 160pF
0 50 100 150 200
Time (us)
330 500pF
501pF
325
502pF
CSA Output (mV)
320 503pF
504pF
315 505pF
506pF
310
507pF
305 508pF
509pF
300
510pF
0 50 100 150 200
Time (us)
n-bit ADC
Φ
CSA STB
FSM
CMP Internal Clock
NEG Generator CLK
POS CMP
Φ~
CCCs
… …
CCCs
CBCs …
..
CBCs
CACs
…
..
CACs
ENCODER
where the digits b2, b1 and b0 can be 0, 1, 2 or 3 and denote how many capacitors of 160pF, 40pF and
10pF respectively have to be connected in parallel. Notice that each external capacitor value is an
exponential value of 4 multiplied by 10pF in order to create all the capacitance reference combinations
between 0 and 630pF with steps of 10pF. In order to implement any of these reference capacitor
combinations, three sets (A, B and C) of 3 capacitors each, is required. The first set (A) has 3 identical
10pF capacitors. The second set (B) has 3 identical 40pF and the third set (C) has 3 identical 160pF
capacitors. Higher number of potential combinations can be achieved if more than 3 sets are defined or
if the 3 digits in equation (3) had a potentially different radix:
It should be noticed, that in the present design, radix-4 was used in order to cover the specific
capacitance range with the simplest reference capacitance bank and interconnection scheme. A
different numerical system may have been selected if a different range had to be covered. The use of
external commercial capacitors has some significant drawbacks. First of all, there are several
capacitance values that are not commercially available in a single component and have to be formed by
a combination of capacitors connected in parallel or even in series. Then, each commercial component
has a tolerance from its typical value. Although expensive components may have a small tolerance
(e.g., 1%), this tolerance has to be taken into consideration. Parasitic capacitances affect the typical
capacitor values too. More accurate capacitor ratios could have been achieved if the reference
capacitors were implemented on-chip but their absolute values in this case would have to be quite
smaller significantly limiting the capacitance input range of the whole system.
The tolerance of the external reference capacitors is handled in this work by using one redundant
capacitor in each one of the A, B and C sets mentioned above. Although the reference capacitance is
still formed in a radix-4 numerical system as described by equation (3), the digits b 2, b1 and b0 can now
have 5 values: 0-4 allowing the connection of up to 4 identical capacitors in parallel. Using this
extended radix-4 notation a specific capacitance value may have more than one representation. For
example, the capacitance of 160pF can be implemented by using a single 160pF capacitor (b 2=1, b1=0
and b0=0) or by connecting in parallel four 40pF capacitors (b 2=0, b1=4 and b0=0), or by connecting in
parallel three 40pF and four 10pF capacitors (b2=0, b1=3 and b0=4). This redundancy reassures that
there will be no gaps due to component tolerances in the supported input capacitance range.
The CSA output is monitored by a pair of comparators (CMP) that decide whether the measured
capacitance is higher or lower than the current reference one (indications POS and NEG respectively of
Fig. 5). These indications are used by the FSM that controls the 3 shift registers (A, B and C). The
operation of each one of these shift registers is depicted in Fig. 6.
EN PRESET RESET
0 IN CLK
SHIFTER
S3 S2 S1 S0
1 1 1 1 after PRESET=1
0 1 1 1 after 1st clk period (capacitor controlled by S3 disconnected)
0 0 1 1 2nd clk period (capacitor controlled by S3, S2 disconnected)
0 0 0 1 3rd clk period (capacitor controlled by S3, S2, S1 disconnected)
0 0 0 0 4th clk period (all capacitors disconnected)
Each shift register is a Serial In, Parallel Out (SIPO) register with a Reset, Preset, Enable and
Clock input. The bit that is shifted in, is inserted by the IN pin and the outputs of the shifter are
available at the S3-S0 pins. During the reference capacitor self-configuration phase, all the outputs of a
shift register have to be initially reset (disconnecting all the attached capacitors), then at a specific time
all of them have to be preset to 1 (connecting all the attached capacitors in parallel) and finally some
capacitors have to be gradually disconnected by shifting in, one or more 0’s as shown in Fig. 6. The
algorithm that can exploit such a shifting operation in order to perform the appropriate self-
configuration is the following:
1) Connect all CC capacitors (Cref=4CCCS)
2) Repeat disconnecting CC capacitors until Cref=cCCCS<Cx c=4, 3, 2, 1, 0
3) Connect all CB capacitors (Cref=cCCCS+4CBCS)
4) Repeat disconnecting CB capacitors until Cref=cCCCS+bCBCS<Cx b=4, 3, 2,
1, 0
5) Connect all CA capacitors (Cref=cCCCS+bCBCS+4CBCS)
6) Repeat disconnecting CA capacitors until Cref=cCCCS+bCBCS+aCACS<Cx a=4,
3, 2, 1, 0
NEG NEG
POS /
{ DISABLE C
PRESET B
S1 ENABLE B } S2
STB / POS /
{ RESET { DISABLE B
PRESET C PRESET A
ENABLE C ENABLE A }
BUSY }
POS /
{ DISABLE A
S0 READY } S3
NEG
Fig. 7. A simplified form of the FSM used to self-configure the reference capacitance
Initially, the maximum reference capacitance that can be formed by connecting in parallel all the
CCCS capacitors (4x160pF=640pF in the specific implementation) is set and compared to the unknown
capacitance of the selected biosensor. If its value is smaller than the reference one, the 2 nd step of the
algorithm described above disconnects the appropriate number of 160pF capacitors until the biosensor
capacitance is higher than the current reference capacitance. In the 3rd step of this algorithm, all the
CBCS capacitors (4x40pF=160pF in the specific implementation) are connected in parallel with the
CCCS ones left in parallel by step 2. Then in step 4, some 40pF capacitors are disconnected one by one
until the reference capacitance gets smaller than that of the selected biosensor. A similar operation is
repeated for the 10pF capacitors (CACS). The steps 1, 3 and 5 of the algorithm described earlier are
implemented by activating the Preset input of the corresponding shift register. The steps 2, 4 and 6 are
implemented by shifting an appropriate number of 0’s in the corresponding register as shown in Fig. 6.
This zero shifting is stopped when the enable signal EN of the corresponding shifter is disabled by the
FSM.
A simplified structure of the FSM appears at Fig. 7. The initial state is S0. When the signal STB is
activated, the 3 shift registers A, B and C are all reset for a certain period and then shift register C is
preset to connect all the CCCS capacitors in parallel. The Enable signal of shift register C is activated
then, to allow the gradual disconnection of CCCS capacitors as indicated by the 2nd step of the algorithm
described earlier.
The FSM visits state S1 at this point and stays there for as long as the measured capacitance C x is
smaller than the reference one Cref (indication NEG). When this condition becomes false (indication
POS), an FSM transition to state S2 occurs, followed by the disable of the shift register C, the preset of
the shift register B to connect in parallel all the CBCS capacitors and eventually the enable of B to allow
the gradual disconnection of the CBCS capacitors. The CBCS reference capacitance disconnection stops
when the measured capacitance Cx gets smaller than the reference one Cref (indication POS, transition
to S3 state). The whole procedure is repeated in the same manner by connecting in parallel all the C ACS
capacitors and gradually disconnecting them until the reference value C ref that is closer to the unknown
capacitance Cx is determined.
The implementation of the FSM in a hardware description language as VHDL is easier if the 4
state FSM described above is extended to an 8-state FSM as shown in Fig. 8 where the FSM is
simulated in Altera Max Plus II. The VHDL code of the FSM can run on an Altera EPM7064SLC44-
10 CPLD. The signals STB, POS and the clock CLK are the input of the FSM. The signals RESET,
PRESET and EN(ABLE) are the corresponding ones for each shift register and operate as described
above. The internal signal “state” indicates the current FSM state while “cnt” is an internal counter
used to determine the duration of the RESET and PRESET pulses. The BSY_NRDY signal prohibits
the acquisition system from retrieving invalid transient or inaccurate biosensor measurements as long
as the reference capacitor is in a self-configuration mode.
The shifter outputs are encoded in a k-bit output DB that represents a value between 0 and 63 in
the specific implementation. For this reason, k=log264=6 bits. The specific encoding can be obviously
determined by simplifying the boolean expressions that relate the k outputs (DB0..DBk-1) with the 12
encoder inputs (the shifter outputs SC, SB and SA) but the detailed description of the encoding scheme
is out of the scope of this paper.
The n-bit ADC generates the indication DD that can be combined with DB by the acquisition
system that controls the readout circuit of Fig. 5 in order to estimate the biosensor capacitance using
the following equation:
Cs
C x DB C s DD (5)
2n
Decoder PISO/SIPO
6x64 registers
CSA
Fig. 9. The layout of the IC with the Decoder 6x64 and the CSA used.
(a)
(b)
Fig. 10. The detailed layout of the Decoder 6x64 (a) and the CSA (b).
As already mentioned, the FSM operation was evaluated using an Altera EPM7064SLC44-10
CPLD on a low cost Leap Electronics FPT-3 evaluation board. The 6x64 biosensor address decoder
and the CSA were evaluated using the integrated circuit (IC) implemented in TSCM90nm CMOS
technology that is shown in Fig. 9. This IC was developed by the authors for a biosensor read-out
circuit based on a slightly different configuration. More specifically, the CSA in this IC generates a
sawtooth pulse converted by a comparator to a rectangular pulse with a duration that is proportional to
the measured capacitance. This pulse duration is measured by a counter. The counter indication and the
biosensor address are transferred in a serial manner using Parallel In Serial Out (PISO) and Serial In
Parallel Out (SIPO) registers.
The layout of the address decoder and the CSA are shown in Fig. 10a and 10b respectively. The
evaluation board with the specific IC developed by the authors is shown in Fig. 11. The CSA inputs
and output of the implemented IC are connected as was shown in Fig. 1 in order to evaluate the
operation demonstrated by Fig. 2-4 with appropriate reference capacitors. The STB signal is used to
generate the appropriate Φ signal that is applied to the selected biosensor through the address decoder
of the implemented IC. The address of the biosensor is sent using a serial data and a serial clock line
that is shown in Fig. 12. The external serial input/output signals of the implemented IC are handled by
a low cost microcontroller that offers a standard interface to a host computer (RS232 or USB).
Fig. 12. The 6-bits of the biosensor address plus two reserved bits are sent along with a serial clock (top signal) and then the STB
signal is initiated to start the measurement procedure (bottom signal).
𝐶𝑠
𝐶𝑥 = 𝐷𝐵 ∙ 𝐶𝑠 + 𝐷𝐷 ∙ (1 − 𝑒𝑟𝑟𝑓𝑎𝑐𝑡) (6)
2𝑛
Difference between
CSA Output the present and the
Capacitance Voltage Level previous level
(pF) (mV) (mV)
150 311.52
151 317.99 6.47
152 324.46 6.47
153 330.93 6.47
154 337.41 6.48
155 343.9 6.49
156 350.39 6.49
157 356.88 6.49
158 363.38 6.5
159 369.89 6.51
160 376.4 6.51
Table 1. Estimation of the CSA output level difference between successive parametric simulations for
input capacitance between 150 and 160pF.
Table 2. Estimation of the CSA output level difference between successive parametric simulations for
input capacitance between 500 and 510pF.
Let S be the number of samples required by a biosensor in a time interval T. If there are B sensors
that have to be successively read, then the latency for an individual read should not exceed T/(S∙B). In
a realistic scenario, if B=64 and each sensor has to be read in the worst case S=100 times/sec, then the
time needed for a single read should not exceed 1/6400=156usec and the ADC conversion rate should
be at least (S∙B)/T=6400 samples/sec. The readout system presented in Fig. 5, requires in the worst
case 12 sequential shifts until the correct reference capacitance is determined and the biosensor value is
accurately read. Each individual shift requires a time interval as the one shown in Fig. 3 or 4. This
interval can be shortened from 200usec to less than 10usec since the critical time that has to be
respected is the settling of the CSA output at the beginning of the Φ pulse (time point 100usec in Fig. 3
or 4) and this time is much shorter than 10usec. Thus, each biosensor read would require about 120usec
which is lower than the 156usec limit that was estimated in the above example.
A comparison between the proposed architecture and the features of the referenced approaches that
give such details is performed in Table 3. As can be seen from this table, higher resolution can be
achieved in [11] and [15] but both of these approaches operate on an input range of 10pF. This range
may acceptable by several applications but others including biosensor readout circuits operate in a
broader range because the initial capacitance of a single sensor may be arbitrary high as already
described in Section 1. A broader capacitance range is covered in [2] but the resolution in this case is
much worse (1pF). The proposed configurable reference capacitance scheme can be adopted by any
architecture that has an input range that is determined by the value of a reference capacitance.
6. Acknowledgment
This work has been developed in the context of the project Lab On Chip supported by Corallia Cluster
Initiative.
7. Conflict of Interest
None.
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