intel M8282/M8283 OCTAL LATCH Miltary Fully Parallel 8-Bit Data Register and m 3State Outputs Buffer 1m No Output Low Noise When Entering or '§ Transparent During Active Strobe Leaving High Impedance State 1 Supports M808SAH, M8048AH, M8086, Military Temperature Range: M8088 and M80186 55°C to + 125°C (Tc) High Output Drive Capability for Driving System Data Bus ‘The M8282 and M8283 are 8-bit bipolar latches with 3-state output butters. They can be used to implement latches, butfers, or multiplexers. The M8283 inverts the input data at its outputs while the M8282 does not. ‘Thus, all of the principal peripheral and input/output functions of a microcomputer system can be implemented with these devices. ari028—4 271028-1 Figure 1. Logie Diagrams 271023-5 2ri033-6 Figure 2. Pin Configurations December 1963, 17-110 ‘Order Number: 271023-003M6262/M6283 Table 1. Pin Description ‘Symbol Type Name and Function ‘STB 1 ‘STROBE: STB is an input control pulse used to strobe data at the data input pins (Ao~A7) into the data latches. This signal is active HIGH to admit input data. The data is latched at the HIGH to LOW transition of STB. OE 1 ‘OUTPUT ENABLE: OE is an input control signal which when active LOW enables the contents of the data latches onto the data output, pin (Bq-B7). OE being inactive HIGH forces the output butfers to their high impedance state. ‘Ao-Ay 1 DATA INPUT PINS: Data presented at these pins satisfying setup time requirements when STB is strobed is latched into the data input latches. Bo-87 ° DATA OUTPUT PINS: When OE is true, the data in the data latches Meze2 is presented as inverted (M8283) or non-inverted (M8282) data onto Bo-B7 the data output pins. Ma283 FUNCTIONAL DESCRIPTION ‘The M8282 and M8283 octal latches are 8-bit latch- 8s with 3-state output butters. Data having satisfied the setup time requirements is latched into the data latched by strobing the STB line HIGH to LOW. ABSOLUTE MAXIMUM RATINGS* Case Temperature Under Bias(®). — 55°C to + 125°C Storage Temperature ..........-65°Gto +150°C ‘All Output and Supply Voltages .....—0.5Vto +7V All Input Voltages... ~1.0V to +5.5V Power Dissipation . .. WwW Holding the STB line in its active HIGH state makes the latches appear transparent. Data is presented to the data output pins by activating the OE input line. When OF is inactive HIGH the output butfers are in their high impedance state. Enabling or disabling the ‘output buffers will not cause negative-going tran- sients to appear on the data output bus. “Notice: Stresses above those listed under “Abso- Jute Maximum Ratings" may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any ‘other conditions above those indicated in the opera- tional sections of this specification is not implied. Ex- posure to absolute maximum rating conditions for ‘extended periods may affect device reliability. D.C. CHARACTERISTICS Voc = 5V +5%, Tol) = —55°C to + 125°C ‘Symbol Parameter Min | Max | Units ‘Test Conditions Ve Input lamp Voltage =1 v Ig = —5 mA, loc Power Supply Current 160 mA i Forward input Current =02 mA Ve = 0.45V. i la Reverse Input Current 50 BA Va = 5.25V | Vou Output Low Voltage 0.45 Vv lou = 20 mA | Vou ‘Output High Voltage 24 Vv lon = —5mA | lorr Output Off Current $50 vA Vorr = 0.45t05.25V | Vi Input Low Voltage 08 v 5.0V (Note 1) Vu Input High Voltage 20 v 5.0V (Note 1) Cw Input Capacitance 12 pF 1 MHz 2.8V. Voc = 5V 05°C NOTE: 4. Output Loading lo. = 20 mA, low = ~5 mA, C= 300 pF 2. Case Temperatures are “instant on. watintel M6282/M8283 A.C. CHARACTERISTICS Voc = 5V +5%, Tcl2) = —55°C to + 125°C Loading: Outputs—lo. = 20 mA, low = —5 mA, CL = 300 pF 1. Soe wavotorms and test load circuit on following page. 2. Case temperatures are “instant on". ‘A.C. TESTING INPUT, OUTPUT WAVEFORM ‘Symbol Parameter Min Max Units: Test Conditions TIVOV Input to Output Delay (Note 1) Inverting 25 ns Non-inverting 35, ns TSHOV STB to Output Delay Inverting 45 ns Non-lnverting 55 ns TEHOZ Output Disable Time 25 ns TELOV Output Enable Time 10 50 ns TWVSL Input to STB Setup Time 0 ns TSLX Input to STB Hold Time 25 ns TSHSL. ‘STB High Time 15 ns TOLOH Output Rise Time 20 ns From 0.8V to 2.0V TOHOL Output Fall Time 12 ns From 2.0V to 0.8V NoTes: TESTING LOAD CIRCUIT inpur/ourpuT ar023-1 ‘AC. Testing: Inputs are Driven at 2.4V fora Logie "1" and 0.45 {or a Loge “0 Ting Measurements are Made at 1.5V for Both 1 Loge."1" and "0". Input Riso end Fall Times are Measured ftom OV to 20V and are Driven at § ns +2 ns. 17112intel Meze2/mez83 WAVEFORMS wnat ourmurs 2710239 NOTES: 41, M8289 only—output may be momentarily invalid following the high going STB transition, 2. Al timing measurements are made at 1.5V unloss atherwiso noted. 17-118