Professional Documents
Culture Documents
Location Capacity
• CPU • Word size
• Internal —The natural unit of organisation
• External • Number of words
—or Bytes
Unit of Transfer Access Methods (1)
• Internal • Sequential
—Usually governed by data bus width —Start at the beginning and read through in
• External order
—Usually a block which is much larger than a —Access time depends on location of data and
word previous location
—e.g. tape
• Addressable unit
—Smallest location which can be uniquely
• Direct
addressed —Individual blocks have unique address
—Word internally —Access is by jumping to vicinity plus
—Cluster on M$ disks sequential search
—Access time depends on location and previous
location
—e.g. disk
Direct Mapping
Direct Mapping Address Structure
• Each block of main memory maps to only
one cache line Tag s-r Line or Slot r Word w
—i.e. if a block is in cache, it must be in one 14 2
8
specific place
• Address is in two parts • 24 bit address
• 2 bit word identifier (4 byte block)
• Least Significant w bits identify unique • 22 bit block identifier
word — 8 bit tag (=22-14)
— 14 bit slot or line
• Most Significant s bits specify one
• No two blocks in the same line have the same Tag field
memory block • Check contents of cache by finding line and checking Tag
• The MSBs are split into a cache line field r
and a tag of s-r (most significant)
Direct Mapping
Cache Line Table Direct Mapping Cache Organization
• Cache line Main Memory blocks held
• 0 0, m, 2m, 3m…2s-m
• 1 1,m+1, 2m+1…2s-m+1
Direct Mapping
Example Direct Mapping Summary
• Address length = (s + w) bits
• Number of addressable units = 2s+w
words or bytes
• Block size = line size = 2w words or bytes
• Number of blocks in main memory = 2s+
w/2w = 2s
• Number of lines in cache = m = 2r
• Size of tag = (s – r) bits
Direct Mapping pros & cons Associative Mapping
• Simple • A main memory block can load into any
• Inexpensive line of cache
• Fixed location for given block • Memory address is interpreted as tag and
—If a program accesses 2 blocks that map to word
the same line repeatedly, cache misses are • Tag uniquely identifies block of memory
very high
• Every line’s tag is examined for a match
• Cache searching gets expensive
Associative
Fully Associative Cache Organization Mapping Example
Associative Mapping
Address Structure Associative Mapping Summary
• Address length = (s + w) bits
Word • Number of addressable units = 2s+w
Tag 22 bit 2 bit words or bytes
• 22 bit tag stored with each 32 bit block of data • Block size = line size = 2w words or bytes
• Compare tag field with tag entry in cache to • Number of blocks in main memory = 2s+
check for hit w/2w = 2s
• Least significant 2 bits of address identify which
• Number of lines in cache = undetermined
16 bit word is required from 32 bit data block
• e.g. • Size of tag = s bits
— Address Tag Data Cache line
— FFFFFC FFFFFC24682468 3FFF
Word
Tag 9 bit Set 13 bit 2 bit
Two Way
Set Set Associative Mapping Summary
Associative • Address length = (s + w) bits
Mapping
Example • Number of addressable units = 2s+w
words or bytes
• Block size = line size = 2w words or bytes
• Number of blocks in main memory = 2d
• Number of lines in set = k
• Number of sets = v = 2d
• Number of lines in cache = kv = k * 2d
• Size of tag = (s – d) bits
Replacement Algorithms (1) Replacement Algorithms (2)
Direct mapping Associative & Set Associative
• No choice • Hardware implemented algorithm (speed)
• Each block only maps to one line • Least Recently used (LRU)
• Replace that line • e.g. in 2 way set associative
—Which of the 2 block is lru?
• First in first out (FIFO)
—replace block that has been in cache longest
• Least frequently used
—replace block which has had fewest hits
• Random
External memory slower than the system bus. Add external cache using faster 386
memory technology.
Increased processor speed results in external bus becoming a Move external cache on-chip, 486
bottleneck for cache access. operating at the same speed as the
processor.
Internal cache is rather small, due to limited space on chip Add external L2 cache using faster 486
technology than main memory