Professional Documents
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DLF Rep
DLF Rep
No-
1- Introduction
a) History of digital clocks 01
Significance:
Digital clocks are being a very useful components of our lives. Regarding this change the need of
accurate and simple materials also dramatically increasing. Our proposed project uses a very simple
logic devices to build an accurate synchronous digital clock that is expected to satisfy the need of
those materials.
Construction & Design:
We are providing a breif explanation of construction of this project.
Working Principle:
We know that 60 seconds equal to 1 minute and 60 minutes equal to 1 hour. Hence the
minute section is drived by second section and hour section by the minute section. Each
of the minute and second section has been designed to give a count from 00 to 59 after
which it resets to 00 and the hour section to give a count from 00 to 12 hours after
which it resets to 00. For each cycle of 00 to 59 in second section the minute section
increases its count by 1. Similarly for each cycle of 00 to 59 in minutes section the hour
section increases its count by 1. In this way when the clock reaches 23 hrs. 59mins.
59secs. each of the section resets to 00 giving us a display 00.00.00 popularly known as
the 0th hour.
Hardware:
We used following items in the hardware construction for the digital clock.
555- Timer:
In astable mode, the '555 timer' puts out a continuous
stream of rectangular pulses having a specified frequency.
A resistor (call it R1) is connected between Vcc and the
discharge pin (pin 7) and another (R2) is connected
between the discharge pin (pin 7), and the trigger (pin 2)
and threshold (pin 6) pins that share a common node.
Hence the capacitor is charged through R1 and R2, and
discharged only through R2, since pin 7 has low
impedance to ground during output low intervals of the cycle, therefore discharging the
capacitor. The use of R2 is mandatory, since without it the high current spikes from the
capacitor may damage the internal discharge transistor.
7 Segment Display:
To convert a binary number between 0 and 9 to the
appropriate signals to drive a 7- segment display,
you use a (appropriately named) "binary number to
7-segment display converter." This chip looks at the
binary number coming in and turns on the
appropriate bars in the 7-segment LED to display
that number. If we are displaying the seconds, then
the seconds part of our clock looks like this:
Designing:
The entire project has been divided into four modules. They are as follows:
Seconds section
Using two counters and drivers ICs (IC 4026) in such a way that this portion
produces output from 00 to 59 continuously with a frequency of 1 Hz (1pps).
Using seven-segment display (IC 5001) to display the counts. Both the ICs are of
common cathode type.
Checking the output of the circuit.
Minutes section
Repeating the same circuit as that of the second section, but here the output should
count from 00 to 59 with a frequency of 1 Hz for 1 ppm.
Checking the output.
Hours section
Designing the circuit in such a way so that the output resets to 00 automatically
displaying 12.59.59.
Here the counting proceeds with a frequency of one pulse per hour.
Checking the output.
Assembling
Assembling the three sections together.
B) Checking the output of the final circuit.
Software:
The software part is sub divided into three parts
1- Proteus Schematic Layout
2- Proteus PCB Layout
3- Final PCB Output
As the stable timer requires a very precised value of capacitors and the market is short of it,
therefore our clock is 17 minutes back from the original clock. We will work on the precised
capaitors further. Below is the implementation for the 1hz frequency generator on proteus.
Proteus Stimulation:
Up view:
Down View:
For Clock Circuit:
We used 6 seven segment displays along with 4026 IC and AND Gate ICs.
Proteus Stimulation:
Up View:
Down View: