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Chapter 8: Main Memory
Operating System Concepts – 8th Edition Silberschatz, Galvin and Gagne ©2009
Chapter 8: Memory Management
 Background
 Swapping
 Contiguous Memory Allocation
 Paging
 Structure of the Page Table
 Segmentation
 Example: The Intel Pentium
Operating System Concepts – 8th Edition 8.2 Silberschatz, Galvin and Gagne ©2009
Objectives
 To provide a detailed description of various ways of organizing

memory hardware
 To discuss various memory-management techniques, including

paging and segmentation
 To provide a detailed description of the Intel Pentium, which supports

both pure segmentation and segmentation with paging
Background
 Program must be brought (from disk) into memory and placed within a
process for it to be run
 Main memory and registers are only storage CPU can access directly
 Register access in one CPU clock (or less)
 Main memory can take many cycles
 Cache sits between main memory and CPU registers
Memory Hierarchy
 Very small, extremely fast, extremely

expensive, and volatile CPU registers
 Small, very fast, expensive, and volatile
cache
 Hundreds of megabytes of medium-speed,
medium-price, volatile main memory
 Hundreds of gigabytes of slow, cheap, and
non-volatile secondary storage
Purpose of Memory Management
 To ensure fair, secure, orderly, and

efficient use of memory
Background
 We must ensure correct operation has to protect the operating
system from access by user processes and to protect user
processes from one another.
 To do this …
 Each process has a range of legal addresses.
 Process can access only these legal addresses.
 We can provide this protection by using two registers:

 Base register – hold the smallest legal physical memory
address.
 Limit register – specify the size of the range.
Base and Limit Registers
 A pair of base and limit registers define the logical address space
30004 + 12090 =
42094!!
 Then, we compare every address generated in user mode with the
registers.
 Any attempt (in user mode) to access operating-system memory or other
users’ memory results in a fatal error.
 Therefore, we can prevent a user program from modifying the code or
data structures of either the operating system or other users.
Memory Management
 Subdividing memory to accommodate multiple processes
 Memory needs to be allocated to ensure a reasonable supply of

ready processes to consume available processor time
Memory Manag. Requirements
 Relocation
 Programmer does not know where the program will be
placed in memory when it is executed
 While the program is executing, it may be swapped to disk
and returned to main memory at a different location
(relocated)
 Memory references in the code must be translated to actual
physical memory address
Memory Manag. Requirements
 Sharing
 Allow several processes to access the same portion of
memory
 Better to allow each process access to the same copy of the
program rather than have their own separate copy
Fixed Partitioning
 Equal-size partitions
 Any process whose size is less than or equal to the partition
size can be loaded into an available partition
 If all partitions are full, the operating system can swap a
process out of a partition
 A program may not fit in a partition. The programmer must
design the program with overlays
 Main memory use is inefficient. Any program, no matter
how small, occupies an entire partition. This is called
internal fragmentation.
Fixed Partitioning
Placement Algorithm
 Equal-size partitions
 Because all partitions are of equal size, it does not matter
which partition is used
 Unequal-size partitions
 Can assign each process to the smallest partition within
which it will fit
 Queue for each partition
 Processes are assigned in such a way as to minimize
wasted memory within a partition
Placement Algorithm
 Problems with equal size fixed partitions: „

 If program is bigger than a partition size, use of
overlays „
 Main memory utilization is extremely inefficient;
Internal Fragmentation – waste of space internal to
partition due to the fact that block of data loaded is
smaller than partition
Placement Algorithm
Dynamic Partitioning
 Partitions are of variable length and number

 Process is allocated exactly as much memory as
required
 Eventually we get holes in the memory. This is called
external fragmentation
 Must use compaction to shift processes so they are
contiguous and all free memory is in one block
A hole of 64K is left after loading 3 processes: not enough room

for another process.
Eventually each process is blocked. The OS swaps out process 2
to bring in process 4.
 Another hole of 96K is created.

 Eventually each process is blocked. The OS swaps out process 1 to
bring in again process 2 and another hole of 96K is created ...
Internal / External Fragmentation
1. Internal Fragmentation – allocated memory may

be slightly larger than requested memory; this size
difference is the memory internal to a partition, that
is not being used.
2. External Fragmentation – total memory space
exists to satisfy a size n request, but that memory
is not contiguous.
Reducing External Fragmentation
 Reduce external fragmentation by doing

compaction:
 Shuffle memory contents to place all free
memory together in one large block (or
possibly a few large ones).
 Compaction is possible only if relocation is
dynamic, and is done at execution time.
Placement Algorithms
 Operating system must decide which free block to allocate to a

process
 Best-fit algorithm
 Chooses the block that is closest in size to the request
 Worst performer overall
 Since smallest block is found for process, the smallest
amount of fragmentation is left
 Memory compaction must be done more often
 First-fit algorithm
 Scans memory form the beginning and chooses the first
available block that is large enough
 Fastest
 May have many process loaded in the front end of memory
that must be searched over when trying to find a free block
 Worst-fit algorithm
 Search the entire list of available memory and allocate the
largest block.
 (The justification for this scheme is that the leftover block
produced would be larger and potentially more useful than
that produced by the best-fit approach.)
 Next-Fit algorithm
 Scans the memory from the location of last

placement and chooses next available block
that is large enough
Question
Assume that the main memory has the following 5 fixed
partitions with the following sizes: 100KB,
500KB, 200KB, 300KB and 600KB (in order)
a) How would each of the First-fit, Best-fit, next fit, Worst-fit
algorithms place processes of 212KB,
417KB, 112KB and 426KB (in order)?
c) Compute the total memory size that is not used for each
algorithm.
d) Which algorithm makes the efficient use of the memory?
 A pair of base and limit registers define the logical address space
 Base register
 Starting address for the process
 Limit + Base / Bounds register
 Ending location of the process
 These values are set when the process is loaded or when the process
is swapped in
 The value of the base register is added to a relative address to
produce an absolute address
 The resulting address is compared with the value in the bounds
register
 If the address is not within bounds, an interrupt is generated to the
operating system
Logical and Physical addresses
 Logical address: An address generated

by the process/CPU; refers to an
instruction or data in the process
 Physical address: An address for a main
memory location where instruction or data
resides
 The set of all logical addresses generated

by a process comprises its logical
address space.
 The set of physical addresses
corresponding to these logical addresses
comprises the physical address space
for the process.
 The run-time mapping from logical to

physical addresses is done by a piece of
the CPU hardware, called the memory
management unit (MMU).
Memory-Management Unit (MMU)
 Hardware device that maps virtual to physical address
 In MMU scheme, the value in the relocation register is added to every

address generated by a user process at the time it is sent to memory
 The user program deals with logical addresses; it never sees the real
physical addresses
Dynamic relocation using a
relocation register
Hardware Support for Relocation
and Limit Registers
Logical and physical addresses
Swapping
 A process can be swapped temporarily out of memory to a backing
store, and then brought back into memory for continued execution
 Backing store – fast disk large enough to accommodate copies of all

memory images for all users; must provide direct access to these
memory images
Schematic View of Swapping
Swapping
 Examples:
 In a round-robin system …
When a quantum expires, the memory manager
will swap out the process that just finished
And swap in another memory for execution.
 In a priority-based system …
If a higher-priority process arrives, the memory
manager can swap out a lower-priority process.
Then load and execute the higher-priority process.
This scheme is sometimes called roll out, roll in.
Cost of Swapping
 Process size = 1 MB
 Transfer rate = 5 MB/sec
 Swap out time = 1/5 sec
= 200 ms
 Average latency = 8 ms
 Net swap out time = 208 ms
 Swap out + swap in = 416 ms
Paging
 Physical address space of a process can be noncontiguous
 Divide physical memory into fixed-sized blocks, called frames

 Divide logical memory into blocks of the same size, called pages
 Size of a page is a power of 2
 Typical page sizes: 1K – 16K
 Keep track of all free frames
 To run a program of size n pages, need to find n free frames and load
program
 Set up a page table to translate logical to physical addresses
 Internal fragmentation (only last page of process)
Address Translation Scheme
 Logical address generated by CPU is (p , d):

 Page number (p) – used as an index into a page table. Page table
entry contains the frame no. f where page p is loaded.
 Page offset (d) – offset within the page
page number page offset

p d
m-n n
 Physical address of the location referenced by (p , d) is computed by

appending d at the end of f, as shown below:
frame number offset
f d
Paging Hardware
Paging Model of Logical and
Physical Memory
Free Frames
Before allocation After allocation
Paging Example
 Page size = 4 bytes 0
Page Frame
 Process address space 1
= 4 pages 0111
 Physical address space 2

= 8 frames
3
 Logical address: (1,3)
= 0111
 Physical address: (6,3)
= 11011
11011
32-byte memory and 4-byte pages

Addressing in Paging
 Logical address space of 16 pages of 1024 words each,
mapped into a physical memory of 32 frames.
 Logical address size?
 Physical address size?
 Number of bits for p, f, and d?
 No. of bits for p = ceiling [log2 16] bits = 4 bits

 No. of bits for f = ceiling [log2 32] bits = 5 bits
 No. of bits for d = ceiling [log2 2048] bits = 11 bits
 Logical address size = |p| + |d| = 4+11 = 15 bits

 Physical address size = |f| + |d| = 5+11 = 16 bits
Paging Example
 Example: if 16 bits addresses are

used and page size = 1K, we need 10
bits for offset and have 6 bits available
for page number.
 Then the 16 bit address, obtained with
the 10 least significant bits as offset
and 6 most significant bits as page
number, is a location relative to the
beginning of the process.
 What is a Logical address of relative

1502?
Paging Example
Example
 32-bit linear address

 Process address space= 232 B
= 4 GB
 4K page size
 Maximum pages in a process address
space = 232 / 4K = 1M
 Number of bits for d = log2 4K
= 12
 Number of bits for p = 32 - 12
Another Example
 Logical address = 32-bit

 Process address space= 232 B
= 4 GB
 Main memory = RAM = 512 MB = 229
 Page size = 4K
 Maximum pages in a process address
space = 232 / 4K = 1M
Another Example
 |d| = log2 4K = 12 bits

 |p| = 32 – 12 = 20 bits
 No. of frames = 512 M / 4 K
= 128 K
 |f| = ceiling [log2 128 K] bits = 17 bits
 Physical address = 17+12 bits
Page Size
 Smaller page size, less amount of internal
fragmentation
 Smaller page size, more pages required per
process
 More pages per process means larger page tables
Translation Lookaside Buffer (TLB)
 Each page reference can cause two physical

memory accesses
 One to fetch the page table (PTBR) Page table
base register
 One to fetch the data
 To overcome this problem a high-speed cache is set
up for page table entries
 Called a Translation Lookaside Buffer (TLB)
 Contains page table entries that have been most
recently used
Translation Lookaside Buffer (TLB)
 Given a logical address, processor examines the

TLB
 If page table entry is present (TLB hit), the frame
number is retrieved and the real address is formed
 If page table entry is not found in the TLB (TLB
miss), the page number is used to index the process
page table
Paging Hardware With TLB
Effective Access Time
 Teffective on a hit = TTLB + Tmem
 Teffective on a miss = TTLB + 2Tmem
 If HR is hit ratio and MR is miss ratio, then
Teffective = HR (TTLB + Tmem) + MR (TTLB + 2Tmem)
 Effective Access Time (EAT)
EAT = Hit_Ratio * Hit_Time + Miss_Ratio * Miss_Time
 Tmem = 100 nsec
 TTLB = 20 nsec
 Hit ratio is 80%
 Teffective = ?
Teffective = 0.8 (20 + 100) + 0.2 (20 + 2x100)

= 140 nanoseconds
 Tmem = 100 nsec
 TTLB = 20 nsec
 Hit ratio is 98%
 Teffective = ?
Teffective = 0.98 (20 + 100) + 0.02 (20 + 2x100)

= 122 nanoseconds
Memory Protection
 Memory protection implemented by associating protection bit with each

page table entry
 Valid-invalid bit (v) attached to each entry in the page table:

 “valid” indicates that the associated page is in the process’ logical
address space, and is thus a legal page
 “invalid” indicates that the page is not in the process’ logical
address space
 Read, Write and Execute bits (r,w,x)
Valid (v) or Invalid (i)
Bit In A Page Table
Segmentation
 Memory-management scheme that supports user view of memory
 A program is a collection of segments

 A segment is a logical unit such as:
main program
procedure
function
method
object
local variables, global variables
common block
stack
symbol table
arrays
User’s View of a Program
Logical View of Segmentation
4
1
3 2
4
logical memory space physical memory space
Segmentation Architecture
 Logical address consists of a two tuple:
<segment-number, offset>,
 Segment table – maps two-dimensional logical addresses to physical

addresses; each table entry has:
 base – contains the starting physical address where the segments
reside in memory
 limit – specifies the length of the segment
Segmentation Hardware
Segmentation Hardware
Example of Segmentation
 Logical and Physical Addresses
 (2, 399) – PA: 4300+399 = 4699
 (4, 0) – PA: 4700+0 = 4700
 (4, 1000)  trap
 (3, 1300)  trap
 (6, 297)  trap
Segmentation Architecture
 Dynamic Storage Allocation

 First fit
 Best fit
 Worst fit
 External fragmentation
Paged Segmentation
 Divide every segment in a process into fixed size pages
 Need for a page table per segment
 CPU’s memory management unit must support both
segmentation and paging
s d
index segment
table
p d’
index page table offset within the page
p
Examples
 If there are 64 pages, and the page size is

2048 bytes, the length of logical address
is??
 A computer with physical address space of
232 bytes has the frame size of 4096 (212)
bytes. If the hexadecimal physical address
is 34567890, the frame number in
hexadecimal would be:
 In system where page size is 1024 bytes,
and the available physical memory is
equal to 218=256KB, the length of the
physical address is equal to ??
Paging Example
Example
 Consider a demand-paged virtual memory

system with a 24-bit logical address space, 8KB
page size, and 8MB of main memory. Assume
the access time for main memory is 100 ns and
the page fault service time is 10 ns. Assume the
page table is stored in main memory.
 When we split a logical address into a page number and offset
within the page, how many bits are used for the page number, and
how many bits are used for the offset?
 If no TLB is used, how long does it take for a
user program to load a byte from main memory
into a CPU register? Assume the desired page is
already in main memory.
 Suppose we add a TLB to the system to speed
up logical-to-physical address translation. With a
TLB access time of 10 ns and a TLB hit rate of
0.9, what is the effective memory access time?
Assume we only do a main-memory page table
lookup after a TLB miss, and that the desired
pages are always in main memory.
End of Chapter 8
Operating System Concepts – 8th Edition Silberschatz, Galvin and Gagne ©2009

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Chapter 8: Main Memory

 To provide a detailed description of various ways of organizing

 To discuss various memory-management techniques, including

 To provide a detailed description of the Intel Pentium, which supports

 Register access in one CPU clock (or less)

 Main memory can take many cycles

 Cache sits between main memory and CPU registers

 Very small, extremely fast, extremely

 To ensure fair, secure, orderly, and

 We can provide this protection by using two registers:

 Subdividing memory to accommodate multiple processes

 Memory needs to be allocated to ensure a reasonable supply of

 Problems with equal size fixed partitions: „

 Partitions are of variable length and number

A hole of 64K is left after loading 3 processes: not enough room

 Another hole of 96K is created.

1. Internal Fragmentation – allocated memory may

 Reduce external fragmentation by doing

 Operating system must decide which free block to allocate to a

 Scans the memory from the location of last

 Logical address: An address generated

 The set of all logical addresses generated

 The run-time mapping from logical to

 Hardware device that maps virtual to physical address

 In MMU scheme, the value in the relocation register is added to every

 Backing store – fast disk large enough to accommodate copies of all

 Divide physical memory into fixed-sized blocks, called frames

 Typical page sizes: 1K – 16K

 Keep track of all free frames

 Set up a page table to translate logical to physical addresses

 Internal fragmentation (only last page of process)

 Logical address generated by CPU is (p , d):

page number page offset

 Physical address of the location referenced by (p , d) is computed by

Before allocation After allocation

 Physical address space 2

32-byte memory and 4-byte pages

 No. of bits for p = ceiling [log2 16] bits = 4 bits

 Logical address size = |p| + |d| = 4+11 = 15 bits

 Example: if 16 bits addresses are

 What is a Logical address of relative

 32-bit linear address

 Logical address = 32-bit

 |d| = log2 4K = 12 bits

 Each page reference can cause two physical

 Given a logical address, processor examines the

Teffective = HR (TTLB + Tmem) + MR (TTLB + 2Tmem)

 Effective Access Time (EAT)

EAT = Hit_Ratio * Hit_Time + Miss_Ratio * Miss_Time

Teffective = 0.8 (20 + 100) + 0.2 (20 + 2x100)

Teffective = 0.98 (20 + 100) + 0.02 (20 + 2x100)

 Memory protection implemented by associating protection bit with each

 Valid-invalid bit (v) attached to each entry in the page table:

 Memory-management scheme that supports user view of memory

 A program is a collection of segments

logical memory space physical memory space

 Segment table – maps two-dimensional logical addresses to physical

 Dynamic Storage Allocation

 If there are 64 pages, and the page size is

 Consider a demand-paged virtual memory

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