Static CMOS Circuits

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Outline

In-depth discussion of CMOS logic families

– CMOS circuits for multiple inputs
– Data input on VTC
– Data input pattern on Delay
– Non-ratioed and Ratioed Logic

Optimizing gate metrics

– Area, Speed, Energy or Robustness

High Performance circuit-design techniques

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
 Digital Circuits

Static Circuits Dynamic Circuits

Classical Transmission
DCVSL
CMOS Gate CMOS

Domino NORA TSPC

Logic Logic Logic

Classification of CMOS Digital Circuits

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Combinational vs. Sequential Logic

Combinational Combinational
In Logic Out In Logic Out
Circuit Circuit

State

Combinational Sequential
Output = f(In) Output = f(In, Previous In)

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Static CMOS Circuits
At every point in time (except during the switching
transients) each gate output is connected to
either VDD or VSS via a low-resistance path.
The outputs of the gates assume at all times the
value of the Boolean function,
function implemented by
the circuit (ignoring, once again, the transient effects
during switching periods)
This is in contrast to the dynamic circuit class,
which relies on temporary storage of signal values
on the capacitance of high impedance circuit nodes

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Static Complementary CMOS

VDD Pull-Up Network: make a connection

from VDD to F when F(In1,In2,…InN) = 1
In1
In2 PUN
PUN PMOS transistors only
…

InN
F(In1,In2,…InN)
In1
In2 PDN NMOS transistors only
PDN
…

InN
Pull-Down Network: make a connection
from F to GND when F(In1,In2,…InN) = 0

PUN and PDN are dual logic networks

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Threshold Drops
VDD VDD
PUN
S D
VDD

D 0 → VDD S 0 → VDD - VTn

VGS
CL CL

PDN VDD → 0 VDD → |VTp|

VGS
D CL S
VDD CL

S D

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Construction of PDN
Transistors can be thought as a switch controlled by its
gate signal
NMOS switch closes when switch control input is high

A•B
A A+B
A B
B

Series = NAND Parallel = NOR

NMOS Transistors pass a “strong” 0 but a “weak” 1

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Construction of PUN
PMOS switch closes when switch control input is low.

A•B=A+ A+B=A•B
B
A
A B
B

Series = NOR Parallel = NAND

PMOS Transistors pass a “strong” 0 but a “weak” 1

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Duality of PUN and PDN

PUN and PDN are dual networks

– De Morgan’s theorems
A+B=A•B [!(A + B) = !A • !B or !(A | B) = !A & !B]

A•B=A+B [!(A • B) = !A + !B or !(A & B) = !A | !B]

 A parallel connection of transistors in the PUN

corresponds to a series connection of the PDN
 Complementary gate is naturally inverting
(NAND, NOR, AOI, OAI)
 Number of transistors for an N-input logic gate is 2N

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Example: CMOS NAND gate
VDD

A A B F
A B F
B
0 0 1
A•B
A
0 1 1
B PDN: G = A · B Conduction to GND
1 0 1
PUN: F = A + B Conduction to VDD
1 1 0
G(In1, In2, …, InN) = F(In1, In2, …, InN)

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Example: CMOS NOR gate

VDD
A A B F
F
B B

A 0 0 1

A+B 0 1 0

A B 1 0 0

1 1 0

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Complex CMOS Gate

OUT = D + A • (B + C)

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Complex CMOS Gate

B
A
C

D
OUT = D + A • (B + C)

A
D Derive PUN hierarchically
by identifying sub-nets
B C

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

VTC is Data-Dependent

3 0.5µ /0.25µ NMOS

0.75µ /0.25µ PMOS

A M3 B M4
2 A,B: 0 -> 1
B=1, A:0 -> 1
F= A • B A=1, B:0->1
D weaker
A M2 1 PUN
VGS2 = VA –VDS1 S
D Cint
B M1
VGS1 = VB S 0
0 1 2

VTC Characteristics are dependent upon the data input patterns

applied to the gate (so the noise margins are also data dependent!)

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Observation I
The difference between the blue and the
orange lines results from the state of
internal node int between the two NMOS
Devices.
The threshold voltage of M2 is higher than
M1 due to the body effect (γ),
– VSB of M2 is not zero (when VB = 0) due to the
presence of Cint
VTn1 = VTn0 and VTn2 = VTn0 + γ (√ (|2φ F| + Vint) - √ |2φ F|)

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Review: CMOS Inverter - Dynamic
VDD

tpHL = f(Rn, CL)

tpHL = 0.69 Reqn CL

Vout
CL
Rn
tpHL = 0.69 (3/4 (CL VDD)/ IDSATn )

Vin = V DD = 0.52 CL / (W/Ln k’n VDSATn )

propagation delay is determined by the time to

charge and discharge the load capacitor CL

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Review: Designing for Performance
 Reduce CL
 Increase W/L ratio of the transistor
 the most powerful and effective performance optimization
tool
 watch out for self-loading!
 Increase VDD
 only minimal improvement in performance at the cost of
increased energy dissipation
 Slope engineering - keeping signal rise and fall times smaller
than or equal to the gate propagation delays and of
approximately equal values
 good for performance and power consumption

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Switch Delay Model

A Req
Rp Rp A Rp
A B B

Rn Rp Cint
CL Rp
A A
A

Rn Rn CL Rn Rn CL
Cint
B A A B

NAND INVERTER NOR

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Input Pattern Effects on Delay
 Delay is dependent on the pattern of
inputs
Rp Rp
 Low to high transition
A B
 both inputs go low
 delay is 0.69 Rp/2 CL since two p-resistors
Rn CL are on in parallel
A  one input goes low
 delay is 0.69 Rp CL
Rn
Cint
 High to low transition
B
 both inputs go high
 delay is 0.69 2Rn CL
NAND
 Adding transistors in series (without sizing) slows
down the circuit
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
 Cross Check
3 Input Data Delay
A=B=1→0 Pattern (psec)
2.5
A=B=0→1 69
2
A=1 →0, B=1
1.5 A=1, B=0→1 62

1
A=1, B=1→0 A= 0→1, B=1 50

0.5 A=B=1→ 0 45

0 A=1, B=1→ 0 76
0 100 200 300 400
-0.5 A= 1→ 0, B=1 57

NMOS = 0.5µ m/0.25 µ m, PMOS = 0.75µ m/0.25 µ m, CL = 100 fF

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Transistor Sizing Basic

Inverter as a reference circuit

VDD Device Transconductance
(See Supplement 1)
2 kn = kn’(W/L)n = (µnε ox/tox)((W/L)n
(W/L)p kp = kp’(W/L)p = (µpε ox/tox)((W/L)p
In Out For rise time equal to fall time,

1 kp = kn (Rp = Rn)
CL
(W/L)n
Because µp ~ µn /2
(W/L)p = 2 (W/L)n
The size of PMOS must be twice as large as that of NMOS

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Transistor Sizing: NAND and NOR
Symmetric Response RPUN = RPDN

Rp Rp Rp
2 A B 2 4
B
RPUN = Rp + Rp

Rn Rp Cint
CL 4
2 A A
RPDN = Rn + Rn
Rn Rn Rn CL
2 Cint
1
B A B 1
Rp ∝ 1/(W/L)p
NAND Rn ∝ 1/(W/L)n NOR

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Note on Transistor Sizing
By assuming RPUN = RPDN, we ignores the extra
diffusion capacitance introduced by widening the
transistors.
In DSM, even larger increases in the width are
needed due to velocity saturation.
saturation
– For 2-input NANDs, the NMOS transistors
should be made 2.5 times as wide.
NAND implementation is clearly preferred over
a NOR implementation,
implementation since a PMOS stack
series is slower than an NMOS stack due to lower
carrier mobility
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Size Transistor by assuming Rp=2Rn

OUT = D + A • (B + C)

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Transistor Sizing: Complex CMOS Gate
 Red sizing assuming RPUN =
RPDN
B 8 12
A 46  Follow short path first; note
C 8 12 PMOS for C and B,4 rather than
3 (average in pull-up chain of
D 46
three = (4+4+2)/3)
 Also note structure of pull-up
A and pull-down to minimize
2
diffusion cap. at output (e.g.,
D 1 single PMOS drain connected to
B 2C 2 output)
 Green for symmetric response and for
performance (where Rp = 3Rn)
 Sizing rules of thumb: PMOS = 3 * NMOS
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Fan-In Considerations

A B C D

A CL
B C3
C C2
D C1

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Elmore Delay: Inspecting the general topology of this RC tree
network, we can make the following path definitions:
* Let Pi denote the unique path from the input node to node i,
i = 1, 2, 3, ..., N.
* Let Pij = P i ∏ P j denote the portion of the path between the
input and the node i, which is common to the path between the
input and node j.

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Fan-In Considerations

A B C D

A CL
B C3
Distributed RC model
C C2 (Elmore delay)
D C1 tpHL = 0.69 Reqn(C1+2C2+3C3+4CL)

Propagation delay deteriorates rapidly as a function of

fan-in – quadratically in the worst case.

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 Notes on Fan-In Considerations
While output capacitance makes full swing transition from VDD to 0,
internal nodes only swing from VDD-VTn to GND
C1, C2, and C3, each includes junction capacitance as well as the
gate-to-source and gate-to-drain capacitances (turned into
capacitances to ground using the Miller effect)
– For W/L of 0.5/0.25 NMOS and 0.375/0.25 PMOS, values are
on the order of 0.85 fF
CL = 3.47 fF with NO output load (all of diffusion capacitance =
intrinsic capacitance of the gate itself).
tpHL = 85 ps (simulated as 86 ps).
– The simulated worst case low-to-high delay was 106 ps.

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

tp as a Function of Fan-In

1250
quadratic
1000

750
tpHL tp
500

250
linear
0
2 4 6 8 10 12 14 16

Gates with a fan-in greater than 4 should be avoided.

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Fast Complex Gates: Design Technique 1
Transistor sizing
– as long as fan-out capacitance dominates
Progressive sizing
Distributed RC line
InN MN CL
M1 > M2 > M3 > … > MN
(the FET closest to the output
In3 M3 C3 should be the smallest)
In2 M2 C2
Can reduce delay by more
In1 M1 C1 than 20%; decreasing gains
as technology shrinks

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Fast Complex Gates: Design Technique 2
Input re-ordering
– when not all inputs arrive at the same time
critical path critical path

1 0 →1 charged
In3 M3 CL charged In1 M3 CL
In2 1 M2 C2 charged In2 1 M2 C2 discharged
In1 M1 C1 charged In3 1 M1 C1 discharged
0→1
delay determined by time delay determined by time
to discharge CL, C1 and C2 to discharge CL

Place latest arriving signal (critical path)

closest to the output can result in a speed up.
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Example: Sizing and Ordering Effects

A 3 B 3 C 3 D 3

A 44 CL = 100 fF
B 45 C3
Progressive sizing in pull-down
C 46 C2 chain gives up to a 23%
D 47
improvement.
C1
Input ordering saves 5%
critical path A – 23%
critical path D – 17%

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Fast Complex Gates: Design Technique 3
 Alternative logic structures
 Reduced fan-in results in deeper logic depth

F = ABCDEFGH

Reduction in fan-in offsets, by far, the

extra delay incurred by the NOR gate.

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

END

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956