Embedded Systems Architecture, Pragramming and Design Second Edition Raj KamalAcknowledgements um money grate my teaches: a the din Iu of Tesbneogy, Dei (1966-72) and the Univrsty of pps, Sweden (1978-79, 198), Tor eahing ne the impenance of searing and theese of Keep ‘rere techn. {would Fhe oth Pok MS Seb. FNA. for his support and blesings ioghoat my scaemic Ie ckoowedgr ny Inder coleaues -D: PC Sharma, Dr?K Chante, Dr Sajee Tolar, Mos Win Tek. Dr A “Snomt, De Maya ng. Dr Sanjay Tawar, Ms Prot Sakon, Ms Sada Masih Ms Apuma Dev, and Ms Vat G “Tearand eter nies seaman, Dr PS Grover Det). De Harvie Singh Sani (Hyderaba), De Radka SGutipauey Dr TV Gopl (Anna Uniersiy) and Dr KM Mea (Annu Univesity)—fr tc constant encourage oeiation of my efits. ar thal to heel ean t MeCeaw ill Edin nda Fortec eviews rd day tect, Lacon ne college Dr MK Sa, Hea. Conger Cre of the Universi. wh wi is ew etion she posed aay dig he as phase ofthe pregrain of his ook, Tool alo ike otha all those viewers who Took ou ie ogo tough the rit and give mete Fendbck, mame re itd belo Ramanaryan Rody sep of Computer Science ond Enginern. te Gandia of Technology He Delhi lita Folare findstan Clee of Sone end Tchelogs. Agra Akhil Kothart dep of Electonics and Conmatiation Engineering ahaa Sin Des Tait of Te: Gar priya Kear ins Isat of Engincerag and eral, imi Adina dep of Ceci oe) Commute and Ergineein ‘uta instina of Engivering we Monee Kola Pipankar Ghosh dep of Elec nd Commanicaton Engineering “Sal Ist of Teta. Roan ehashish De dep af Elecrnnics end Cominco Engineering eahnad Saha ning of Tecate: Kote Finally, F acknowledge my wife, Sisil Mtl and my Family merbecs—Shalin Mita, Necdbi Mital, De At ‘ondskar Dr hip! Konasar and Me Anh Kondaskar—for thee immense love, understanding and sopping Je wong ofthis eee eden P Kabisapathy Dep of Eleconics cn Inaramenaion Engineering, College of Enginering and Tecnology. Bhubaneswar KK Mohapatra Dept of Elecinnic. Neti nttatofTetnolos, Rowe JK Meadiratta Dept ef Electrics and Communication ond Engineering RY. Cale of Eninering.Bangaine la B Das ‘ep of Electronics Engineering National Insite of Tecan Calicut ‘Santa Kumari Dept Feces and Canvnonicaton Engineering “anv Universi, Vb V Mortidharen Dept Commuter Sconce ond Bnei. MS Rone hotioneof Toole, Banglore Josephine P Kumar Dept of Computer Science and Brine. MUI Coleg of Enginecring. Bangalore Stanley Johnson Invense Ina Pt. Lid. Cheoma ro with K Contents Prec tothe Second Edition Prac othe Fist Edition 1. Intraductin to Embedded Systems THE Embedded Systems 12 Presi Eade in 2 System 5 13 Embedded Hardware Units and Devices in Spc 10 14 Embed Soma in a Sytem 19 15 Examples of Emedod Sysem 27 16 Embed Steno chip (Se) and Use of VESI Cit Design Texhaology 29 17 Compler yes Desig al Process 12 [LF Design Process in Entel Spey 17 19 omalzaion of System Design 42 1.10 Design Proves nd Design Examples 43 LIF Clasifiton of Embeoled Systeme 52 12 Skis Reqbired orn bedded Systm Desisner 38 2. $051 and Advanced Proceso Architectures, Memory Organization and Real-world Intrtacing 2I BSI Accent 62 22 Real World nertaing 72 2.3 Inradcton to Adve Archean 214 Procesor and Memory Orpnizaian 25 racion-Level Plea 10 26 Perormance Mees 106, 2.7 Memory Types, Memory-Maps and Adress 105 2.8 Proceuor Slostion 12! 29 Memory Seen 118 5, Device and Communication Bases for Devices Network RI 1O Types and Bam 120 42 Sor Communion Devices 1 43 Parl Device Pons 14 1A SopbistsedItrtacng Fetus in Device ns 150 35. Wels Devies 15! 36 Timer nd Counting Devies 152 47 Welcog Tiree 157 38 Rel Time Cook 139 519 Networked Embed Syoms 139 310 Saial Bus Communion Protea 160 2LI Paral Bs Device role Parallel Communication Network Using ISA. PC, POLX a Advanced Buses (66 412 Inert Enabled Syren Network Prtacls 170 413. Wireless nd Motil Sytem Protocols 175 Device Drivers and Interrupts Service Mechanism ‘$1 Prgms 0 Busywcit Apeeach witout Inert Service Mechanism 189 a roxiv 42 ISR Concene 192 5 ncrpt Sources 200 413 nrg Servicing (Huang) Mechanim 203 415. Moliple Incr 209 “6 Comex and the Periads for Cote! Switching, Inter Latency and Deane 211 449 Clasiticaton of Process lnterrupt Service Mechanism frm Content Saving Angle 27 444 Drea Memory Aeces 218 49 Device Driver Programming 220 Programming Concepts and Erabeded Programming in C, + and Java 5.1 Sofware Programing in Assembly Language (ALP) sad in High-Level Lingwage “C235 5.2 C Program Elements: Header and Source File and PeporesorDietves 237 53. Program Elements: Macros and Functions 259, 514 Program Element: Data Types, Duta Stucures, Motes Sttemens Lops and Poiners 247 55 Object.Orented Programming 262 56 Embedded Programming in Cr 265, 57 Embosded Progamming in fava 261 (Program Medelinn Concepts 6.1 Progr Models 274 62 DEG Moses 277 3. Ste Machine Programming Models for Event conralled Popa Flow 282 {64 Modeling of Multiprocessor Systems 258 65 UML Modeling 295 2. Interprocess Commnication and Synchronization of Processes, Threads and Tasks LL Muliple Preset an Appicaion 05 72. Maliple Teas in am Applicaton 306 73 Tasks 308 14 Tank Sates 08 15 Tank and Data 310 “16. Cleareut Distinction teoween Farsi, ISRS and Tanks y ther Characterisies 377 17 Concept of Semaphore 314 18 Shared Dats 325 118 Inerpacese Commusicaion 230 1140 Signal Fanction 332 TN Semaphoce Functions 324 LAD Message Queue Fares 35 7113. Mailbox Functions 337 ZLIA Pipe Functions. 339 LAS Sooke: Furctions 347 716, RPC Functions 45 8. Real-Time Operating Systems 8:1 OS Services 351 82 Process Management 355 83 Timer Functions 356 8 Event Funcions 258 85 Memory Management 258 Contents ms 380 contents ‘56 Devic. Fle and 10 Subyysems Management 67 17 loterspt Roane n RTOS Environment eu Handling of reap Sas Call 1 Keattime Oporating Spwens 70 9 Basie Design Using an RTOS 372 10 Rugs Tas Scheduling Modes, tterap Latency and Resp of the Tasks Perfomance Metics 385 LIL OS Seouiy Funes OP 9. Realtime Operating System Progeamming-1: MicrogOS.I and VaWorks 91 Basic Fusions and Types of RTOSES. 408 92 RTOS mcOs-t #10 93 RTOS VaWorks 453 10. Reals Operitng System Programming: Windows CE, OSEK and Rea time ux Functions 11 Windows CE 78 102 OSEK 494 103 Linws 26.cand RTLnox 496 1H. Design Examples and Case Studies of Program Modeling and Programming with RTOS 11.1 Case Study of Embed System Design ad Cocing fo an Amati 5/2 (Chole Verding Machine (ACVM) Using Mocs RTOS 1.2 Case Stay of Digial Camers Harbrre at Solvare Arciecre 531 113 Case Sua of Coin fr Seating Appicaion Layer Byte Sueur on 3 TTCHMP Nevwork Using RTOS Vawerks 57 12. Design Examples and Cae Stes of Program Modeling and P Rros2 12.1 Case Sudy of Conmuication Betwarn Ochoa Reiss 567 123 nba Syste ia Autre 374 12.3 Cave Stay of am Embedded Stem oe an Adie Case Cantol (ACC) Sytem in Cor 377 12.4 Cae Sty ofa Embed Sytem ora Stat Cand S48 25. Cine Sly oa Mable Phone Sta or Key Iga vgramming with 13, imbedded Softare Development Process und Tuo 1.1 Insoducsion Enid Sotware Develapent Press and Tals 620, 132 Most and Target Maines 62! 15.3 Linking and Locating Solware 626 138 Going Embedded Soware ino the Target System 630 18S sues im Hrdvane-Software Design and Co-deign 34 1H. Testing, Simulation and Debugging Teetiques and Tools 1 Testing oo Hest Mashine 649 142 Simolsters 650 143 Laboratory Toole 655 Anpends I Roadmap for VariltCoe Sates Agpex2: Selec Bibigriphy Indes e 406 ” ts oss 602 63- Walkthrough TEAL ge aapveoh (| Simple way of point-wise presentation of the details by | | | ‘Summary, Keywords and thet Gelintions, review questions - and practice exercises in each chapter‘Waiktheough ‘Walkthrough l xi) x Explains modeling of programs and sokwareenginesing practices fr system design by Comprehensive explanation with coding exams for Case studies of systems fr automatic choclate vending mactine, ita camera, TOP! learn he dey used ATOSeS. mCOS, Vator, IP stack creation, abot orcosta, automatic use contol, smart caréand mobile phone ts enlace emai manteai{ opendis2: select Bil Detailed selected biography of books, journal references and important web tnks at end ofthe book ofacitate bling a startup Ivar for references and further studies in Embedded Systems Wiatktraugh Introduction to Embedded Syste a £ A R NN I N G HRRRANRS BO Sia wee OF TEeNN@LOGY UmRARY EANGALONE - S00 60, ACN, Ho. Section 1 Deftions of system and embedded system Section 1.2 The processing unit of an embeded system consists of 1. A processor 2 Canmonly used microprocessors 3. Applicationspecific intrction set processors (ASTPst ‘nicraconrllers, DSPs ard others Single purpose processors Section 1.3 The hardieare it of an embeded stem consists of 1 An embedded ‘sem poser source with esate peace ddssipaion 2 Aclack oscillator circuited clocking unit hat eta processor 3. Timers and areal me clock (RTC) or various timing needs ofthe stem 4. Rese circuit nd watchdog timer 5. System and external memories 6, System input ouput (10) ports, sera, parallel and wireless communication, serial Univeral Asynchronous Receiverand Transmiter (UART) and other port protcols ad buses 7, Devices such as Digital to Analog Converter (DAC) using Pulse With Modulation PWM), Analog to Digital Converter (ADC) Ligit Emiting Diode (LED) and Liquid Crystal Display (LCD) units, keypad and keyboard, touch screen, pulse dialer, madem and transeiver 8 Muliplexers, deruliplerers, decoder for interfacing of he devices and busesL £ A R N I 22 ° a mes & 9 trig conor (aer Seaton Ls 1 Languages tha are sed develop embeded software fora stem 2. Program modes 4, Matting using on operating sytem (08), tom device driver, device sunagemen and real tne operating stem (RTOS) 4 Sofmre tos for em design Seton 15 vaples of epplicion: of embedded sytem Seton U6 Designing on embedded stem ona VLSI chip 1 Embed SC (Sytem on Chip) and eampls of ts eplicatons 2. Uses of Application Specie Ison Set Pres (ASIP) ad Inelecual Property TP) coe 4. Fld Pregraoable Gate Array (FEGA coe wth single or maple pocesar ants onan ASIC chip section 17 The comes tem consis of 1. Embedded microprocessors or GPPs i complex ses 2 Ebeling ASIP mcrconrlers, DSPs. med an ner processors 1. Bnei appcatiom specie sem processor (ASSP 4 Enbedng ralipteprocesors in ytens section 18 The devon process has 1 Changes In embeded stem design 2 Design mers opiniation 43. Code of harvard sofware componens Section 19 The sate design forma defined Seton 110 The design of embeded harvard sofare in an awomatc chocolate vending machine smartcard dsacanera able phone. mobile compe ar ar five as examples Section Lt Classification of embeded sens ino thre res Section 112 Sls needed to dsgn an embedded sem Invoducton o Embedded Systems f J 1.1 “EMBEDDED SYSTEMS 1.4.1 System ‘Asystem is « way of working organizing or doing one or many tasks acconling oa fixed plan, program. or exof rales A system salsoan arrangement in which lls units ssemble and work together according tothe plan or program ‘Consider a watch. Iti atime-splay system. Is pars ate its hardware, needles and batery with the beautiful dial, chasis and sap. These pars organize Zo show the real ime every second and cominvously tpdate the ime every second, Te system program updates the display using three needles afer each second, follows ast of rales. Some ofthese rule area follows: () All needles move only clockwise. i A thin and Tong needle rotates every second such that it earns to same positon ater a minut. (i) A Tong needle rotates very minute such that it returns to same position after an hour, (i) A short nee ote every hour sch that ftretums to same position after twelve ours. (¥) All thee needles etum tothe same inctnation ater twelve hours each day ‘Consider a washing machine, It isan automatic clothes-vashing sytem, The important hardware parts include ils status display pane, the switches and dials for user-defined programming, 2 motor to rotate or ‘pin, its power supply and contol unit sn inner water-level sensor a solenoid valve for ling water in and nother valve fr keting water Uain out, These parts organize to wash clothes automatically according 10 & program preset by a uset. The system-program is activated to wash the diy clothes placed ina tank, which fotales oF spins in preprogrammed steps and stages. follows a set of rules. Some of these rules are as follows: ( Follow the steps strictly in the following sequence. Step I: Wash ay spinning the motor according to programmed peiod. Step I: Rinse in Fesh water after draining out the dity wate, and rinse @ second time ifthe system snot programmed in water-saving mde, Sep II: After daining out the water completely spin the motor fs fora progranimed period for ding by eentuging out water from the clothes. Sep TV: ‘Show the wash-over status bya blinking display. Sound the alam for 2 miwe to signal thatthe wash cycle is compete. (i) At each step, display the process stage ofthe system. i) In ease of an interuption, execute only the remaining part of the program, starting fom the postion when the process was interupted, There fan Beno repetition from Step Lunlss the wer resets the system by inserting anoer se of clothes ad resets the progra 4.1.2 Embedded System Definition One of the definitions of embeidd system is a follows “An embedded system isa system that has embedded sofware and conputerhardware, which wakes it «system dedicaied for an applications) or specie part of an application or product ora part ofa larger Embedded systems have been dened in books published recently in several ways. Given below isa eres of definitions fom others in the eld ‘Wayne Wolf author of Computers as Components ~ Principles of Embedded Computing System Design: “what is an embedded computing sytem? Loosely defined, iis any device that includes a programmable ‘computer bus not itself intended to be a general-purpose computer” nd “a fax machine or aclock bil rom mieroprocessor is an embedded computing system"i ex Embedded Systems. EAS: " BM author of Bnbeed Mirocontles “Embedded Sytem se eectonc sens ta aa microprocessor or microcontoller, tut we do aot think of them as computersthe compote hidden or embedded in the system.” David E. Simon author of Ar Embedded Safoware Primer: ‘any computer system hidden in ny ofthese products InP tear a an eodction tothe Design of Smal cole Embedded Stems with examples Freeney CRHCOS8 miroconroles: (I “An embedded system ks sytem whose rp function is not compu “People use the term embeded sytem to mean system, hidden from view, forming an integral pat of microconiroller-base, software driven, rela {teractve, operating on diverse physical vai and cost-conscious market" the greater whole". (2) “An embedded system is a real time control system, autonomous, or human- or network ls and in diverse environments, and sold into a competitive ‘computerisation conpnents 1" Amisepeesor 2 Auge memay eth loin to ks (Prima mean mond eis Rado Acs Mey (RAM, Rely Nee (ROM) and fast accessible caches) ae mane aes (© Sesinary meno innermost nhs, tes an cade pes ope Imeony in CD-ROMs or memory sks (in mobile compute] ising ohh dee Pans con eed ne mayen 3. vodissch sachsen meen tc 4 lp ois chase nce dias eae 5: Outpt ans sich aan LCD ses, es ra eee 6, Networking unis uch ners et, fr end aces ed set bs ive, ex 1 Av oping system (0S) th hs pene use wer sa pss a tay non ‘Anemone syst is sym ht as te min components nbd tit "Kendriya Snr aconpute Fg hw hoist eat fan embed {aiem Asta niente KOM orathmeme, teal one hadi oed CD menor as nts 2. Renbet min epteaon ts er proceso eae 3. Hembeds a realtime operating sytem (RTOS) that sp vare. The application software may concurrently perform a series of ervises the application software running on to the procties of tasks in the system, It Perea saomectanism tole the processor una process as sched and contextswich berocee he cet ae ee, Ti cone of process, tread and ask explained ner in Sections 71 te 3g Ste les rng te exestion ofthe appleaonotvae TA aac oi to ‘not embed the RTOS.) a ° Irroducton to Embedded Systoms reaones | verte Omer Crt Pons [outputs intertocinge | | | 1 _} L_Baergecse : 3 i : i Fig. 1.1 The components of embedded system hardware and evens have different rates and time istinet rates. For example, audio, vdeo, data, network steam and ie constrains (2) Complex algorithms. (3) Complex graphic user interfaces (GUIs) and other user inter (4) Dedicated functions. Constraints An embed system design ping in vw the costs: (1 arise system reno, ie peso sp) dt sitive re en Conia ee of wat Tor ven ra Op wake ad lp "he system dein or an embed ye has cnsins with ear fo perfomance power ie and (Gi) # include mah > (i) woid main (vty { (iv) in if, 2,13. a float ress (v) T= 127 (2 = 29513 = AD; a m iF + 2 + 18: ces = wort (a): (¥) pri (resul):) generates the object codes. It assembles the codes ictal || Fiat eluding ct seairg Sekar | | ecahng Sch C, Ce, Java, Visual C++ ar the languages used for software development. A C program has various layers: processor commands, main function, tsk and library funesions, nterrup service routines and kere (Gcheduler). The compiter generates an object fil. Using linker and locator, the file for the ROM image is created forthe targeted hardware, Initoducon to Embedded Systems 1 | acne A Cotesia A oc Fa z ‘Compiier | Obed Fae. | £ way | 2 i Mastin [Linker | Progam oses al |_Goses ‘Slaps an ¢ town in Fire 18 Embodied System] ROM Merry Fig. 1.8 The process of converting 2 C program into the file for ROM image 1.4.5. Program Models for Software Designing “The program desige ask i simplified if «program is modeled, “Thedfferent models tha ae employed during the design processes othe embed software areas follows 1. Sequetal Program Mode! 2 Object Oriented Program Model 3. Control and Data lw graph or Synchroncus Data Flow (SDF Grapor Muli Thread Graph (MTG) Moet 4. Finite State Machine for datapath 5. Multithreaded Model for concurrent processing of processes ar tread or asks UML. (Universal Modeling language) isa modeling language lor object oriented programming. “These models ae explained Chapter 6 1.4 Software for Concurrent Processing and Scheduling of Multiple ‘Tasks and ISRs Using an RTOS ‘An embuilded system program is most often designed using multiple processes or multitasks or 3 tmultitheads. [Refer to Sections 7.1 to 7.3 for definitions and understanding of the processes, threads and tasks | “The molipl tusks ae processed most often by the OS na sequentially bt concurently. Concurent processing tasks ean be interrupted for running the ISRs, snd higher priority tsk preempt the running of lower priority tasks. 'An OS provides for process, memory, devices, 10s and file system management. A filesystem specifies the ways in which a file is erated, called, named, used, copied, saved of deleted, opened and closed, File system i the software fr using to files ona disk, ash memory, memory card or memory tek. (0S software have scheduling functions forall the processes (asks, ISRS and device drivers) inthe system. Since the runing of the tasks and ISRs may have realtime consrsnis and deans or nishing the tasks, an RTOS is required in an embedded system. The RTOS provides the OS functiogs for coding the system, provides interpocess communication funetiqas anyacontols the passing of messages and signals to task [RTOS funetions ae highly complex. There ae a numberof popular and rea Chapters # to 12 desribes the RTOS functions and examples of applications available RTOSS, the embedded syste,[2] Embedded Systems eg RTOS is wed in most embedded systems and the system dees concurrent processing of multiple ‘when he tess have eal ime constrains and deaine 1.4.7 Software for Device Drivers and Device Management in an Operating System Am embse system is designed to perform muitpie functions snd has to control mutiple physical end ‘nul devices. nan embeddedsystem, here may be numer of phsicul devices, Exemplary physical devices ae timer, keyboarus, display, ash meme, parallel por nd wetwuek cards ‘A program is ako be developed using the concept of virtual devices. Examples of veal deviees areas Fallows 1. A ile (of revords opened, ead, written and closed, and saved as a siceam of bytes or words) 2. A pie for sending nd recevirg a seeam of bytes fom a sauce Wo destination) 3. A socket (for sending and receiving a stream of bytes belwoen the client and server software and between souce and destination computing systems) 4. A RAM sk for sing the RAM in a way simile t files the disk) A fileisa data structure (or vital device) which sends the econ characters or words) ta daa sink (Kor ‘example. prmgram neon and which tees the data From the data source fi example. program Function Alena computer may also be stoce in the hard disk ain Mash memory in embeded system, ‘Theterm vitual device fllows from the analogy tha usta keyboard zives an input to the processor for 4 read, a le aso gives an input to the processe. The peacessor gives an output 10 a printer for a write Similar, the procesr writes an output the ile A device fr the purpase of conto. handling. eating and writing three components) A contol registro word thal stores the bits that, on setting or resting by a device ‘diver, conta device ations. Gi A status register worl hat prvi the flags (its) to sy the device situs othe device diver (i) A deviee mechani that controls the deve ations. There my be input an ‘utp data bles ina device, which may be writen or read by device driver Deviee driver aeons are to J, input data balers, utp data buffers and status setions ean be taken as consisting of 25 inp oF send pas fom the conte er f the devin ‘A devie ever is sftware for opening, connecting or binding eaing, writing and cling or controlling sections ofthe device Is software writen in high level language. Ht contas functions for device open (configure), connet bin listen, read or write or else. The device driver executes ltr the program the con regiter (or we) of peripheral or viral device. The programming i called device initialisation (registration or attachment. The diver rads the status regis, ets the imps and writes the outputs. I ‘executes onan interrupt oor from te device. A driver controls tee functions. ()Intalining, which is sctivated by placing appropiate bts atthe control register or word. (i) Calling an ISR on interupt or on sting status fag in the status register a unig (riving) the I (nterupt Handler Routine). i) Reseting the stats ia aller an interrupt service. ‘diver may be designed for asyctwonous operations (multiple use by task one after smother) or synchronous ‘operations (concurrent use by the tsk). Using’heifltion ofthe OS, a device diver coding ear be made sch that the underyng hardware ix hidden as much as possible. An API then defines the hardware separately. This makes the driver usable when the device hardware changes in a system, eee fs A device driver aeceses a parallel or serial port, keyboard, mice, disk. nctwork display. ile, pipe and sweket at specific addrewes. An OS als provides device driver cok for ystem-port arses and for hardware acess mechanisms, ‘A device manager software provide codes fr deleting the presence of devices for niialring these and for testing the devices tha are present. The manager includes software For allocating and registering pet (in Fac it may be a register ar memory) addreses for te various devices at distin diferent adresses, neloing, tenes for detecting any collision between these i any. I ensures tha any device acesses to ome task oly it rn instant I takes into account that virtual devices may also ave akreses tht are alocated by the manager. ‘An OS alo provides and executes movil for managing devices that associate with an embedded system. ‘The underlying principe is tha at an instant, only one physical or viral device should get accesso oF from cone tsk only Sections $24 and 8.6.1 will describe device drivers and device management in detail. The OS alo provides and manages viwal device such as pipes and sockets. Sections 7.14 and 7.15 deveibe these in deuil For designing embedded-softwar, two types of devices are considered: physical and virwal. Physical eviews include Keypad, printer ce display unit. A vial device could bea leo pipe or socket oc RAM tisk, Device drivers and device manage software ae needed inthe system, The RTOS includes devic- drivers and a device manager to contol and facilitates the use ofthe number of physical and viral ] li | | PROGRAM | ! bata | (CONTROLLER L AND PORT i i | | Fig. 1.10 ASoC embeded system andits common bus withinternal ASPs, internal processors, IPs, shared memories and peripheral interfaces Introduction to Embedded Systems 31 1.6.1 Application Specific IC (ASIC) ‘ASICs designed using the VLSI design tots with he processor GPP or ASIP and analog circuits embedded jm the design, The designing is done using the Electronic Design Automation (EDA) too. [For design of an [ASIC, a High-level Design Language (HDL) i wed, 1.6.2 IP Core (On 2 VLSI chip, there may be integration of high-level components. These components possess sate-level sophistication in cteuits above that ofthe counter, register, multiplies, floating point operation unit tnd ALU. A standard souce solution for syathesizing a higher-level component by configuring an FPGA ‘ore or a core of VLSI circuit may be available as an Intellectual Propery. called (IP). The designer or the ‘esigning company hols the copyright forthe symthesized design ofa higher-level component fo gatelevel implementation of an IP. One might have to pay royalty fr every chip shipped. An embedded system may inconporate several IP. + Am IP may provide hardwired implementable design of a ansform, an encryption algorithm or 3 decinhering algorithm, + Am IP may provide a design For adprive filtering ofa signal + Am IP may provide a design foc implementing Hyper Test Transfer Protocol (HTTP) or File Transfer Protocol (FTP) or Bluetooth protocol to transmit a web page ora file on the Internet + Am IP may be designed fora USB or PCI bus controller. [Sections 3.103 and 3.12.2] 1.6.3 FPGA Core with Single or Multiple Processors ‘Suppose an embedded system is designed with @ view to enhancing functionalities in future. An FPGA ‘cores then used inthe circuits. Kt consists of large numberof programmable gates on a VLSI chip. There is ‘asetof gates ineach FPGA cel called mero cl. Esch cell as several inputs and outputs. All cells iteconnect, Tike an aray (matrix). Each interconnection is programmable through the associated RAM in an FPGA ‘programming tool. An FPGA core can be used with single or multiple proceso. Consider the algorithms for the following: Fourier transform (FT) and its inverse (IFT), DFT or Laplace ‘transform and itsinverse, compression or decompression, eneryptingo: deciphering specific pater recognition {or recognizing a signature o finger print or DNA sequence). We can configure a algorithm int the logic fates of FPGA. It gives hardwired implementation or a processing unit I is specific © the need ofthe embedded system. An algorithm ofthe embedded software can implement in one ofthe FPGA sections and another algorithm in its other section. FPGA cores witha single or muliple processor units n chip are used. One example of such core is Xiling Vinex-ll Pro FPGA XC2VPI25. XC2VPI25 from Xilinx has 125136 Topi cells in he FPGA core ‘with four IBM PowerPCS. Ic has been used as a data security solation with encryption engine and data rate (of 1.5 Gbps. Other examples of embedded systems integrated with logic FPGA. arays are DSP-enabled, realtime video processing systems and line echo eliminators for the Public Switched Teleeommnication [Networks (PSTN) and packet switched networks, [A packet is @ nit of a message or a flowing data such that t can follow a programmable route among the number of optional open routes available at an instance.)Embedded Systems 1.7 ~ COMPLEX SYSTEMS DESIGN AND PROCESSORS 1.7.1 Embedding a Microprocessor A General Purpose Processor microprocessor can be embedded on & streams of mieroprocessors embedded ina complex system design, I chip, Table 1. list different Table 1.4 Important microprocessors used in embedded systems ————— ‘Seam “Microprocessor Faris Somer (CISC oF RISC oF Bath fetus Seam | esHeux Motorola cise swan 2 x86 case Seeam 3 SPARC sun Sean ARM ARM 1.7.2. Embedding a Microcontroller Microcontolle: VLSI cores or chips for embeded systems are usually among the five steams of families siven in Table 1.5 Table 1.5 Major microcontrollers® used in the embedded systems Seam iron ; Sone GiCor AC ban Svea! 6SHCHxx, HCI2e, HCI6x Motors asc | siveam 28051. s051Bx niet, Philips cis | sem} IC IEA CH, I6FTG and ICIS Mistp owe RISC Cove with CISC funconaity | Steam 4" aticroconrolles Enhancements of CORTEX-M3 ARM, Texas. Philp. | ARMS/ARM? from Philips, Semsung and Samsung and St ST Microelectronics Microelecooes ete ® cx pop icrcons area allows (Hise and Super Tet. Gi) Misi 70,700, MgC a 1M92C amis. (i) National Semiconductor COPS and CRI6 15: iv) Teshita TLCS SS (Tent sven MSP 490 for low oagebatery beter) Seung SAM, (vi Zils 290 e280, 1.7.3 Embedding a DSP ‘A digital signal processor (DSP) isa processor core ot chip forthe applications that process digital signals [For example, filtering, noise cancelation, echo elminatia, compression and encryption applications Just as 8 microprocessor isthe most essential unit of a computing system, & DSP is essential unit of en embedded Intoducton » Embedded Systoms [33] _syslem ina luge numberof applications needing processing of signals. Exemplary applications ae in image processing, multimedia, io, video, HDT, DSP modem and teleommunicaion processing systems, DSPs fs il use in systems for ecognizing image pattern or DNA sequence [DSP as an ASIP isa single chip or core ina VLSI unit includes the computational capabilites of @ pencessor and Multiply and Accumulate (MAC) units. A typical MAC has a 16 32 MAC unit [DSP executes dseretestime, signal-processing insructions. I has Very Large Instruction Word (VLIW) processing capailitis: processes Single Insivction Multiple Dia (SIMD instructions it processes Discrete Cosine Transformations (DCT) and inverse DCT (IDCT) functions. The lauer re used in algorithms for signal analyzing, coding. tering. noise cancellation, ho elimination, comyyessing and dccompressng, ee Major DSPs for embedded systems are from the tree seams given in Table 16, Table 1.6 Important digital signal processor® used in the embedded systems Sesan ‘se Fans Source Seam 1 "Tws320Cxx, OMAP! Texas Sxeam 2 ‘Tigee SHARC Analog Devoe Siren 3 0a Moto Seam 4 PNK 1300, 1500? Philips ‘example, TMSS200G2XX a Fae pin 200 Miz DSP Section 235, 2h roe which ies ida DSP operas odes eon Se 1.7.4 Embedding an RISC A RISC microprocessor provides the speedy processing of instuctions. each ina single clock-eyte, This Facilitates pipelining and superscalar processing. Besides greaily enhanced capabilities mentioned above. thre is grel enhancement of speed by which a insrueton fron sets processed. Thunb” instruction set isa new industry standard thal also gives a reduced coe density in ARM RISC processor RISCs ar used when the system needs to perform intensive computation. or example. ina speech processing sytem, 1.7.5 Embedding an ASIP ASIP isa procesor with an instucton set designed for specific application areas on a VLSI chip or core {ASIPexainples ae microcontroller, DSP, 10, medi, network or ather domain-specific processor Using VLSI design tools. an ASIP with instructions ses required inthe specific aplication areas can be designed, The ASIP is programmed using the insrctions of te following fupetios: DSP, cont! signals processing. discrete cosine transformations. apie fiterng wel comniation pretaca-mplementing functions. 1.7.6 Embedding a Multiprocessor or Dual Core Using GPPs In an embedded system, several processors or dual core processors may be needed to execute an algorithm fast within a strict deadline, For example, in reabtime video processing, the number of MAC ‘operations needed per second may be moce than is possible from one DSP unit. An embedded system {then incorporatgs two oF more processors running in synchronization, An example of using moltple ASIP is high-definiion television signals processing. [High definition means thatthe signals are processed for a nose-fee, echo cancelled transmission, and for obtaining a at high-resolution image (1920 x 1020 pixels) onthe television screen] A cell phone or digital camera i another application with multiple ASIP. processing.34 Embedded Systems Ina cell phone, a number of tasks have to be performed: (a) Speech signal-compression and coding. (b} Dialing (¢) Modulating and Teansmiting (d) Demodalating and Receiving (e) Signal decoding snd decompression (P) Keypad imertace and display imtrtace handling) Shon Messe Service SMS) peotocal- based messaging (hy SMS message display. For all these tasks a sirgle processor does not suffice. Suitably synchronized multiple processors are used ‘Consider a video conferencing system. In ths system, a quarter commen intermediate format—Quarer- (CIF—is used. The numberof image pixels i jus 14 x 176 as aginst 525 x 625 pixels ina video picture on ‘TV. Even then, samples of the image have tobe taken at ate of 144 x 176 x 30 = 760320 pixels pr second and have to be processed by compression before transmission on a telecommunicaton or Viral Private [Network (VPN). [Note:The numberof frames are 25 or 30 per second (as per te stand udopted) fr real- time displays and in motion pictures. | A single DSP-based embeded system does ot suis to get real-time images during video conferencing. Real-time video processing and multimedia applications mes often need ‘multiprocessor unin the embedded system ‘Multiple processors or dual core processors are used when a single microprocessor does not meet fhe needs of the different asks that execute concurenly. The operations of ll he processors are synchronized to obtain optimum performance. 1.7.7 Embedded Processor/Embedded Microcontroller Anembedded processor isa processor with special features that allow it to embed nlp processes into the system, Realtime image processing and aerodynamics ae two areas where fast, pecise and intensive calculations and fast context switching (from one program to another) are essential, Embedded processor is the term sometimes used for processor that has been a specially designed such that it has the Following capabiliies 1. Fast context switching and thus lower latencies ofthe tasks in Complex real time applications [Section 4.6} Fest context switching means ha the clling program or interpted service rouse CPU resisters save and retrieve fast [Section 46 2 32-bit oF 64-bit atomic addition and muliplcstion, and no shared data problem in the operations with large operands with each operand placed ia two or four registers. [Section 7.8.1] 3. ARIE RISC core for fast, more precise and intensive calculations by the entbeded software, Embedded microconiller isthe term sometimes used for specially designed microcontrollers that have the following capabttes: |. When a microconeoller has intemal RAM, large Mash or ROM, timer, interupt handler, devices end peripherals and here is no external memory or device or peripheral ried forthe given application. 2. Fast context switching and thus lower latencies ofthe tasks in complex eeal ine applications. For example, ARM and 68HCIx microcontrollers save all CPU registers fast ‘Am embeded processors term used for processors with Fast processing, fst context-swtching and atomic ALU operations. An embedded microcontroller is the term used for microconeller that has interul RAM, lage flash or ROM, timer, interrupt handler, internsl devices and intemal peripherals an there is 10 extemal memory or device or peripheral requied fr the given application Inzoducion to Ered Sysoms [3s Complex System Embedded Processors Table 17 gives cfecentprocessrs tht cun embed in & complex system, Table 1.7 Processors in complex embedded systems eaten "aavonage Disaivamage Proceso Generel Purpose When intensive NNowngincuing es for Adio! redundant Microprocessor oman we esgring he procesor execution wis that ae reed, aces we used ot need in he sven ‘nd pple and ‘sem design perc options tue edad and ge ‘meddle 10 be oct in the exter memory exes hips Microcontroler sod with itera No engineering cos for Adina) rien devices and designing the processor manufacturing cos and evita and when wit inlral memory, eduodatsplicaton Combed sofware iso devices and penpherals, unis which are no, te oct in he itera eeded inte sven | ROM oh fate devin | ose sed wit sige No cngincering cost Manufacturing co may procesingreled Involved for designing be high | Inetwctons for fers, the signal precessoe ' image, si, and ideo | ‘and CODEC operations. Single purpose ‘Consol 10 and bos They support oer In-house enginceing proceso and peat’ ae proving unis inthe eos of developmen, royalty pyment for an IB or of procesor and timoso-market con ‘pplication specific Pripterasand devices. Sytem and exerte [se procesor specific halware| I proasses fas Manufacturing cost as | Duat core processor Tosigrifcantyenance Reduced engineing | Reema cal woene potions — cay cero Toast tote prey ‘Eagenig att Ree, pmctagwinas” seein apt fone pt mine meee? oet creosote Pera tae ‘nae opesions ake cost. fd Joa aceon ‘Rodents lav ene |36 Emoedded Systems ADDSP for motile phones. for example. OMAP of Texas Instruments, uses he efective power dsipation methods of dynamic switching box fr poser supply voltage and operating frequency othe CPL’ cone For » number of upplcitins the DSPs cores may not sfice. Darmin specific ASIPS ave specific insructon ses. For 10s. network. media or security applications, smart card, videogame, palim tp computer, cellphone, mobie- Inert hand-held embedded systems, Gbps transceivers, Gbps LAN systems, satellite of missle systems, we need special processing units in a VLSI circuit designed to function a a procor with an insruction-set fr programmability. These special units are called domain-specific ASIP, 1.7.8 Embedding ARM processor Examples of Seam 4 GPPS in Table 1 are ARM 7 and ARM 9. The core ofthese processors ean be embeded onto a VLSI chip or an SoC. An ARM-processor VLSLarcitecture is avaiable ethers CPU. chip or for integrating it into VLSI or SoC. ARM, Intel and Texas Instruments and several ether companies have developed such processors. ARM provides CISC futionality with RISC architecture at he core. The ores of ARM7. ARMY and their DSP enhancements ae available for embedding in systems. [Refer to hip? \wwticomse!doesfasic/modulslam?.Atm and am htm, ARM integrates with other features (for example DSP) in new GPP, which are available from several sources, for example, Intel and Texas Instrument. Exemplary ARM 9 applications are setup boxes. cable modems, and wirelessdvices sich as mobile handsets, ARM has a single eycle 16 x.32 multiple accumulate unit. W operates at 200 MHz. It uses 0.13 ys GS30 °MOSs.Ithasa ive-stage pipeline, It incomporates RISC core with CISC functions [cinegrates wil » DSP shen designed for an ASIC solution. An example i its integration with DSP is TMS320C35 from Texas instruments [Refer to hip:/www.i.convseidocs/sschmdulesart7 hand arm] ‘Mower performance but very popula version of ARMY is ARM7. It opertes at 80 MH. I uses 0.18 jm based GS20 tim CMOS. Using ARM7, ARM9 aed CORTEX-MB, a large number of embedded systems have recently become available Lately, 2 new lass oF embedded systems has emerzed that aditicnally incorporates ASSP chips or cores in ts design 1.7.9 Embedding ASSP ‘Assume that there is an embedded system for real-time video processing. Redl-time processing arise for ligtal television, high definition TV decoders, set-up boxes, DVD (Digital Video Dive) players. web phones. video-conferencing and other sysems. An ASSP that i dedicated to these sprcific tasks alone provides faster solution. The ASSP is configured and interfaced with the rest ofthe embedded system, Assume thal there isan embedded system thar using a specifie protocol interconnects it units through specific bus architecture to another system, Also, assume that suitable encryption and decryption is required {The outpu bitstream encryption protects messages or design fom passing to an unknown external entity} For these tasks, besides embedding the software, it may aleo be necessary to embed some RTOS features [Section 1.4.6}. I the software alone is used forthe above tasks, i may tke a longer time than hardwired Solution for apliation-speifie processing. An ASSP chip provides such a solton. For example, an ASSP hip from i2Chip (hp ww i2Chip.com)} has a TCP, UDP. IP, ARP and Ethernet 10/100 MAC (Media Access Control) hardwired logic included ino it. The chip from i2Chip, W3100A, is «unique handwvied internet coneetvity solution, Much needed TCPAP stack processing software for networking tasks i thus avaloble as -@ hardwired Solution, This gives output five times fester than a software soltion using the system's GPP. I is also an RTOS-Ies solution, Using the sme microcontroller inthe embedded stem to which his ASSP chip Introduction 19 Embedded Systems (37) imerfaces, Ethernet connectivity con be kde. Another ASSP. which is now avilable. she “Sera-W-Ethort Converter (IIM710(. I des realtime da processing by a hardware protocol stack, Hence change im he pplication software or fmvare sexi provides the most economical and mallet RTOS-solation, ‘An ASSPis used as an addtional processing unit for running application specifi asks in place of processing using embedded software "1.8 DESIGN PROCESS IN EMBEDDED SYSTEM “The concepts used during 2 design process are 2 follows 1. Abstraction: Each problem component i ist abstracted, Fo example. inthe design ofa robotic Sem, the problem of abstract ean Be in ers of contol of arms and moors. 2. Hardware and Software architecture: Architectures shouldbe well understood befor a design. 3. Extro functional Properties: Ex functionals required in the system being developed should be well understod frm the design 4. System Related Family of designs: Families of related systems developed eater should be taken ino considerzion ing designing 5. Modutar Design: Modular design concepts should be used. System designing is fas by decomposition of software into modules hat ae tobe implemented, Modules shouldbe sch tha they ‘an be composed (coupled or imtgrated) later. Etfctve modular design should ensure effective (i) function independence. (i) cohesion and Gi) coupling, (@) Modules shouldbe clearly undestod and should maintain continuity (b) Ako, appropri protection sateies ate necessary foreach module. A modules nt permited to change o madly another mole neionaliy For example, paecton Ion device driver modifying the configuration of another device 6. Mapping: Mapping ito various representations is done from software requirements. For example, dufovin fe ancy eng page flcatcmpegter aan ety Term an censaction mapping design processes are wed in designing. Fv example. ina snp ta to spt can hav der nanbe pls clus, The spe dos no proc cach Pixel and colour indvidoaly. Transom mapping of image is dene by appropiate compression and Norage algorithms. Transetion mapping ix done to deine the sequence of images. 1. User interface Design: Usenet desig san ipevtan prof design Usernerfaceste designed a5 per user requirements, analysis othe envionment and system futons. For example, nan automatic chocolate vering machine ACM) sytem, te user inerface isan LCD mln graphs dispay. can display a welcome messge 2 well ws speify the coins needed tobe ised into the machine Fo cach type of chocolat. The same ACYM may be designed with ouchsreen User nerface (GUT), oF it ‘may be Gesigned with Voice User Imerfaces(VUIs). Any theseimerace designs has be validated by thecustomer,Forexample the ACVM customer who installs emachine must validate message language and messages be displayed before an interface desi can poczed oie implementation Sage. 8. Refinements: Each component and module design need tobe refined erative tlt becomes the ‘most appropiate for implementation by the sofware team. mim “The software design process may require use of Architecture Description Language (ADL). Its used for representing the following: () Contol Hierarchy (i) StrctalPartioning (i) Data Structure and Hierarchy (i) Software Procedures.(=) Figure I-11 shows the activities for software-design cycle during an embedded software development Embedded Systems process and the cycle may be repeated bil less show the verification of specifications. Development oo Anaiyes| 1 | | | il omascrse || ow [Le & | j i, | | Ilr | || | ke eel a /~\ [ee] es

a Fig. 1.11 Activities for software design during an embedded software-development process 1.8.1 Design Metrics ‘A design process akesito account design mews. There ar several design mestcs for an embedded system, nd these are listed in Table 1.3 1.8.2 Abstraction of Steps in the Design Process {A design process i called botom4o-top design i it builds by starting from the cormponents. A design process 1 called top-to-down design if it first starts with abstraction of the process and then after abstraction the details are created. Topto-down design approach isthe most favoured approach. The following lists the five levels of abstraction from top to botom inthe design process: Design Mei Power Disipaion | reformance Proces deadlines Emgincerng cost Manufacturing cast Hsiitiy | preter evelopment ime Time-to-marke System and wser safe | Moinrnance Invoducton to Embedded Systems Table L8 Design metrics used in the embedded systems —_—— Deseripion For many systems, paca baery operated syste, suchas mobile pone o digital ‘ama the power consmed by the system i an important fxr. The batery aed to be recharged les fequety if power dissipation is small Instone exeetion ine ia the system measures the perfomance. Smaller exeeton| time means higher peformence. For exile, 4 mile pore vice signals processed between antenna and speaker in O.s shows pone perfomance. Consider another. For frample, 4 igs camers, shooting 4 4M pac sil image in Os shows the camera performance. Thee are numberof processes ia the syste, fr example, keypad input processing. graphic isla etesh oto signal processing and video sera processing. Ths ave deadlines ‘iin which each of them may Be eqired 0 fsh computations ard give resus ‘hes nce keypad GUIs and VU Sie ofthe system is meseured in terms of (phys! space reuied,Gi) RAM in KB and internal flash memory requirements fn MB of GB fr eaaring the software and for dat Storage and i umber of millon lope gle io be hada. Int cost of developing, debugging and testing the hardware and sofware sealed ceinering cos and onetime ecg cos. (Cost of manufacturing cach nit Fesiblity in design enables, witout any significant engineering cot development of| Gieret version of» product and advanced versions later on. For example, sofware fntancenedt by adding entra fonction necessiated by changing enviroment and software reenginesing. time taken in ays or months fr developing the prottype ad nous esting for sstem funcinlites I inclads engineering ime and maklag he prototype ine “Time taken in days or months afer protorype development to put a product or wets and Sysem safety in terms of cel fl from hand or able, the (ea phooe loking bly and tracing bi) and ia terns of user safety when sing a product (or example, utomobile Brake or ego). Maintenance means anges and abtons te system: for example, dingo oping softwar ita and harewre. Example of software rience i oa see or functionality software. Example of datz maintenance is addons Angi, wallpapers, ‘ideo ips in ob phone of extnting card expiry dt a cse of smartcard ample of arate mainfenanosisaddlonl memory o changing the memory sick nail computer sd digital camera (1) Requirements: Definition and analysis of sytem requirement, Is only by 2 complete clarity of the equred purpose, inputs. outputs, uncioning, design metrics (Table 18) and validation requiremen's for finally developed systems specifications that well designed sytem canbe crested. Tere has to be consistency in the equiremedts.40 Emboddod Systems (2) Specifications: Clear specifications ofthe cequzed system are sunt. Specifications ace «be precise. Specifications guide customer expectatwns from the product. They also guide system architecture. The designer needs specitiatons fr i) hardware, for extmple, peripherals. devices processor and memory specification, i) dat types and processing specications, ii) expecte system ‘behaviour specifications iv) constrains of design, and («expected hie eyele specifications. Press specifications are analysed by making sso inputs on eves outputs on cventsand how the processes activate on each event (inept). (G) Architecture: Data modeling designs of atibutes of dala structure, data ow graphs (Section 62), program models (Section 6.1), software architecture layers and hatUware architecture are defined Software architectural layers areas follows 1. The first layer isan architectural design. Mere, a desig for system architecture is developed. The question arises a8 to how the different elements—data structures, databases, algorithms, contol functions, state transition funtion, proces, dala and program flow-—are to be organised 2. ‘The second layer consists of data-dsign. Questions «this stage areas follows. What desig of data structures and databases would be most appropiate forthe given problem? Whether data organised asa tee ike sruture will ke appropiate? What wil be the design ofthe components in the data? [For example, video information wil have two compenens, image and sound 3. ‘The third layer consists of imerface design Important questions at this tage areas follows. Wht shall be the interfaces to integrate the components? What isthe design fec sytem intreation? ‘What shall be design of interfaces wsed for taking inputs Fom the data objec, stetures and databases and for delivering outputs? What willbe the port structure for eecevirg inputs and transmitting outputs? Components: The foun tayer sa component level design. The question a this stage isa ftaws, ‘What sal be the design ofach component? Thee national requicement inthe design of embeded system, thateach component shouldbe optimised lor memory usige and poser dissipation, Components of hardware, processes, interfaces and algorithms, The following iss the common hardware compenents 1. Processor, ASIP and single purpose procesors in te system 2. Memory RAM, ROM or intemal and externa sh or secondary memory inthe system 3. Peripherals and devices internal and exter othe system 4. Ports and buses inthe system 5. Power source o battery inthe system During software development proorss we can model the components a object-oriented, Table 1. list the stages as component-based objesoriented software development process (5) System Integration: Built components are integrated in the system, Components may work fine independently, but when integrated tay nt fulfil the design mets, The system is made o function and validated. Appropriate ests ae chosen, Debugging tools are used to corect eroneous functioning, Each component and is interface system integrated after te design stage. Program implementation in «language and may use an integrated developmen envionment (IDE), and source code engineering tos, Which shoul follow the model, software architecture and design specifications. Prograin simplicity should tbe maintained during the implementation process. « ‘The design stages range from abstrtion A» detiled designing to verification activites. Continuous ‘refinement in design can be made by effective communication between designers and implementers. Soflvare design can be assumed to consist of four layers: architecture design, dala design, interfaces design and ‘component level design. lnvodton Embedded Syste («) Table 1.9 Components-based object-oriented software development process ‘Actes ior Model Deficiency Suge | Component tht could be wed in software development identi Suge? Selection of availabe clases (single logically bonded 70098) OM Ke or bust nxn sottare component rier ary eee Sips} Sertcomponets, wich ar avalable and eusable by re-engvcering and case the ele eich ae onsale components ae at avaiable in regu Stage 4 Re-ngincer components and crete ueavalbe components weit Stage S Couset software fom te components and tes them | sa lee Actions at each step Research by software engineering experts have shown that on an average, a designer needs to spend about 50% of the time for planning analysis and design, 40% for testing, validation and debugging and 10-15% on coding. Action required tobe taken a each step inthe design process sisted in Table 1.10 6 eave conte il fl validation of software Table 1.10 Action to be taken at each step of design process ‘Benga Wate Desripion Anatyis, Design i arly “The ces of sali i aed to improve design to moet specications and mets Step for improvement Verification Sysem design must be veiedw ena that mets the design mts gven in Table 1.8 1.8.3 Challenges in Embedded System Design: Optimizing Design Metrics Following are he challenges tha arse during the design process. Amount and type of hardware needed: Optimizing the requirement of microprocessors, ASIPS und single purpose processors in the system on the bass of performance, power dissipation cost and other design metres are the challenges ina system design. A designer also chooses the appropriste hardware (meniory RAM, ROM or internal and extra flash o secondary menor. peripherals and devices intemal and external ports and buses and power source or battery) taking into account the design metrics given in Table 1.8: for ‘example, power dissipation, physical size, number of gates and the engnecring, provtype development und manufacturing costs ‘Optimizing Power Dissipation and Consummpion: Power, consumption ding the eperaionl and ile sate of system shouldbe optimal. The following metheds are used to meet the design challenges, Clock Rate Reduction Power disipation typically reves 2.5 pW per 100 kz of reduce tock rate So reduction from 8000 kHz to 100 kHz reduces power dissipation by about 200 IW, which ic nary similar to-when the clock is nonfunctional. (Remember, total power dissipated (energy required) may not reduce. This is because on ducing the clock rate, the computations will ake alongs tme nd total energy required equals the power dissipation per second multiplied by computation ine}fa] Emboted Systems bad Te power25 Wt typical te esl dspaton ded o pea ins nd few ter ais By psa eck a ler fetency odin the powerdown noth pcs th drapes Sra) Power rd teat genre de) Kai gue nlc oes {beveled owe sion wine ats Wadatd RF (Rade Fcc) power defends on he RF Sone ne gn ih ede oe ona in“ON" stress vee asa neo SENMOSPET uanior and Oat ede eat goraion Voltage Reduction Inportable or hand-heddevics such as acellular phone, comparedto 5 V operation, ‘aCMOS ercuit power dissipation reduces by one sath, ~(2V/SV},in2.0 V operation. Thusthe time intsvals reeded for recharging the batlery increase by afactor of six. Wait, Stop and Cache Disable Instructicns An embedded syste may ned tobe run continuously, ‘without being switched ofthe sytem design, Uerefoe, is constrained by the need to limit power dissipation ‘while itis ON but sin idle state. Total power consumption by the system while in eunning, waiting and ile states should be limited. A microcontoller must provide for executing Wait and Stop instructions forthe power down mode. One way to reduce power dissipation ito cleverly incorporate into software the Wait and Sop instrtions. Another i to operate the sytem at the lowest voltage levels inthe ile state and selecting, power down mode in that state. Yet another method ito disable use of ein structural Units ofthe processor for example, caches—when not necessary and to keepin disconnected sate those structure units that are not needed during «particular software execution, fr example timers or 10 units. Operations canbe perfrmed at low volage of educed clock rate in order to contol power dissipation. For ‘ebeded system software, performance analysis during its design phase must ala inclode the analysis of power dissipation during program execution and during standby. An embedled system has to perform tasks continuously From power up to power-off and may even be kept “ON” continuously. Clever eal-time ‘programing by using "Wait and ‘Stop insirections and disabling certain units when not neded is cme ‘met of saving power during program execttion Process Deadlines Meeting the deadline of all processes in the system while keeping the memory, power dissipation, processor clock rate and cost at minimum is a challenge Flexibility and Upgrade ability Flexibility and uperede ability in design while Keeping the cost ‘minim and without any significant engineering cos isa challenge. Flexibility and upgrade sbiity slow different and advanced versions ofa product ote inroduced in the market later on Reliability Designing a relble product by appropriate design, testing and thorough verifeation is ctallege. Te goal of testing is to find eros and o validate that the implemented software sas pr the Specifcion and eqiement Verification fest an activity to ensure pei function ae eorecty ‘mpeneated.Vaaton refers to an activity wo ene tha the system hat hasbeen created is a per the requirement ageed upon tthe analysis phase, an to ensure is ait. “1.9 “FORMALIZATION OF SYSTEM DESIGN Farmalizaton of system design i done using a top-down approach by abstraction (Section 1.82) and by + Detling equirements and specifications of hardware and software Introduction to Embedded Systoms ‘+ Dotining architectures of hardware and software + Covdmg and impemsntaton a per architocture {Testing validation and verification of system Since a diagrammatic mode! clears the design conceps beter than abstraction, 2 modeling language, foc formalization ean be used, The Universal Modeling Language (UML) is used. In UML. a designer deveribes the following 1. "User Diagram’, “Object Diagram’, ‘Sequence Diagram, ‘State Diagram’. “Class Diagram and “Activity Diagram 2. Clases and Objects, which describe dently, atrbutes, components and behaviour 3. Inertances of the clases and objects 44 Interfaces of the objcs ad their implementation atthe objects 5. Strvetural deweription of the dexign components 6. Behavioral description in toms of sate, sate machine and signals (Section 6.3) 7 Se Evens desertion ton 65 will describe UML in detail. Chapters 1 and 12 will describe the model design examples detail, “1.10 “DESIGN PROCESS AND DESIGN EXAMPLES 1.10.1 System Design Process Examples Chapters 11 and 12 wil deseribe design examples in det 1.10.2 Automatic Chocolate Vending Machine (ACVM) Lets consider an automatic chocoite vending machine. This interesting example given here helps reader to understand several concepts of programming an enbeided system as 3 muliasking system Figure 1-12 shows the diagrammatic representation of ACYM, Assume that ACVM has following ceomponent: [thas Keypad on thetop ofthe machine. That enables child to interac witht when buying a chocolate “The owner can also command and intract wit the machine 2. Ithavan LCD display nit on the op of the icine, It displays menus, text entered into the ACVM. ‘nd pitograms, welcome, thank you and other messages. Ic enables the child as well asthe ACYM, ‘owner to paphically interact with the machine. Ils displays time and date. (For GUIs, he keypad land LCD display units or uch seen are basic units.) 3. Ithas coin insertion stot anda mechanical coin sorter so that child can insert coins to buy a chocolate. Tthas a delivery slot 50 tht cld can collect the chocolate and cons, if refunded 5. Ithas an lnteret connection port sing a USB based wireless modem so that owner can know stats ‘ofthe ACYM sales fom aremee location ‘ACV Functions Assume that ACYM functions areas follows: |. The ACVM displays the GU anf the child wishes to enter conactinformation, birthday information ‘or get answer to FAQS; it splays the appropriate menu 2. Tedisplays a weleome messege when in ide state, I also continously displays time and date atthe Fight botiom corner of display seree. It can also intermittently display news, weather data or ‘advertisements or important information of interest daring ide state(«] emoesia Syston s 4 ‘When firs coin i inserted. a timer also stars. The child iv experted ts insert sl requiee! eins in 2 minus. Alter? minutesthe ACV will display a query to the chil if the child docs not insert salfclent coins. Te the query is not anywered the coins ate refunded. Within 2 minutes if sufficient coins are collected, it displays the message. “Thanks, wat for few ‘moments plese", daliversthe chocolate through the delivery sll and displays message. “Collect the chocolate snd visit again, please” Hardware units _ACVM embeds the following hardware units 3 4 Microcontroller or ASIP (Application Specific Instruction Set Proces-or) RAM for storing temporary variables and stack ROM for application codes and RTOS codes fr scheduling the tasks Flash memory for storing user preferences, contact data, user address, user date of birth, user iemiticaton code, answers of FAQs “Timer and interrupt controler A TCPAP port (Iniemet broadband connection) tothe ACVM for remote conto and forthe ownee to ei ACYM status reports ACM specific hardware to sor cons of different denominations. Bach denusninatio coin generates ‘se of stats and input is and port-incerrypss. Using an ISR for that port, the ACYM process eas the port status and input bits. Te bits give the information about which coin has en inane. ter cach read operation, the satus bits are veset by the routine Power supply a=) {Use _wweeiess_} Moser [tester [eerste Fig. 1.12 Diagrammatic representation of the ACVM Software components ACVM embeds the following soltware components 1 3 4 s. 6 Keypad input red task Display sk Road coins ask for find Deliver chocolate task TCPNP stack processing task TTCPIIP stack communication task ins sted 1.10.3 Smart Card nN ‘Smart card is one othe most used embedded system today Is used for evedit-eit bankcard, ATM card, e-purse or e-Wallet card, identifeaton card, medical card (Tor istry and diagnosis details) and ead for @ Irroducton to Embedded Systems 45 number of new innovative applications. [Reader may refer to a frequently updated website. tpi! wor sguthery @ia.ne fr the answers of Fequentl asked question about card. |The security aspect of ‘paramount importance for swurt card use. when used for financial and banking-elaed vansictions TRcoder ‘may cefer to huip//wworhome hkstarcomalanchan!papertsmartCardSecurty! and hip.J/www rescarch, ipmcomsecure_systemssard hum fur details ofthe card-securty requirements | ‘The smart cai is a plasie ear ISO standard dimensions, 85,60 x 53:98 x 0.80 mm. [isan embedded ‘system on acard SoC (System-On-Chip 150 recomnmended standards are IS07816( 0 4) fr host-rauchine ‘contact-based cards and 18014443 (Part A or B) lor the contactless cards, The silicon chip is just few ‘multimeter in sie and is concealed in-between the layers ts very small size prec the cad from bending Figure 1.13 shows embedded-system hardware components for a contactless smartcard ‘A Embedded Systm Contsel.ies St ard Components eer ems (erase! aA ta ratio aoe ee one 77 le [eer 1p Tima [ime na | mptece | ret Cansoter ‘snc’ | ones Key Weasor | ‘Crest ‘System Power Sirly onca Fig. 113 Embedded hardware components ina contactless smart card Embedded Hardware ‘The embuided hardware components areas follows ‘+ Microconieoller or ASIP RAM for temporary variables and sack (One time programnchle ROM for application codes and RTOS codes for scheduling the asks Fash fr storing user data, ser aes. user identification codes, card umber and expiry at “Times and intapt contol ‘carieeqoncy 16 Mie goneting cuit and Amphi Interfacing cite forthe 10s Charge pump fr delivering power othe ante for ransmision and for syst iris. The charge pp tres chage fom recived RF (rai frequency) a the card antenna in its vicinity. [The charge ump sasimpecicithat consis ofthe diode and bigh vale feraelecics materi based capacitor “The dels ofthe basic hardware units rs follows: sd Shifted Key (ASK) modulator4% Embedded Systems 1. The Microcontroller used can be MC5SHCIIDI or PICIECRS or a smartcard process Philips Smart XA ora similar ASIP Processor, MCSSHCIIDO has 8 KB intemal RAM and 32 ks EPROM and 273 wire protected memory. Most cards we 8-bit CPUs. The recent introduction inthe cards is of {1 32-it RISC CPU. A smartcard CPU should have special features, fr example, security lock. The Tock is fora certain sections ofthe memery. A protection bit atthe mirooontolle may protect | KIS ‘or more dats From maification and access by sn extemal source or instractios outside that memory ‘Once the protection bit is placed at the maskable ROM in te mierocontoley, the instructions or data ‘within that part ofthe memory are accessible fom instructions in that part only Ginter) aed not accesible from the extemal insrutions or insrctions ouside that part. The CPU may disable wecess by blocking the write cycle placement a he data its onthe buses For instructions and data protection at the physical memory ater cetin phases of card iniializaion and before issuing the card to the User Another way of protecting iss Follows: The CPU may access by using the physical addresses, which re diferent fom the logical address used in the program, 2. ROM is used i the card. The usual size is 8 oF 8 KB Fr usual or advanced cryptographic features in the card, respectively, Full or put of ROM bus activates only after a security check. The processor protects apa of the memory from access. The ROM stores the flfowing. i. Fabrication key, which is unique secret key fr each ca. It is inserted durin fabrication. ii. Personalization te, whichis inserted after the chip is tested on a printed circuit board. Physical, axdeesses are used in the testing phase. The key preserves the fabrication key and this key insertion preserves the ex personaliation, Aller insertion of this key, RTOS and applications use only logical adicesses ii, RTOS codes is. Application codes ¥_Avulilization Tock to prevent madiication of two PINs and to prevent access to the OS and pplication instntions, It stoes afl the card enters the utilization pha, 3, BEPROM or Fash scalable. These means that onl that put ofthe memory required fra particular operation will unlock for use. The auhorier wil use the required part: the application will we the other part. I is protected by the access conditions stored therein. lt toes the following: {. PIN Personal Identification Number. the allotment and writing of which is bythe authorize for ample, abank)andits seis posible ty the late only by using the pesonaliationand fabrication keys. It for identifying the ead user in Future transactions. Card user is given this key Altematvely, nifiable password is given tothe user and password opens the PIN Key. ii, An unblocking PIN for use by the authorizer (say the bank). Through ths ey. the card iret ‘entities the auhorizer before unblocking. Dats ofthe user unblocks forthe authorizer and Storing of information onthe card is posible bythe authorizer through the host ii, Access conditiors for various hierarchically aranged da ile, iy. Cand wer dat, for example, name, bank and branch identfiaton number and account number (or health insurance details vs Data post issue thatthe application generates. For example, in case of e-purse, the details of previous wansacions and curent balance. Medical hisiory and diagross dtalls andor previ insurance claims and pending insurance claims record in ease of a medical car vi also stores the application's non-volatile data vil Invalidaion lock sent by the hos after the expiry period or ea misuse and user account closing rexucat I hacks le data files ofthe nsx or ekencitay individual ile or both, 4, RAM stores the temporary variables and stack during eard operations by cunning the OS and the applicaion Introduction to Embedded Systems. far J 5. Chip power supply voltage exact by scare pump eitcut The pump extracts the eae fran the ‘signal rom the host analogous to what mouse desi a computer and delivers the regulated voltage tothe aid chip, memory and 10 systom, Signals cas be Frm antcana or rom lock pin. na typical curd operation axing 0.18 technolo. 1.65.5 V isthe teshold init and for. pn ieenology, 271055. 6, 10 System of chip and host interact thewugh asynchronous svial UART (Section 32.3) a 9.6 k or 1116 of 115.2 k baud. The chip inerconmics to card hosting sjstom (reader and writer) etter Through the gold contacts oF though a centinster sized antnaa on each side. Te later provides ‘contactless inerconnection between the 10 pins which are mean or contact based interaction, RST {Reset Signal fom hast) and Clock (Hem hos) 17, Wireless Communication foc 10 interaction i hy rations dough the antenna coils fr coat interaction. The card and host interact tough a card modem and a ost modem, The aplication rococo data unit (APDU) isa standad for communication betwen the ear and hest computer ‘Modulation is with 10% index amplitide modulating carrier of 13.66-13.56 Mbps ASK (amplitude shied keying) suse forcontactess communication at dts ratesot~1 Mbps. One-sixtenth frequency subeatier modulates though BPSK (Binary Phase Shifted Keying Embedded Software Smart card eters ihe folio 1. Boot, initsisstion and OS peograns 2 Sit card seve fle system 3. Connection establishment and verination | Conimaication with host 5. Cryptography algorithm 6. 7 softwite components: Host authentication Cand authentication dion paraneers of rvent new data sen by the bot (or example, present balance let) “The sinart card is an exeimplry secure embedded system with security Softvare. The card eth. cryptoprapic soiware, Embedded software inthe card neous special Features in its operating system ove and above the MS DOS or UNIX system features. Special features needed areas fllows 1. Proicted envivnnen.H-mcans vtiware should be stored in he proteted pat oF the ROM, 2. Restricted! rosie ensrnament A. IOS, every method, class and rn time idea soul e sealable 4S Code-sive termed unl be epitnun, The system needs shoud mo exceed 64 KB memory. 5. Limited use of datatypes: multidimensional arays. kone Gb inegcr and eating points ad very limited use of the roe handlers, exceptions (Section 4.22), sigals (Sections 6 Sand. 10), stialization, debugging und profiling [Serialization i the process of converting an objet ino dat stream (oe transfering itt network or From one proces 10 snther. Te deserialize dat arc the receiver end}. 6, A three-layered file sytem forthe dats. One file forthe maser flew toe al ile headers. header ens File status, access conditions andthe ile lok. The second file is a dedicated file to hold file frouping and headers ofthe immedi sucessor elementary files ofthe group. The third file isthe elementary file hold he file header and its le data, 1. Ther is eter a fixed length fle management ora variable length fle management with each file im __ having a predefined offct 8. Clases Forte network, sockets, connections, data grams, characte input output and steams, security management, digital-cenificaton, symmetne and asymmetric keysbased cryptography and digital signatures ’Emboddod Systoms, 1.10.4 Digital Camera Digital cameras may have 4 1 6 M pine! sil images, clear visual diplay (ClearVid) CMOS sensor. 7 cin wide LCD photo display screen, enhanced imaging processor, double anti blue solution and high-speed provesting cine, 10X optical and 20X digital zooms and can also record high definition videoclips. It therelowe has speaker microphone(s) fer bigh quality recorded sound. I is an auiivideo out port for conrectng to a TV/DVD player or compute. Letus assume that the camera is sill jas a camera. Figures 1, 14a) and (b) sow hardwae and software ponents in simple digital eamera, Assume thal the camera has the following Components | [tebarteaecsentartone ven] [Kor oo | | =m ee | [Dee ——- Fig. 1.14 (a) Digital camera hardware components (b) Digital camera software components 1. thas keys oa the camera. That enables a usr to operate the camera. thas navigation keys to mivigate Uhrough the images back and Forth. 2. Shuter, lens and charge coupled device (CCD) array sensors for images in sizes 2992 x 1944 pixels = 5038848 pixels, YGA (E-mail) 640 480 = 307200 pixels, 2592» 1728 = 3.2 M pixels, 2088 x 1536 pixels = 3 M pitels.or 1280 x 960 pixels = 1 M pixel. 3, Tihas a good resolution photo quality LCD display unit onthe hack of camera to show photographs ‘recorded video-lips. It displays text suchas image, shooting data and ie and serial number. In isplays messages 1 displays the GUI menus when the user interacts with the came. 4. has agelf-timer lamp for fash 5, Intemnal memory lash to store OS and embedded software, and limited nutes of image files 6. Flash memory stick of 2 GB or more for large storage. - Introduction to Embedded Systeme [4 7. teh Universal Serial Bus (USB) por (Section 3.10.3 or Be computer and printer, ih interface. which cannes i toa Camera Functions Assume tht the camera funetions is fll |. teisplays the trame view on the LCD screen so that usce ci aj the camera inclination before ‘hooting the frame 2 Walsplays the saved images onthe LCD using navigation keys 3. When a key fr opening he shulter i presed, the Flash ann glows and the sf timer ciruit switches of the lamp astomaticaly. 44. The rae ight fallson the CCD array, which wansmits tho bits foreach peli each row in the Fame through an ADC. Bits from dark area pines in each row are sed for offset comections inthe CCD signal fr light intensities in each rv. ‘The CCD bits ofeach psel in each row and column are offset crtected using a CCD signa processne «CCDSP), 6, The procesed signa te compressed using 2 PEG CODEC and saved inne jp file foreach rams. [A DSP does compression using the the discret cosine transformations (DCTs) and decompression by inverse DCT. Thoreater.it also does Hulfman coding for JPEG compression. A DAC send the inputs forthe display unit. The DAC gets the inp from the pixel pmecessor. which et the inpus fom the JPEG files forthe saved images snd gets input diretly fom the CCDSP Hough the pixel processor or the frame inthe present view” igital Hardware units The camera embeds te following hardware units |. Mierocontoller oF ASIP 2 Mltiple processors (CCDSP. DSP. pixel processor totes) 3. RAM for storing temporary vribles and stack 4. ROM lor application cades and RTOS codes Fr scheduling tasks 5. Tine fash memory Tor storing see preferences, contact dl, user adress. user date of hi. usce idenieaton code. ADC, DAC and interut controller (Sections 1.3.3, 13.5. 147 and 13.11) USB controller (Section 3.10.3) Direct memvey access conrier (Section 4.8) LCD contmller (Section 334) Baery Software components. The camera embeds the following software components CCD sia geocensng for offset correction 2 JPEG coding 3. JPEG decoding 4: Pixel processing before display 5. Memory and file systems 6. Light. lash and display device drivers 1. COM, USB port and Bluetooth device divers for port operations for printer and computer ‘communication conto on 1.10.5 Mobile Phone The mobile phone today has a large number of features. I has sophisticated hardware and software.{9} Embedded Systems Hardware units» mebile phone embeds an SoC (System-on-Chipy incense follwing hardware units |. Microcontroller or ASIP JAn ASIP is configured to process enewtiny and deciphering and another tes the vice compression, Third ASIC dal, modulates, demodulaes. interfaces the Keybosrd and touch serecn or matte fine LCD graphie displays, and processes the data input and recall of data Fro mesnoryh 2, DSP core. CCDSP, DSP, video, voice and pixel processors 3. Plash mentor stick, EEPROMS and SRAMS 44, Peripheral circuits, ADC, DAC and interrpt conolier 5. Ditect memary access controller (Section 48) 6 1 LCD contcller (Section 3.3.4) Bauery Software components The mobile phone sofware development tools are a follows: 1. OS (Windows Mobile, Palm, Symbian) oF BREW 2) Java 2 Micro Editon J2ME) along with KVM asa Java Viaual Machine Section 574) 3. Java Wireless toolkit with JDK (lava Development Kit) “The mobile phone embeds the Following software component TE Memory and filesystems 2. Keypad, LCD, serial, USB. 3G or 2G pont device drivers for port operations fr keypad, printer and computer communication contol 3. SMS (Short Messaging Service) message creation and communicator. contact and PIM (personal information manager, task-to-do manager and ena ‘Mobile imager for uploading pictures and MMS (multimedia mess “Mobile braser for access 1 the Web Downloader for Java games, ring fone gnes. wall papers Simple camera with (Section |.10) Bluetooth synchronization. IDA and WAP connetions support (Section 3.13) ervey 1.10.6 Mobile Computer “The mobile computer has Windows CE or Windows mobile as OS. [thas w touck sereen for GUL, The wer uses sys to enter commands. Ithava vieual keypad (the keypad displayed en the screen and entries of text and comimands is through te stylus. In addition to phone, a mobile computer bas following software components {. OS (Windows CE, Windows Mobile, PocketPC. Pali OS or Symbian OS) Touch sereen GUIs, memory and file systems ‘Memory stick Outlook. Internet explorer, Word, Excel, Powerpoint, and handwritten text processor Applications or enterprise software 1.10.7 A Set of Robots ‘Consider a set of robots. One robots the master robot (music director) and seven ae slave robots conductor). Assume that thestisused to ply an orchesta Figures 1.14) and (b) show hardware and software components {nthe sot of robo. Assur: that the robot has the following component 1. The master robot signals the commands and slave robots play accordingly Introauton to Embedsed Systoms e) Each mbt is asumed to have ive degrees of freedom. Each robes hava mochanical ystem of five degrees of freedom. At each degree of freedom, thre is a servociotor A servomatar conto by PWM methud (Seetion 1.7). Each motor fs controlled in squence tlt the robe pron the esiced etn 3. sch root hava mierocontraller with expansion ports, Po. P8. Actually axngle ASIC cam perfonn ‘line port fonctions of a microcontroller, Howevesnce the engineering cst of ASIC development is igh. «general purpose microcontroller 6BHCT2 or 8051 is use. “The port eutpuls comect he metors snd PWM outputs dive the motors in cach robo Each robot has eral 10 with EDA protocol (Section 3.13.1) Tneral memory Mish to store the OS, embedded sofware and limited amount of music There is a mas file processor Fo playing the music. Slave robots have speaker outputs fe playing ‘Master Robot Functions Assume that maser robot functioning iv a follows |. Hreceives comands from s emote controle to stat and sop the rasic and the code forthe speviic orchestra toe played 2. sends PWM signals othe pos for moving the sticks in oth hands as per the program, 3. Wesublishes and binds the sockets the vitua devices) connection with the slaves. I sends the signals through rockets using DA protocols. The byte streams respons to the clients ae as pe the Music File tobe played by the save ‘Slave Robot Functions Assume tat slave robe functioning i as follows: 1. establishes and binds the sockets (he viral devices) connection with the mast 2. Mt receives rom a miner socket the commands accep () and write (it alo receives commands 10 start and stop music ad the code forthe specific orehesta tobe played receives the signals through sockets using IeDA protocols. The bye steams from the server areas per the music ie being pled, Hardware units Robots embed the following hardware uit 1. Microcontroller or ASIP 2 Masi file procesor 3. RAM for sexing temporary variables and stack 4. ROM for application codes and RTOS codes for scheduling bot setions and asks 5 Timer Mash meniory for storing wer preferences and musi Files 6 IeDA controller (Section 3.13.1) 7 8 Dincct memory access contllr (Section 48) Powersupply source or battery Software components Robots embed the fllowing sofware components 1, Socket functions 2. Music coding 3. Music decoding 4. Memory and ile systems 5. Light, flash and display device divers tam 6. IrDA and socket port device drivers 17. Motor devers 8 10 15Rs) 52 Embedded Systems ~iScoto,Tener |_owac: Pune | [se tseen i usuoh or rOAos es Fig. 1.15 (o} Hardware components in the set of robots (b] software components in the set of robots in which a master robots signals the commands and slave rabots play according to the signals from the master “1.11 “CLASSIFICATION OF EMBEDDED SYSTEMS ‘We ean elasify embedded systems into thre type as follows, 1. Small scale embedded systems: These systems ate designed with a single 8 or 16-bit microcontale: Fy have ite adware and softwar complies ad inset ene eign They mayeven ebay ops When deeaping ened swash anc semble dcr meted develomen envsanmen(IS8 ose the mica or procevor ular te nai programming os Ying" lneue grams se compa io the aebly and execuabe codes te ppromy located ne spent meray he setae ak to whi the memory avalble and keep WO te need ty litt poverdaspaton when Ue 1. Medium scale embedded systems: These ssems ae uu designe with ingle or afew 16- or 32-bi micecontoner: DSPs RISC. Ths systems may aso employ the ready aaa single perce proceso od IPs espind later Yor te ato anton for expe Ds ineracing [ASSP« and IPs ay ao have to be appropri configured by he SskmSfate before ing ints ino she sen] Media sealed syiems hae ot haar sd sft competes For compe stare Sein.efelowin opammagolear sve ices Cevtav RTOS, sore cove ensnsing ol ims dugg a at ieee Aevelmestenvionneat Siar el so provide solaton 10 adware complesiies 5. Sophisticated embedded systems: Sopisieted embeded system hae enous barwae anon compleisand ray ce sve IP, SIPs, sable posse congue pce ti programmable less They ae wed fr eating ede aie tha ee Rarote and Sotvarecodesign an compen ht ave oe netted ial stem The a eonsaine by te prcesing sessment hart nts Cerin sofa tons ach neyptn rroguction to Embodied Systems e and deciphering algorithms, discs cosine tansformation and inverse rnsformation agoritnss TCP? IP protocol stacking nd netor: rier functions are implemented in the harvaré to obain kita speeds. The software implements some of the functions of the hardware resources in the ssn ‘Bevelopment tots fr these systems may not be readily available a a reasonable cost or may not be valle all In some cases, « compiler oF eget compiler might have tobe developed for these [A retagetable compiler is one that configures according the given target eafguraion in em "1,12 “SKILLS REQUIRED FOR AN EMBEDDED SYSTEM DESIGNER “Anembeded sytem designer has o develop product using tre aailable too within the given specifications, cont and time free. (Chapters 6, 13 and 14 will cover the design aspects of embedded sysen. 1. Skills for Smal! Scale Embedded System Designer: Author Tim Wilmsinurs i his book ‘sats that the following skills are neded in the inividua::""1 or team thats developing small Scale ymem: “ull understanding of microcontrollers witha basic knowledge of compute architecture, digital electonie design, software engineering, data communication, contol engineering, motors and ctuators, sensors and measurements. analog eleconic design and 1C design and manufacture” Specific kills wil be needed in specifiesuations. For example, contol engineer knowledge will be eee for design of contol systems, and analog electonic design knowledge willbe needed when design the system interes. The basis aspects of the following tops will be described in this book eo ‘prepare the designes wha aleady hak & good knowledge ofthe microprocessor or microcontoller to be used. (i) Computer architecture and orgarination. Ci) Memories. (ii) Memory allocation (iv) Interfacing memories. (v) Burning (a term used for porting) the executable machine codes in PROM or ROM. (v! Use of decoders snd demultiplexers. (vi) Direct memory access, (Vi) Pons. (vi Device rivers in assembly (x) Simple and sophisticated buses. (x) Timers (xi Inteupt servicing snctanism. (i) C programming elements. (aii) Memory opinnizaton. (xiv) Selection of hardware and microcontole, {xv Use of ty Circuit Emulators ICE}, erose-usemblers and testing equipment (ivi) Debugging the software and hardware bugs by using st vectors. Basic knowledge in other reas—software engineering, da cosmmunication, contr enginesrng. notors and actuate nd measurements, analog eletronic design and IC design and manvfacture—can be obtained from the standard text books avslable. A designe interested in small-scale embedded systems may nia need at ail concepts of interrupt latencies and deadlines and their handling, the RTOS programming tons described in Cages: 9nd 10 andthe program models given in Chapter 6, 2. Skills for Medium Scale Embedded System Designer: ¥aeledge of *C'1C#+lhava programming, RTOS programming snd program modeling sis are mst to design medium-scale tmbedded-systein. Knowledge of he following are etal.) Tasks or threads and their scheduling by RTOS. (i) Cooperative and preemptive scheduling. i) Iter processor communication functions. iv) Use of shared dl. and programing the cca setions andre-entrant functions. (v) Use of semaphores, mailboxes, queues, sockets and pipes. (vi) Handing of erat latencies and meeting task deans (i) Use of various BTOS functions. (vi) Use of physical and virual device drivers. [Refer vo Sections 426, 7.10and7. 11] Chapters 4t0 1 give detailed deseriptoas ofthese seven along with examples and Cher 11 and 12 provide on understanding oftheir use with de hep of casestudies. A designer must haan: to an R708 programming tool with Application Programming Interfaces (APIs) forthe specific microcontroller to be used. Solutions 0 various Functions like memary allocation, timers, device divers and interrupt handing mechanism ae readily availabe asthe APIs of hx RTOS, The designer needs toEmbedded Systems ‘now ony the hardware organizaviomand us of tes’ APIS. The microcontroller press thn epee small sytem element for he designe ad ite Knowledge may suc, 3, Skills for Sophisticated Embedded System Designer: A wa is needed to e-design ant solve the high level complexities of hardware and software design. Embedded system haste engineers should have skills in hardware units and hasie knowledge of (C7AC+ and Java, RTOS snd ‘other programming tools. Sftwareengincer should have basic knowlege in hardware and ar knowledge of. RTOS und ther programming tos A Final optimum design solu sthen cbtined by system integration, ‘Summary ‘An embeded sytem is one thit hs embedded software it computer hawae, which makes it ayo Software tots.N&2~ 2G BRK SRR RORSL BO In this chapter, we wil lear the following 1 8051 architecture in brief and its processor. memory. ports, Counterstimer Seria 10 and interrupt handler wits 2. Real world wterfacing, and internal and external buses that interconnect the rocessor with the system memories, 10 devies and all other system units Imverfacing examples with keyboard, displays, ADC and DACS ‘Advanced processors x86, ARM and SHARC architectures Processor and memory organization ‘Insarucion-level parallelism and superscalar, processing, pipelining and cache tuuts for improved computational performance of the processor by faser ‘rogram execution Various types of memory and their uses Devices and memory addresses allocations Performance metrics to measure the performance of a processor 10. Processor selection for embedded sytem 1, Memory selection for embedded system ” 2.4 “BO5T ARCHITECTURE ‘The following subsections summarize the 8051 architecture in brief. A ceader may refer toa standard text for details 2.1.1 8051 Microcontroller Architecture Figure 2.1 shows the architecture ofthe classic 8051 microcontroller. Classic means the original version, based upon which new enhancemetts and vesions are provided ‘The classic version consss of following hardware: 1. A 12 Mie clock, Processor instruction cyte time is! us. 2. An B-bit ALU. The internal bus width i 8 3. CISC Complex Insirvction Set Computer) architecture. (CISC provides many modes for addressing operands in arithmetic, laical and other instructions, Several complex instructions take more than one cycle time. Complex instuetions implement in hardware not by separate hardwired logic circuits for each instruction but by a microprogram contol circuit} 4. ‘Special bit manipulation instructions. 5. A program counter, in which the inal default reset value defined by the processor is 00000, 6. A stack pointer, in which the inital defaut value defined by the processors 0x07. 2 2, 13. (ase) Fig. 218051 Architecture {A simple architecture, with n0 floating-point processor, no cache, no memory management unit mo ‘atomie operations uit, no pipeline and no instruction level parallelism, (Sections 2.3 and 2S). There jis no DMA controle (Section 4.8) in the classic and mast other versions. 'A Harvard memory achitectre(Setion 242). The program memery and data memory have separate ‘adress spaces from 0x0000 ad separate control signals). (On-chip RAM of [28 bytes. The B052 version provides for RAM of 256 bytes; 32 bytes of RAM are sso used as four bank (ets of registers. Each estr-set (bank) thus has eight registers. The external datafstack memory canbe add upto 64 KB in most versions In cetain 8051 enhancements this iit has been enhanced to 16 MB. ‘There ae special function registers (SFR). These are PSW (processor stats word), A (accumulator), B tepiser, SP (stack pointer) and resisters for serial 10s, times, pots and interrupt hander. 8351 version has on-chip ROM; 8751 version EPROM; 8951 version has on-chip EEPROM or flash ‘memory of 4 KB. Several versions provide fr higher capacity ROM. Additional program memory can be added extemally upto 64 KB. In extended 8051 and unified address space versions (8051 EX and [MK versions) this limit hasbeen extended to 16 MB. ‘Two extemal interrupt pis, INTO and INTI Four pots PO, P].P2 3p P3 of 8 its each in single chip mode. Section 2.1.3) Thee are two timers (Section 2.15) anda serial interface (SD. Itcan be programmed fr three fll duplex UARTT modes for ‘serial TO. [JO with each bit ofa word successive transmitted onthe data ine fr atime interval} The ‘Sl can also be programmed fo half duplex synchronous 10 (Section 2.1.6).tc Embodsed Systems 114 Classic version has no pulse widlh modulate ad prs on support v9 DAC. (Seetion 1.3.7) thas no modem, 0 watchdog timer, 0 ADC. Ceraia vrion spon witchog timer and ADC. Siemens SAB 80535-Nsuppors ADC with programmable rogram codes rea trom program memory). {sis because of the use of Harvard architecture (Section 22) for system memories ‘An iterfacing circuit consists of decoders and demultiplexers and is designed according tothe available como signals and timing digrars of bus signals. Ths circuit sonnet al the units processor tvemory and the 10 device through the system buses Is apart ofthe glee circuit used in the system and in GAL (generic array logic or FPGA. Figure 28 showsa simple diagram of typical computer system in which buses provide an interconnecting rnetwrk between the processor, memory, and IO systems. In real world interconnections, the network Foxes by buses in the main subsystems. “The system bus imerconnects the subsystems, which interconnects the procesor withthe memory systems andalso connects another st of signals called the 10 bus. Figur 2.10 shows the sytem and IO buses, Iisa twoevel bus architecture. Using an 10 bus allows a computer io interface with a wide range of 10 devices ‘without having fo implement a Specific imtrface fr each 1O device. An 10 bus ean also suppor variable umber of devices, allowing users to add devices toa system after it hasbeen hardwired, Beviees an be designed to interface with te bus allowing them to be compat with any system that utes the same typeof [bus The 10 bus creates an interface abstraction that follows te processor to interface with awide range of 10 devices using a very limite set of interface hardware. Deus descriptions of popular 1 buses and wireless communication are given in Sections 3.10 193.13, PCI and USB bus (Section 3.12.2) interfaces to devices are designed to meet the PCI standard and USB (Geeton 3.103) standard ‘All thats required isa device driver (Section 4.2.4 in an each operating system—a program that allows tne operating system to conta he 10 device (Section 86.1. ‘The downside of using an IO tus to interface to 10 devices i that al the 10 devices in a computer must share the 10 bus, and 10 buses are slower than dedicates connections between the processor and an 10 device because the 10 buses ae desined for maximum compatibility and flexibly 75 ‘08 and Advanced Processor Architectures, Memory Organization ard Rea wold tracing ooncr Cock for He XTAL Te025 | MAS att ep pets = OM 007 moor (arogwrie) (rage mr ‘rc wito) @ = r 0000 White concn FFF ‘g2.9- (a) Timing of signals from processor when interfacing memory anil ports in 68HC11 (6) Circuits for the interfacing memory and ports in 68HC11 ‘An interfacing circuit consist of decoders and demultiplexers as well ss an 10 bus bridge controller. The imterfacing circuit is designed as per available contol signals and timing diagrams of bus signals. This, circuit connects all the units, procesor, memory, 1O bus bridge controller nd the 10 devices through the system as well as through the 1O buses, 10 bus bridge controller may be apart of the glue interfscing circuit sed in the system and isin PLD (programmable logic device), GAL (generic atay loge) or FPGA. ‘Multilevel Buses Figure 2.10 shows a two-level bus architecture, Figure 2.11 shows a three-level bus architecture, 152.2. 10 Addresses of Ports and Devices in Real World Interfacing ‘Memory Address-Mapped 10 Operations Many processors and memory organization require ‘memory-mapped IOs, 10 device and port addresses are interfaced such that these ate distin from the memoryif 76| Embedded Systems —l [fon oa bce | erent ca SS 5S oS [Toone] Cetera] ows] [bene] Fig. 2.10 Memory, system bus and 10 bus interfacing in a two-level bus structure (mae = reas] | 1 Cater Pr St i = a L_, 1 — contr Ledarinan | {(gsaaeices"] [use rers | 2.41 Separate memory and /O buses to communicate with the memory system, and the 1/0 system using 3 bus controller and a separate disk 10 bus aise Menry ies eo dt nd ose, and 10 aes forte 108 Te floving are fees of meno mp Os The prcsr ha or 1 aes sce or prs an devises, * The nanctons aswel eco ea fre optons noes a mem 10 parandve addresses are the same. ‘as prletiats {051 and Advanced Processor Architectures, Memory Orgaization and Reak:wordItertaong | 77 + The processor has no separate input-output and memory load-stoe instructions {+ The arithmetic, logical and bt manipulation instructions that are available for data in menvory ae ato avalable for 10 operations. The process can dcctly manipulate the data taken from or sted tthe 10 por or device. The manipulation of ll istuetons i the memory can be dane using an scum any fegiteror any other mcmocy address where the 1O por byte is transfered afer, during or belie the arithmetic ological operation Almost all microcontrollers. therefore, have no separate instructions for 10 processing, The #051 njerocontrollr (Section 2.) an example ofa memory-mapped 1O-tased processor an memery orgnization, ‘The 8051, 80196 and 80196 microcontollers have preassigned device 1Oadresses for ther intemal devices sd these addresses are not configurable. Figure 2.12(a) shows tha device addresses are within the RAM and are distinct fom memory aditesses. Movorola processors have no separate nsrutioné for 1 processing. Consider another sytem with a 68HCII icrocontoler. ‘configuration is shown in figure. Pon A, 10 contol register PIOC, Port C, Band port contro! (CTL) registers have addresses ber wezn (00 to (x04. On-chip RAM is configured between Ox003F to x00. [The port addresses and on-chip RAM are configurable by the bits ofthe configuration register in 6SHC1 Forexample, the above device addresses can ao be r-configured and assigned between 0x0 100 and Ox 1040 10 Addresses Mapped !O Operations Some processor and memory-organization requires IO ales ‘mapped IOs operations. Consider assem withan 80x86 processor Figure 212) showsthe memory ress cn the lef side. I shows the port adresses allocated in TBM PC for timer, keyboard realtime clock an serial por (called COM2) on the right sie, This figure shows tht device addrestes need not be distinct, they can be the same asthe memory addresses ass contol signal will distinguish between them, The following ae featwes of 10 addres-mapped 10s 1. The pracessor is scparte 10 adres space for ports nd devices 2 The insrwtions and contol signals for operations on bytes at the memory and 10 ports an devices are distinct, making the desi simple, 10 devices and pot addresses ar interfaced independent of ‘memory, without considering the memory addreses that ae asigned for sliwaze and da, 3. The processor has separate input-output (or ead ad write) insretions nd memory load-store (for ‘ead and write insructioas. 4, All he arithmetic, logical and bit instevctions that are avilable in memory are fist operated using the accumulator and then fom there Byes are transfered afer an arithmetic or logical operation, ‘The IC subsystem has input units and ouput units, aso called 10 devices. Al 10 ports and devices have adresses. These ae assigned to deviees accoring to the sysem processor and intemal hardware coniguation Direct ALU operations on pot byte(s isnot provided The addresses of device depend on the syst hardware configuration. Most processors follow memory- ‘mapped IOs and process the memory and ober devices data with the same instructions. Some processors se 1O-mapped 10s; forexample, 80:86 processors process these wih diffrent st of instructions (input ‘outpetinstetions) and control signals. 2.2.3 Device Addresses in Real World Interfacing During processor instruction, a device when addressed, it ges selected and communicates with sytem bus or 0 bus using aset of adresses. These adresses are selected either as per decoder circuit desig ora pe the AB %0 Big Endian 0 4B cD F In general, programas donot need to know the endianness of the system they ar working on, except when the same memory location is accessed using leads and stores of different lengths. For example. if ‘byte store of 0 into location Ox1000 was peared on the 32-bit systems in Example 2.10. a subsequent 322it load From 01000 would run 0xS0ABCDOM on the itle-endian system and OxCOABCDEF on the big, endian system. Endianness soften an issue when transiting data between ferent computer systems. as big. endian and litle-endian computer systems wil inte the same sequence of bytes a diferent words of dat, ‘Toget aound this problem, the data must be procesedto conver it to the endianness ofthe computer that will read it Figures 2.10 and described the memory, processor and 10 units organized onthe buses. It canbe safely concluded thatthe memory organization has a tremendous impact on computer system performance and is ‘often the limiting factor on how quickly an application executes. Both bandwith (how much data can be loaded or stored ina given amount of time) and laeney (how log a particular memory operation takes to complete) are critical to application performance Other important issues in memory system desig include protection (preventing different programs from accessing each others data) and how the memocy system interacts withthe IO syste, 051 ard Advanced Processor Architectures, Memory Organization and Real-world tracing | 103, “There may be on-chip memories as RAM andlor register files. windows, caches and ROM in a micro “The caches are the integral pars of the wemory-organization within a system, The software designer should enable the se of caches by an aropnate instruction, wo obain greater performance during the un of ‘section of a program, while simultaneously disabling the remaining sections in onder to vedce the power dissipation and minimize energy requiremenis. Hardware designers shoud select a processor with mulway ‘ache units so that only that par of a cache unit sets activated that ha the data necessary to execute &subet fof insiruetions, This ako reduces power dissipation Processor Memory Organization: Princeton Architecture Figure 2.23(a) shows processor and ‘memory organization in Princeton architecture. 80x86 processors an ARMT have Princeton architecture for ‘hain memory. Vectors, pointers, variables, program segments and memory blocks for data and stacks have Afferent addresses inthe program in Princeton memory architecture. Processor Memory Organization: Harvard Architecture Figure 223(b) shows processor and memory organization in Harvard architecture. A processor having Harvard main-memory architecture has rom 2). bes 21. 22. /* Base Segment for 32 byte of Frogram Variables Data at RAM */ 23. _beastart = 0x10010; 7* Smart card base segment data at the base segment data file named here*/ ero Pane ktes Mrm Cams otros ions {13] 4. _BottonotHeap = 0x10900 5. text rom 6 Ue crypting Java Card program instr. the file named here*/ Joa (-== stmt) 8. data ram Oi 10. /* Shadow Segnent for 256 bytes of Initials: from RON from */ —Datastart = 0x10000; 12. /* The card shadow segnent data at the date file named here*/ a. (-~~.datay 13, _vatasna = ox100FF; ud J* Command for copy into the RAM * 15. a. rom 16. bes uv @ Data at RAM for @ copy /* Base Segment for 2 kB Program Variables Data at RAM */ 19. _besstart = 0x10100; 20. /* Java card base segment data at the base segment data file naned here*/ 21. a. (-=--.be8) 22. _bssEnd = Oxi08FF; 23.7 2a.) ‘The memory mp that inchades the device 10 addresses is designe after appropiate adres allocations of 25. * (--~~.bes) 26. bssBnd = 0x1002F: the pointers, esters. dt setsad data stetres Ite min menery 8 oF Farardahecan te pense ay imenory map wil be separate. For example, 8051 rads fom the program memory by spa ce ok a insttons Ginpst-cupa nsttons). Example 2.15 "2.8 “PROCESSOR SELECTION Consider another memory map [Figure .25(4] for another exemplary card. The locator specifies diferent map sections as follows: A hardware designer must take inte account following procestor-specitic features |. A processor which an operate at higher clock sped, grocesses more inructions per second. 2. A processor gives high computing performance whea there exist (a) Pipeline(s) and superscalar SECTIONS Tee eee ee ee architectures, (b pre-etch cache unit caches, and regiser-files and MMU and (c) RISC architecture, ees 3. A processor with register. windows provides fast content switching ina mltsking sytem, Ae 4. A powereficentembedded system requires a processor hat has programmable auto-shut down feature : for its units and programmability for disabling use of caches when the processing nee fora functionEmbedded Systems 2051 and Advanced Processor Architectures, Memory Orgarization and Real world Intrtacing or instewction set isnot constrained by limit on execution deadline, Processor uses Stop. Slep and Table 2.7 Essential processor capabilities in four exemplary set of systems ‘ait instractions, nd sperial cache design 5. A processor that has a bust mode accesses extemal nemvris as reads Fast and writes fost Pricer caps Cae Cnet Cane me & A processor with an atomic operation unit povides arias olin to shared data problems when Required ‘Automat ice deve Wabi.pon voice designing embedded software, ele special progzarining sill and lft eto be made when program Choco Vending acqisto,Wocedta Network Tamer Proceso tes shared variables and data buffers amoag multiple asks Machine, Acn: Congreso den Fat Sis fetes, We 7. When coding in asembly language or designing compiler of locator. dat may store in bigeian sieeSearm Kal | Compreion Adee Milf cheat prog rode ina system and the lower ordrbytes store athigher ates: forexamplen Motorola processors ae ares tee ae Data may also store in Fitle-endian mode in a system. Lower order bytes stort lower adresses and ee vice vers: for example, in Entel processors, A processor may also be coiure atthe inital program }— = a — stage bigendian or litle-endan storage of words: for example the ARM proce sr Regie proceso Micrconvaller——_ Microprocesor Muliprssser Sytem Microprocessor The StrongArm family processors frm Intel and TigerSHARC from Analog Devices ave high power {DSP ted llcency features Moliprocessor The processor selection processes canbe understood by considering four representative cases, Fisly Sytem desgn- able similar to Table 2.7 ible Then 3 processor having the equired situa unis and capable of Proceso insrucion -05101 001-004 (20005-0001 0.01 ~ 0.005 shine sired proces perfomance in syste schon — yee intima TP Case J. Systems in which processor instruction eye time ~ | sand on-chip devies and memory Show at sedan oi s ; San suffice Examples ate automatic chocolate vending machine. 58 Ktps moder, rob. data eee ates cee ernie eae ‘acquisition systems like an ECG recorder or weather recover or inulin! temperature an pressure Area bus wih 8 2 2 “ recorder and teatime robotic cone. ints 2, Case 2: Systems in which processor instuction cycle time ~ 101040 ns require on-chip devices and ee ee Bee rg a memory do not suffice and medium processor performance is required. Examples are 2 Mbps router, Sehiosue image processing, voiedata acquisition, voice conipresion. video decompression adaptive ruse 7 ; 7 ! contol system wih sting stability and network sateway. Progum comer 2 2 4, Case Systems in which instruction evee times of 5 to 0s gre and high MIS or MFLOPS ond sack itr, psfocmance is needed Examples are multipo 100 Mp etwock tanseier at 100 Mbps switches, Siosk ststernt ——Esernal Extra rine Internal Inert Toutes, multichannel fst enerypions und decryption. syste. Pera enor 4, Case 4: Systems in which instruction eyele time of even Ins doesnot sulfce and multi-processor Cops - va system is required along with use ofthe eating point and MAC units. Examples are voice processing wee ‘ideo processing reine aio or video processing and mobilephone systems Ditteren systems require different processor features, A hardware designe takes these into view and Peete twee No ve Ys. Ye ! selets an optimum perfarmance-giving processor. ai sai j 2.8.1 Microcontroller Sele COffchip RAM in Noonshipslfices Yes Yes ves There are numerous versions of $051. Additional devices wd writs ne provided in these versions Aversion ta oct and microcontrollers selected foe embeded system design as per the aplication as wel a i cos. 1 Embedded sytem in anatombie, for exarpl, requires a CAN bus (Section 310.2), Then a version COnctip egiser No Ye Yes Ye vith CAN bus contr is selected windows ad files 2, Au805t enhancement 8052 has an addtional timer ao miooes 3, Philips P83C528 has PC serial bus (Section 3.10.1), sehng res 4, 8051 fansly member 83C152IA (and its sister JB, AC and JP microcontrollers) has wo direct memory fe a ne aa access (DMA) channels on-chip (Section 4.8) The 80I96KC tas a PTS (PerigheronTransactions imenain‘icw:— erocenetler Serve) thar sapports DMA functions. (Only single and balk ransfer modes ae supported, not he conte er exe burst transfer made) When a system requires det transfer to mesmory from external systems, the to wocesor DMA contol, ingroves the system perfonnance by providing fra separate processing unit forthe ams data transtrs from ant the peripherals.Embedded Systems jne — = 5 Presser camilin Cue 4 Cae 2 Case coed | Required Auomu Voice de Malicpon ie | Chace Wet acquis, Wice-date Nevwort Traneciier— Presor ‘Mactine. Data Aegui-Campressoe, Video Fast Swine, Rowters. Video sion Srstem, Real Compression, Adaptive Multichannel Fist pressing end ‘ime Robotic Cnt! Crise Conia Stem Encryptions anole Pen | Nenwork Gateway lasruction and das No Yer Yes Yes with Sing Sabin, decraions Sites | | caches and MMU Cmehipmenory —Yevonctin.——Nenctpes——Nasonchipdos Nosy fmverePmont ties an neni Gono Esta items 16 2 18256 ie | imine ted ery wed Heavy wed Hey mad peo i Srsumy ofa No Mont Noses) May be tay es | reyoing Harv ms} DMA center No te ve aye Evemiplary 8051. 68HCII or 12x86, 80860. 80940 ARM. Sunspare armors | pocour niyo Ta tony oS PICIGFSS Powerc | 'scaal wien mile pos and michael opsratos ee ats sai 1, robotic system motor needs signalling the rate above 50 to 100 ms. Hence there is enough time available for signalling and eal-ime contro f multiple motors at the robot when we use a processor with instrution eyele time =1 ys 2. The processor speed nee! not be very high and performance needed is much below f MIPS, So n0 ‘aches and advanced processing units like pipeline and superscalar processing are requted 3. A four-col stepper motor ness only a4-bt input anda DC motor needs I-bt pulsewidth modulated output, Therefore an 8-bi processor suffices. 4, Frequentaccesss and bitaranipulations at 10 posse needed, CISC architecture therefore sce 5. The program can fit i 4 KB or 8 KB of ileal ROM on-chip. Stack sizes needed in the [rogram are smal! so that can be stacked in an on-chip 256 or 5I2-byte RAM. A ‘microcontroller is thus needed. No floating-point unit is needed 051 and Acvanced Processor Architeetures, Memory Organization and Real-world ntertaong 117 Microcontrollers appropriate for the above case are 8051, 68HCII, 6SHCI2, 6HHCIO oF 80196, Microcontrollers GSHCI? and 6HHCI6 can he used due to availabilty of tage umber of pos. The G#HCI2's instruction cycle an clock cyl tne equal 0.125 ps, Number of port eqs 12 in 6SHC2. Therelone, 6 oF more degree of fecdown mbt with 6 or nee motors ean be driven directly trough thse pors, STOP and WATT instructions in the processor save power when the robot isa est) Example 2.17 Case Sty of Yair Oats Sonumeeesion Syste 1, Voice sigals ae pulse-code modulated. The rte at which its ae generated is 64 Kbps. A suitable algorithm can process the data compression ofthese bits with an instruction cycle tine of ~ 0.01 to (0.04 js (100 to 25 MHz) when the processor uses advanced processing units and caches 2. Let us assume thatthe processor nstuction cycle time is 0.02 us (50 MHz)” With a three-stage Pipeline and two-line superscalar acter, the highest performance will be 300 MIPS. [Refer to Example 2.11 for an understanding of the computations of MIPS}, I suices for not ony for voice but aso for video compression, 3. Frequent aecesses and complex instructions may not be needed. {4 The program cannot fit in 4 KB or 8 kB of intemal ROM on-chip, and stack sizes needed inthe program ae big, Instead large ROM and RAM as well s caches are needed, 5. Notloating-poim is needed as mos the it manipulation instvctionsare processed during compeession, Exemplary processors that are snpropriate forthe above case are 80X86 and ARM family processors Example 2.23 6 1. Transfer rates of 100 MHz pls are needed in last switches on a network. Assuming 1D insructions er switching and transceiver ation, nsrution cycle tan is ~ 0.001 pls. A mliprocesor system is needed for GHz transfer aes 2. Let us assume thatthe processor instruction eycle time is 0.01 ps (100 MHz). With 4 five stage pipeline and two-line superscalar architecture, the highest performance wil be 1000 MIPS. [Example 2.11. Multipcocessor system is thus needed for 1000 MHz pus switches 3. The processor should have RISC architectue for single cycle instrction processing at ach ff stage and line. 44. ROM and RAM us well as caches are required, 5. No floating-point is needed as mostly the bts are processed fr 10s. a Exemplary processors that are appropriate forthe above case are ARMT, ARMY and Pentium, Example 2.49 Kearse «en eo 1, Real-time video processing requires fast compression of an image needing use of DSP. Many real-time tasks have to be provessed: for instance, scaling and rotation of images, corections for shadow, colour and hue, image sharpening and filter functions. In such cates, a multiprocessor system with DSP(s) and that has the best processing Exemplary processors that are appropriate for multiprocessor system are ARM integrated with TMS family DSP(S) or ARMII or TigerSHARC._ jn) Embedded Systems "2.9 “MEMORY SELECTION Once the software designer’ coding s over andthe ROM image fle is ready; the hardware designe is faced withthe questions of what typeof memurv and what sizeof each shouldbe used. Firs a desiya-tble. 2 in Table 28, is built. The memory having the required features and address space is chosen. Following are the case studies. The actual memory requremest is known only after coding s per the design functions and specifications. ROM ond RAM allocations for various segments, data sets and structures willbe avalable from the software design. However. prior estimate ofthe memory type and size equirements can be made {Remember the memory ave avalable as: | KB, 4 XB, 16 KB, 32 KB, 64 KB, 128 KB. 256 KB, S12 KB and IMB. Therefore, when 92 KB of memory is needed, hen a device of 128 KB is selected.) Example 2.20 (a) Case Study ofan Automatic Washing machine Consider an automatic washing machine sytem. Assume that machine isnot saving the pictures and _raphics.(a) An EEPROM first byte is required to store these (wash, rinse cycle I, rinse cle 2 and Eich 10 device has sinc eof sess, Each 10 device alo has tinct tof device registers ~ data ‘registers, conto registers and sas registers. At advice adds, there may be more than one rept Te device adieses depen onthe sytem hardware. Basel on the merry mp with 1 device adresses cst rogram is designed locate the linked abet code file an generate & ROM image.Absolute addressing moe Accelerator Accumulator ane A ames Arithmetic uni reitrs ARM ARM? and ARM Asynchronous serial Auto indes Boe addressing Baud Rate Boot back fla Branch raniher cache Burning us interface unit cise Cote Compaiiliy ‘Keywords and their Definitions Embedded Systems Defie al he ass sin an inst. |ASIC, IP core or FPGA, which sears he cove execution which may so inl the bus interface uit, DMA, ead and write units esr: with thee cores. ‘Areisertht provides input toan ALU and that accuses resins operand from te ALU. Aigh perfomance version of the AMBA used in ARM procs. ‘Aunit to prfom aiimetc and log operations as per theists. [An essed opensource specification fr on-chip intercom that se, ssa framework for SOC designs and IP itary develpnen Regie that hold he input an tpt operands und es with she ALU. |A family of high performance rice cade density ANM?. ARMS. ARMO Ghd ARM Il processors. which are sed in embeded ystans asa chip, or as core inan ASIC Two fii of RISC procestor for an SOC frm ARM and Texas siren ath available in single-chip CPU versions and ia fie esos or embeding at VLSIchip ARM 7 bas Princeton architecture or tie nan emery and ARM fs Harv Architecture. ‘Data byes or fame nt msi uniform phase dtfeencsin serial ‘When after executing a instuction, the index register contents change scat [Adressng an ade from where first element of data suture ts Rate at which ser its are eeivd athe ine ding & UART communication, |Afiash with few sectr sir oan OTP device enable soape of bootup rogram a dat Cache 1 holdin advance the next Sto insbuctons © be exceuel onthe ‘rogram branching to this {A proces in which is tend rom a sin xase fxm to he Is and Os ina device as per input 15 and 05 ‘Aoi ietconect the intel buses with the external buses fr conch, ‘ress and data bi AcomplistedIsraston Set Computer that has ne feature tat provides a big fnsteton set for permiting multiple adéessing modes fr the source and ‘esination operands in an aston. Phe hardware executes he instructions inadiferent number of cycles as prthe adessng ode used inan instruction Usability of codes by vicious generations of xi de composer studio covec Control unit DAA ata cache Device address Device programmer Device programming Derceegier Device Dinytone Digital Pitering Direct address pas beam 8051 and Advanced Processor Achitecures, Memory Organization and Reatword Interfacing | 123 | ‘An IDE for T DSP specific code composing which provides an enviroment ‘ilar to MS Visual C+ consis of te allowing: level (Cs wel DP assembly debugger. compiler, assembly optimise, RISC ke sembly «cde and RISC scheduling for psu pertrance ad eine pote its fle 10 funcions, comprehensive da vsaliztion dpa and GEL erping language based on © ‘A ant for digi xing alter ADC and ater operon ud deci 0 get snag sina using DAC ans ae operons. wedi processing ao or (CCD deve piel an vdeo signals ‘Toconolandsequonceal he processng sons ing an stron excain Direct access aangement for example, pial DAA sei a and out port irc transfering the awlog input and capt wsng Wp 19 | mse ind 7 slave CODECS. (Cachet old the dats in content adresse memory Format Discrete Cosine Tranformation funtion sed in abe of DP fonctions, for ‘exanple, the MPEGIMPEGE compression, A device address sd by processor to access ise of esters. teach ess there maybe one or more device egies A system or unto programing a device by baring-in ROM ine Programing of tts by buring ina mesa of mracontlr or in 3 PLA, PAL. CPLD or any ctr device -Aresstrin dvie for byte, word of dua. fags contol is Several device rege ny have a common ares {A pv or virual uit a as theese f reise dat registers contol reps and suns esters. and which he proceso abiecesiie amen ‘benchmarking program tht measures the performance of & processor for ‘processing integers and strings (characters) I uses a eachasek progr ‘salable nC, Pascal or Java bench a CPU, 20 te pesfoman of he 1OorOS cali. MIPS = 1757 Dirysones ‘A iter for the signals that se DSP functions ‘A ltl usable tes in an stretion, Wis sully the aden page in the memo {A dict memory acess by a contr ital or extra. DMA operons fasta the peripherals and devices of thesyzem obtain access the ster memeries diet, without te proceso comune wander of be byte 1 rmemory block. ‘Dyna RAM, which tess cotinsusly by a device called DRAM refs cvetrle, Once programmes, it auto read and writes the sire st of bis repeatedly by scaming the DRAM menary ce A proces of lining echoes | sina received afer delay and which spetimposes over the eign sige Forerarpl, na hl oat the ils we hear te orignal sound as wel asthe ‘echoed sound, Smal there may be eco in electron iali) eos bewac EPROM erKow Erase tine lead pon arithmetic Flach Flesh losin poi artmeic Hightvel language support Inder register Inrvction cache Insect decoder Iestruction frat ‘usrction quenog ait Instruion register astro 14 Insertion et merece cenit. taal bus Java Aceletor wa MAC unit Master Embedcod Systane pes ol fy Eleni Design Attomaio, EDN Emhadled Herta Conan, ‘Ayn of menory ca byte of which is erable nny ies and Be !mogtanne by inns proranas wells by avi propane A type uf memory tt rsable many dines by UV Hight exposure and Programmable by a device pagar, Time taken for eevee ering Acithete wing signs or unsigned ic ges employing processor registers ‘memory. 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A proceso, device osystem wich syctzonaly or asytchronusly ontos ‘the oupt to several ifeentpocesiers. devices and systems cal sles, 5051 ard Advanced Processor chiecues, Memory Organization ard Rea word itacing | 125 Meese Memory adds reir Memory deta reir Memory management unit Memory map Microarchiecare Noise elimination OMAP 5910 procesor Onchip paral port (On-chip serial por Opcode Perfrmanee beneloarking Piptiving Prec conrol wnt Program couuter Progr flr insracion ROM or oT Pulse accumulator counter "Realtime video procsing ‘The maver cn couse sn ait aes sive fa save hs iinet adres Te avr cnehineturcviveaminpa fiom any sone by cata ist, A highspeed communica niche! Buteod Serial Pur | register hat hast ales fora memoey anit For placing i he bus sing bus itr it A retro he dats for ai a emmy uit ‘unit to mangge he poh, paging and segmentation of memories, ‘A meinory aes allocation table seh tht the map eet he ava Iemory ales for varius uses the pracesor A merery map dines the areses ofthe ROMS and RAM the sysem When proceso actinctare refers specify othe achietransuction Set and programmers models thet aeramicte referee the implemeniation of hase architectures, & processor say have CISC sbiesure wh am RISC meena plementation, rally inetd sgl eompunents A proces tat inintes wc ‘ATI proceso funigue uci in DSP chips of igh peso with ow prover consumption Tho prt a hip which uses Ur send 16 ts ata instance ‘The port na eip ws reeves or sends sisal an instance with 2 fii ate ap Pa te UAT ins byic sin forthe entation ds he proees Htincs the upoa o poee¥s e peronaa o the opcndts Maxie faresatatng he peste of ste ‘Thetis pipsiing also inthe supercross I meas an is ALS “itvilevinton abun. nis tse the poses pth nsoeion isting acaton instante tthe ig rossi ope nh esti is taking plac. Thre maybe mali pipet i apres topos ple ‘A wit ofc insratons in alte a dt ia ance fom tbe mesney ‘A prosssur giver to al he cue insti aie tae eset es fet yea eb “Aninsrucion in wich he pogrom ear onan pie ages ‘ay event a its neal changes Jog pura eee A.gpe of mary which it programmable nce by a device panes OTP sa cuesine prgranmable wen. ‘Account cout the apt pulses during a st neal. Whe wed 63 timer with areal ole vale it factons asa pte wid ltr Pressing of ideo signal such hat alo moins anes ar proceso ‘in atime frame such that cach processed fame maiatns constant phase fees inthe ines hate hem126: Embedded Systems RISC wth CISC furctoualiy +A poceser with RISC inplemeataton but use programs it smart. CISC nase A Re! Israston Set Computer that ison eatuehat provides sal insttion set and permite limited addressing modes forthe source and destination operansinan aint or logic wsrcton The hardware executes ‘etch estrcton ina single eycle Segment register | regis to pont 0 the staf a segs for a program code oF daa stor sting o sock Store [A proceso or device or sytem. which receives the input from the master procenoror device or sytem, This ave ith one having a distinct adress Ed chosen bythe master Special function register ‘A epiaerin $01 forspeil ution of ccunultor dpi, ime coma timer ae, seri buler ell consol, power down contol. prs. et Stock pointer A regatrtht hold anaes to define the availabe me mary sesso where the proceso can push the egters and variables 0 sack operation ad rom ere they canbe popped Stock A block to memory that hols the psbe valus Foran first-out data transfer ‘on popping bck he values Supercar processor A processor with the capacity to fetch, decode and exeoue more than one Gsrcion npr tan stan. ‘Synchronous communication + Dutabyesorramesmintsin vom phe derenees inser communication. System reister Processor regis Thunb? insraeton set Aniston st ia which ach nstuton i of 16 bison 232: proceso. Ie ves redoed cae deny ks Gs isto et which ensles32-it Pevfronce at 86-bit system cow. They ze wed by ARM procesor. Timing diagram ‘agatha eft the elatve ine itr ofthe signal on the exter buses with spect wth processor clock pues Video accelerator Am aceertor forthe video out Wochdog Timer tines whichis setinadsance ant pogramcoete maesuchthais overow indicates that 2 proces ic tuck same where std therefore the processor resets sn estan Review Questions 1. Exlpin 8051 acitecturalfestares, What ae the devices iterally presen! inthe else BSI. How do ye inerface a frorammable peripheral interac in 8051? Desert serial interac, inecouners and inteape in 01 Describe eal-erditertacng. Explain interfacig to keybon Compare memory-mapped 10 and 10-napped 10s “What sre the common srt unis in mos processors? Compe Harvard and Poncsen memory organizations. ‘What are te Special stra! wien proceso for gil camera systems, rea ime vdeo procensing systems speech compresion systems, voce compresion ystems and veo games 051 and Advanced Processor Aehtectses, Memory Organization and Rea‘woietacng | 127 How do having prt caches fo incon, dt and branch hp 9 What see advantage ving nly ache wis 0th nl ht x pat of he ache wii activated, which has the aecowiy ac exces sions Lis or xen process with ultway ace. 10. Wh do you sd MAC ut at a proces inthe seni? 1, Esplin tree sage pipeline, supencaler procesing and rach aoa pendency pestis 1 What ae te vantages in Harvard architecture? Why i the ee of acing ck sd dt table a progran tvemory les in Harve memory cite compare Praccten tenn aiete” 1. xpain he perormance mewes of proc: MIPS. MFLOPS a Dhzyums pe seca 14 Why should pros eve no functions oats er modules aes placed incre memory blocks 15, How dothe ARM7. ARM, ARM If nd SwongAvn ifr! When wl yo pofer ARMY, when ARM9 al when ARM? 16, How does a memaxy nap help in designing oar progr? 17 What do youre byte ems: Quan CIF, EDO RAM. RDRAM pexpherl eamsatons sever shadow segment ‘on-chip DMAC and tine-vison mules 18 How ds decoder help memory and 1 device ieracing! Draw fur erly cuts Practice Exercises as 19. Draw the memeryeranzation in 8051 20. il you ase am 8S to for server in a oho asin incre and pon of HOST? 2A, Atwo by dc mas mules By ante by two mati, dt ran th 3 esr oer kes 2m ulin tan 210 al lpi tke 0 mat wl ee enecton Gime? How wa MAC uni ily. Ase ht hse times ate sarin DSP witha MAC wi 22, Anaya 1 imegers cach of 3 is Letaniteger be ao sind in he tay muti hy 1024 Let tbe tase ahs in immary be G40 How wl he is Be fred or te OP, 4 and 9® ln a ig-saian sate () ite ode? 3 Weean aku tt he mem of an ene system is als a deve List dhe rier ike aces cota egies andthe cone of Virtual le aed RAM dsk deve 24, Nowudhyshih-perfomnee ented sen we eter a0 RISC praesor or pacer with an RISC ce with eade-opiniaed CISC neton xe Why? 25. A circular qaeue hs [carter the memory ables, ach of 2s What wl Be he ta meron pace equi. nluding the spe fr hath tbe ste pons? 26, Esme the menny sequent fra 00mage dita carera when the esoton fa) 1024 x 768 pels (6) 640 40. 20 240 and 16D 20 pce ad ech mage sles n compres pe fort. 27. Whatarethe spec retwal unite processors fr digital ee elsime video processing. speech compression and video game stn? ss fr, (Him: Use of