Lecture 390 – Open-Loop Comparators (4/8/02) Page 390-1

LECTURE 390 – OPEN-LOOP COMPARATORS

(READING: AH – 461-475)
Objective
The objective of this presentation is:
1.) Show other types of continuous-time, open-loop comparators
2.) Improve the performance of continuous-time, open-loop comparators
Outline
• Push-pull comparators
• Comparators that can drive large capacitors
• Autozeroing techniques
• Comparators using hysteresis
• Summary

ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 390 – Open-Loop Comparators (4/8/02) Page 390-2

Push-Pull Comparators
Clamped:
VDD

M4 M6

M3 M8
vout
- M1 M2
vin CL
+
M5
+ M9 M7
VBias
-
VSS Fig. 8.3-1
Comments:
• Gain reduced → Larger input resolution
• Push-pull output → Higher slew rates

ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 390 – Open-Loop Comparators (4/8/02) Page 390-3

Push-Pull Comparators - Improved

Cascode output stage:
VDD

M4 M6
M15
M3 M8
M14 M7

R1 R2 vout
- M1 M2 M9
vin M12 CII
+ M10
M5 M11
+ M13
VBias
-
VSS Fig. 8.3-2

Comments:
• Can also use the folded cascode architecture
• Cascode output stage result in a slow linear response (dominant pole is small)
• Poorer noise performance
ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 390 – Open-Loop Comparators (4/8/02) Page 390-4

Comparators that Can Drive Large Capacitive Loads

VDD

M8 M10
M3 M4
M6
- M1 M2 vout
vin
+ CII
+ M7 M9 M11
VBias M5
-
VSS Fig. 8.3-3
Comments:
• Slew rate = 3V/µs into 50pF
• Linear rise/fall time = 100ns into 50pF
• Propagation delay time ≈ 1µs
• Loop gain ≈ 32,000 V/V

ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 390 – Open-Loop Comparators (4/8/02) Page 390-5

Self-Biased Differential Amplifier†

VDD
VDD
VBias M6 Extremely
M6 large sourcing
M3 M4 current
M3 M4
vout
vin+ vin- vin+ vin-

M1 M2
M1 M2
M5
VBias M5
VSS Fig. 8.3-4
VSS
Advantage:
Large sink or source current with out a large quiescent current.
Disadvantage:
Poor common mode range (vin+ slower than vin-)

†
M. Bazes, “Two Novel Full Complementary Self-Biased CMOS Differential Amplifiers,” IEEE Journal of Solid-State Circuits, Vol. 26, No. 2, Feb.
1991, pp. 165-168.
ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 390 – Open-Loop Comparators (4/8/02) Page 390-6

Autozeroing Techniques
Use the comparator as an op amp to sample the dc input offset voltage and cancel the
offset during operation.
Ideal Ideal Ideal
Comparator Comparator Comparator
vIN
- - - vOUT
+ + - +
VOS VOS CAZ VOS + VOS
+ VOS
-C
AZ

Model of Comparator. Autozero Cycle Comparison Cycle

Fig. 8.4-1

Comments:
• The comparator must be stable in the unity-gain mode (self-compensating comparators
are good, the two-stage op comparator would require compensation to be switched in
during the autozero cycle.)
• Complete offset cancellation is limited by charge injection

ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 390 – Open-Loop Comparators (4/8/02) Page 390-7

Differential Implementation of Autozeroed Comparators

φ1Ideal
vIN-
+ - vOUT = VOS
Comparator VOS
φ2 - +
- vOUT
φ1 VOS
vIN+ + Comparator during φ1 phase
φ2 VOS vIN - - vOUT
CAZ φ1 +
vIN+ + -
VOS VOS
Differential Autozeroed Comparator Comparator during φ2 phase
Fig. 8.4-2

ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 390 – Open-Loop Comparators (4/8/02) Page 390-8

Single-Ended Autozeroed Comparators

Noninverting:
φ2 - φ1
φ1 CAZ vOUT
vIN +
φ2
φ1
Fig. 8.4-3
Inverting:

CAZ
vIN vOUT
φ2 - φ1
φ1 +
Fig. 8.4-4

Comment on autozeroing:
Need to be careful about noise that gets sampled onto the autozeroing capacitor and is
present on the comparison phase of the process.

ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 390 – Open-Loop Comparators (4/8/02) Page 390-9

Influence of Input Noise on the Comparator

Comparator without hysteresis:
Comparator vin
threshold
t

vout
VOH

t
VOL Fig. 8.4-6A
Comparator with hysteresis:
vin
VTRP+
t
VTRP-

vout
VOH

t
VOL
Fig. 8.4-6B
ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 390 – Open-Loop Comparators (4/8/02) Page 390-10

Use of Hysteresis for Comparators in a Noisy Environment

Transfer curve of a comparator with hysteresis:
vOUT vOUT
VOH VOH

VTRP+ R1 (V -V )
R2 OH OL VTRP+
vIN 0 vIN
0
VTRP- VTRP-
VOL VOL

Counterclockwise Bistable Clockwise Bistable Fig. 8.4-5

Hysteresis is achieved by the use of positive feedback

• Externally
• Internally

ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 390 – Open-Loop Comparators (4/8/02) Page 390-11

Noninverting Comparator using External Positive Feedback

Circuit: vOUT
V OH

R2
R1 (V -V ) R1VOH
vIN R1 R2 OH OL
+ vOUT 0 R2
vIN
- R1VOL 0
R2
VOL
Fig. 8.4-7
Upper Trip Point:
Assume that vOUT = VOL, the upper trip point occurs when,
 R1   R2  R1
0 = R1+R2VOL + R1+R2VTRP+
 
→ VTRP+ = - R2 VOL
   

Lower Trip Point:

Assume that vOUT = VOH, the lower trip point occurs when,
 R1   R2  R1
0 = R +R VOH + R +R VTRP- → V TRP
-=-
R2 VOH
 1 2  1 2
Width of the bistable characteristic:
 R1
 
∆Vin = VTRP+-VTRP- = R  VOH -VOL
 2

ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 390 – Open-Loop Comparators (4/8/02) Page 390-12

Inverting Comparator using External Positive Feedback

Circuit:
vOUT
VOH
vIN - vOUT R1 (V -V )
+ R1+R2 OH OL
0 vIN
0
R2 R1VOL R1VOH
R1 R1+R2
R1+R2 VOL

Fig. 8.4-8
Upper Trip Point:
R 
 1 
vIN = VTRP = R +R VOH
+  
 1 2
Lower Trip Point:
R 
 1 
vIN = VTRP = R +R VOL
-  
 1 2
Width of the bistable characteristic:
 R1 
 
∆Vin = VTRP -VTRP = R +R  VOH -VOL
+ -
 1 2
ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002
Lecture 390 – Open-Loop Comparators (4/8/02) Page 390-13

Horizontal Shifting of the CCW Bistable Characteristic

Circuit:
vOUT R1 (V -V )
VOH R2 OH OL
R2
R1 R1+R2
vIN
+ vOUT R2 VREF
0 vIN
- 0 R1|VOL|
VREF R1VOH R2
R2
VOL
Fig. 8.4-9

Upper Trip Point:

 R1   R2   R1+R2 R1
VREF = R +R VOL + R +R VTRP+ → VTRP+ =  R2 VREF - R2 VOL
 1 2  1 2  

Lower Trip Point:

 R  R  R +R  R1
1  2  1 2
VREF = R +R VOH + R +R VTRP- → VTRP- =  R VREF - R VOH
 1 2  1 2  2  2
Shifting Factor:
 R1+R2
 
 R V
2  REF

ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 390 – Open-Loop Comparators (4/8/02) Page 390-14

Horizontal Shifting of the CW Bistable Characteristic

Circuit:
vOUT R1 (V -V )
vIN - vOUT R1+R2 OH OL
+ VOH
R1
R2 R1+R2VREF
R1 0 vIN
0 R1VOH
VREF R1|VOL| R1+R2
R1+R2
VOL
Fig. 8.4-10
Upper Trip Point:
R 1   R1 
vIN = VTRP + = R +R VOH + R1+R2V REF

 
 1 2  

Lower Trip Point:



R 1   R
 1 
vIN = VTRP - = R +R VOL + R1+R2V REF
 
 1 2  

Shifting Factor:
 R1 
 
 R +R  VREF
 1 2
ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002
Lecture 390 – Open-Loop Comparators (4/8/02) Page 390-15

Example 8.4-1 Design of an Inverting Comparator with Hysteresis

Use the inverting bistable to design a high-gain, open-loop comparator having an
upper trip point of 1V and a lower trip point of 0V if VOH = 2V and VOL = -2V.
Solution
Putting the values of this example into the above relationships gives
R1 
  R1 
1 = R1+R2 2 + R1+R2VREF


   

and
 R1   R1 
0 = R1+R2 (-2) + R1+R2VREF
   

Solving these two equations gives 3R1 = R2 and VREF = 2V.

ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 390 – Open-Loop Comparators (4/8/02) Page 390-16

Hysteresis using Internal Positive Feedback

Simple comparator with internal positive feedback:
VDD

IBias M3 M6 M7 M4
vo1 vo2

vi1 M1 M2 vi2

M8 M5

Fig. 8.4-11
VSS

ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 390 – Open-Loop Comparators (4/8/02) Page 390-17

Internal Positive Feedback - Upper Trip Point

VDD
Assume that the gate of M1 is on ground and the
input to M2 is much smaller than zero. The
resulting circuit is:
vo1 M3 M6 M7 M4
M1 on, M2 off → M3 and M6 on, M4 and M7 off. vo2

∴ vo2 is high.
M1 M2
W6/L6 i1 = i3 i2 = i6
M6 would like to source the current i6 = W /L i1 vin
3 3 M5
As vin begins to increase towards the trip point, the I5
current flow through M2 increases. When i2 = i6, Fig. 8.4-12A
VSS
the upper trip point will occur.
 W 6 /L 6   W6/L6 i5
  
∴ i5 = i1+i2 = i3+i6 = i3+W /L i3 = i3 1 + W /L  → i1 = i3 = 1 + [(W /L )/(W /L )]
 3 3  3 3 6 6 3 3
Also, i2 = i5 - i1 = i5 - i3
Knowing i1 and i2 allows the calculation of vGS1 and vGS2 which gives
2i2 2i1
VTRP+ = vGS2 - vGS1 = β2 + VT2 - β1 - VT1

ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 390 – Open-Loop Comparators (4/8/02) Page 390-18

Internal Positive Feedback - Lower Trip Point

Assume that the gate of M1 is on ground and the input VDD
to M2 is much greater than zero. The resulting circuit
is:
vo1 M3 M6 M7 M4
M2 on, M1 off → M4 and M7 on, M3 and M6 off. vo2
∴ vo1 is high.
vi1 vi1
W7/L7 M1 M2
M7 would like to source the current i7 = W /L i2 i1 = i7 i 2 = i4
4 4 vin
As vin begins to decrease towards the trip point, the I5
current flow through M1 increases. When i1 = i7, the M5
Fig. 8.4-12B
lower trip point will occur. VSS
 W 7 /L 7   W7/L7
  
∴ i5 = i1+i2 = i7+i4 = W /L i4 +i4 = i4 1 + W /L 
 4 4  4 4
i5
→ i2 = i4 = 1 + [(W /L )/(W /L )]
7 7 4 4
Also, i1 = i5 - i2 = i5 - i4
Knowing i1 and i2 allows the calculation of vGS1 and vGS2 which gives
2i2 2i1
VTRP- = vGS2 - vGS1 = β2 + VT2 - β1 - VT1
ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002
Lecture 390 – Open-Loop Comparators (4/8/02) Page 390-19

Example 8.4-2 - Calculation of Trip Voltages for a Comparator with Hysteresis

Consider the circuit shown. Using the VDD
transistor device parameters given in Table
3.1-2 calculate the positive and negative M3 M6 M7 M4
IBias
threshold points if the device lengths are all 1
µm and the widths are given as: W1 = W 2 = W 6 vo1 vo2
= W 7 = 10 µm and W 3 = W 4 = 2 µm. The gate
of M1 is tied to ground and the input is the vi1 M1 M2 vi2
gate of M2. The current, i5 = 20 µA
Solution
M8 M5
To calculate the positive trip point,
Fig. 8.4-11
assume that the input has been negative and is VSS
heading positive.
(W/L)6 i5 20 µA
i6 = (W/L)3 i3 = (5/1)(i3) → i3 = 1 + [(W/L)6/(W/L)3] = i1 = 1 + 5 = 3.33 µA
 2i1 1/2  2·3.33  1/2
i2 = i5 − i1 = 20 − 3.33 = 16.67 µA → vGS1 =  β1  +VT1 = (5)110 +0.7 = 0.81V
 2i2 1/2  2·16.67 1/2
vGS2 =  β2  + VT2 =  (5)110  + 0.7 = 0.946V
∴ VTRP+ ≅ vGS2−vGS1 = 0.946−0.810 = 0.136V

ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 390 – Open-Loop Comparators (4/8/02) Page 390-20

Example 8.4-2 - Continued

Determining the negative trip point, similar analysis yields
i4 = 3.33 µA
i1 = 16.67 µA
vGS2 = 0.81V
vGS1 = 0.946V
VTRP- ≅ vGS2 − vGS1 = 0.81 − 0.946 = −0.136V
PSPICE simulation results of this circuit are shown below.
2.6

2.4
2.2
2
vo2
1.8
(volts)
1.6

1.4
1.2
1
-0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5
vin (volts) Fig. 8.4-13

ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 390 – Open-Loop Comparators (4/8/02) Page 390-21

Complete Comparator with Internal Hysteresis

VDD

IBias M3 M6 M7 M4

M9 M8

vi1 vi2
M1 M2 vout

M10 M11
M8 M5

VSS Fig. 8.4-14

ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 390 – Open-Loop Comparators (4/8/02) Page 390-22

Schmitt Trigger
The Schmitt trigger is a circuit that has better defined switching points.
Consider the following circuit:
VDD How does this circuit work?
Assume the input voltage, vin, is low and the output
M5 voltage, vout , is high.
∴ M3, M4 and M5 are on and M1, M2 and M6 are off.
M4 When vin is increased from zero, M2 starts to turn on causing
vin M3 vout M3 to start turning off. Positive feedback causes M2 to turn
on further and eventually both M1 and M2 are on and the
M6
M2 output is at zero.
The upper switching point, VTRP+ is found as follows:
M1 When vin is low, the voltage at the source of M2 (M3) is
vS2 = VDD-VTN3
Fig. 8.4-15
VTRP+ = vin when M2 turns on given as VTRP+ = VTN2 + vS2
VTRP+ occurs when the input voltage causes the currents in M3 and M1 to be equal.

ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 390 – Open-Loop Comparators (4/8/02) Page 390-23

Schmitt Trigger – Continued

Thus, iD1 = β1( VTRP+ - VTN1)2 = β3( VDD - vS2- VTN3) 2 = iD3
which can be written as, assuming that VTN2 = VTN3,
VTN1 + β3/β1 VDD
β1( VTRP+ - VTN1) 2 = β3( VDD – VTRP+)2 ⇒ VTRP+ =
1 + β3/β1
The switching point, VTRP- is found in a similar manner and is:
β5/β6 (VDD - VTP5)
β5( VDD - VTRP- - VTP5)2 = β6( VTRP-)2 ⇒ VTRP- =
1 + β5/β6
The bistable characteristic is, vout
VDD

0 0 vin
VTRP- VTRP+ VDD
Fig. 8.4-16
ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 390 – Open-Loop Comparators (4/8/02) Page 390-24

SUMMARY
• Open-loop, continuous-time comparators can be improved in the areas of:
- Current sinking and sourcing
- Removal of offset voltages
- Removal of the influence of a noisy signal through hysteresis
• Comparators with hysteresis (positive feedback)
- External
- Internal

ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002