NXP’s LPC2148

Peeyush.K.P.
Amrita School of Engineering
Coimbatore
NXP’s LPC2148
Architecture

Peeyush.K.P.
Amrita School of Engineering
Coimbatore
LPC 2148 ARCHITECTURE
LPC 2148 ARCHITECTURE
PHASE LOCKED LOOPS (PLL)
PLL FREQUENCY CALCULATION (CCLK)

FOSC = 10 MHz to 25MHz

CCLK = 10 MHz to Fmax (LPC2148 – 60MHz)
FCCO = 156 MHz to 320 MHz
 Calculation of M and P (Divider) Value
(FOSC = 12 MHz, CCLK = 60 MHz )

M = CCLK / FOSC
M = 60 MHz / 12 MHz = 5

P = FCCO / (2 X CCLK)

Range of FCCO is 156 MHz to 320 MHz.

Substituting FCCO = 156 MHz,
P = 156 MHz / (2 X 60 MHz) = 1.3.
Substituting FCCO = 320 MHz,
P = 320 MHz / (2 X 60 MHz) = 2.67.

Since the value of ‘P’ must be an integer, the integer

between 1.3 and 2.6 is ‘2’.
PCLK FREQUENCY CALCULATION

VPB – VLSI Peripheral Bus

 Steps for PLL Configuration
FOSC = 12 MHz, CCLK = 60MHz, PCLK = 15MHz

1) Enable PLL and Disconnect PLL from CPU and other peripherals
PLL0CON = 0x01;
2) Configure M value and P value
PLL0CFG = 0x24;
3) Feed Sequence for locking to desired frequency
PLL0FEED = 0xAA; PLL0FEED = 0x55;
4) Check whether the PLL0 has locked on to the desired frequency
while( !( PLL0STAT & 0x00000400)); PLOCK = 0
5) Enable (again) PLL and Connect the PLL to CPU
PLL0CON = 0x03;
6) Feed Sequence for connecting the PLL0 as system clock
PLL0FEED = 0xAA; PLL0FEED = 0x55;
7) Configure PCLK at 1/4 frequency of System Clock
VPBDIV = 0x00; CCLK = 60 MHz and PCLK = 15 MHz
1) Enable PLL and Disconnect PLL from CPU and
other peripherals
PLL0CON = 0x01;
PLL Control Register (PLL0CON)

PLL0CON = 0x01;
2) Configure M value and P value
PLL0CFG = 0x24;
PLL Configuration Register (PLL0CFG)

FOSC = 12 MHz, CCLK = 60MHz M = ? -- 5

FCCO = 156 MHz to 320MHz, CCLK = 60MHz P = ? -- 2

 For 214x
FOSC = 10 - 25MHz
Max. CCLK = 60MHz

So Max. MSEL = 6 for 214x

PLL0CFG = 0x24 0 0 1 0 0 1 0 0

2 4
3) Feed Sequence for locking to desired frequency
PLL0FEED = 0xAA; PLL0FEED = 0x55;
PLL Feed Register (PLL0FEED)

PLL0FEED = 0xAA; PLL0FEED = 0x55;

4) Check whether the PLL0 has locked on to the desired
frequency
while( ( PLL0STAT & 0x00000400) == 0); PLOCK = 0

It can also be written as

while(! ( PLL0STAT & 0x00000400));
PLL Status Register (PLL0STAT)

while( !( PLL0STAT & 0x00000400)); PLOCK = 0

5) Enable (again) PLL and Connect the PLL to CPU
PLL0CON = 0x03;
PLL Control Register (PLL0CON)

PLL0CON = 0x03;
6) Feed Sequence for connecting the PLL0 as system clock
PLL0FEED = 0xAA; PLL0FEED = 0x55;
PLL Feed Register (PLL0FEED)

PLL0FEED = 0xAA; PLL0FEED = 0x55;

7) Configure PCLK at 1/4 frequency of System Clock
VPBDIV = 0x00; CCLK = 60 MHz and PCLK = 15 MHz
VPB Divider Register (VPBDIV)

VPBDIV = 0x00;
NXP’s LPC2148
GPIO

Peeyush.K.P.
Amrita School of Engineering
Coimbatore
 PIN DIAGRAM – GPIO
P0 – 30 Pins PORTS
P1 – 16 Pins P0.0 – P0.25
P0.28 – P0.31
P1.16 – P1.31
 STEPS TO BLINK LEDs

1) Set P1.31 to P1.16 as GPIO

PINSEL2 = 0;
2) Set P1.31 to P1.16 as Output Port
IODIR1 = 0xFFFFFFFF;
3) Switch on all LEDs on Port1
IOSET1 = 0XFFFFFFFF;
4) Switch off all LEDs on Port1
IOCLR1 = 0XFFFFFFFF;
 STEPS TO BLINK LEDs

1) Set P1.31 to P1.16 as GPIO

PINSEL2 = 0;
PINSEL2 REGISTER

PINSEL2 = 0;
 STEPS TO BLINK LEDs

2) Set P1.31 to P1.16 as Output Port

IODIR1 = 0xFFFFFFFF;
IODIR1 (Direction Register)

IODIR1 = 0xFFFAFFFF;

1111 1111 1111 1010 1111 1111 1111 1111

LEDs Switches

IODIR1 = 0xFFFFFFFF;
 STEPS TO BLINK LEDs

3) Switch on all LEDs on Port1

IOSET1 = 0XFFFFFFFF;
IOSETx & FIOSETx (IO/FAST IO Register)

IOSET1 = 0XFFFFFFFF;
 STEPS TO BLINK LEDs

4) Switch off all LEDs on Port1

IOCLR1 = 0XFFFFFFFF;
IOCLRx & FIOCLRx (IO/FAST IO Register)

IOCLR1 = 0XFFFFFFFF;
 STEPS TO BLINK LEDs

1) Set P1.31 to P1.16 as GPIO

PINSEL2 = 0;
2) Set P1.31 to P1.16 as Output Port
IODIR1 = 0xFFFFFFFF;
3) Switch on all LEDs on Port1
IOSET1 = 0XFFFFFFFF;
4) Delay
5) Switch off all LEDs on Port1
IOCLR1 = 0XFFFFFFFF;
6) Delay
 Register Summary - GPIO
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PINSEL0 P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PINSEL0 P0.15 P0.14 P0.13 P0.12 P0.11 P0.10 P0.9 P0.8
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PINSEL1 P0.23 P0.22 P0.21 P0.20 P0.19 P0.18 P0.17 P0.16
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PINSEL1 P0.31 P0.30 P0.29 P0.28 P0.27 P0.26 P0.25 P0.24

15 14 13 12 11 4 3 2 1 0
PINSEL2 GPIO/TRACE GPIO/DEBUG SEL
NXP’s LPC2148
UART

Peeyush.K.P.
Amrita School of Engineering
Coimbatore
ARM Vs PC Serial Communication

ARM PC

Tx Rx

Rx Tx

Gnd Gnd

TTL RS232
Logic 1 – 5V Logic 1 – -3V to -15V
Logic 0 – 0V Logic 0 – +3V to +15V
 ARM Vs PC Serial Communication

ARM Max 232 PC

Tx TIN TOUT Tx

Rx ROUT RIN Rx
Gnd
Gnd
Level
Converter
TTL RS232
Logic 1 – 5V Logic 1 – -3V to -15V
Logic 0 – 0V Logic 0 – +3V to +15V
DB9 Connector Details
PIN DIAGRAM – USART 0 & USART 1
 STEPS TO TRANSMIT A CHARACTER
(ARM To PC)

1) Set P0.0 pin as TxD & P0.1 pin as RxD - (USART0)

PINSEL0 = 0x00000005; // Pin Select 0
2) Set 8 bits - no Parity - 1 Stop bit for Txsion & DLAB = 1
U0LCR = 0x83; // Line Control Register
3) Set Baud Rate as 9600 bps - 15MHz VPB Clock (PCLK)
U0DLL = 97; // Divisor Latch LSB
4) Disable Access To Divisor Latches
U0LCR = 0x03; // DLAB = 0 Bit – 7
5) Wait until UART0 ready to send character
while(!(U0LSR & 0x20)); // Line Status Register – THRE
6) Sent a character to UART Transmit Register
U0THR = ‘a’; // Transmit Holding Register
 STEPS TO TRANSMIT A CHARACTER
(ARM To PC)

1) Set P0.0 pin as TxD & P0.1 pin as RxD - (USART0)

PINSEL0 = 0x00000005; // Pin Select 0
 PINSEL0 REGISTER

PINSEL0 = 0x00000005; // USART 0

PINSEL0 = 0x00050000; // USART 1
 STEPS TO TRANSMIT A CHARACTER
(ARM To PC)

2) Set 8 bits - no Parity - 1 Stop bit for Txsion & DLAB = 1

U0LCR = 0x83; // Line Control Register
 U0LCR (Line Control Register)

U0LCR = 0x83 1 0 0 0 0 0 1 1

8 3
 STEPS TO TRANSMIT A CHARACTER
(ARM To PC)

3) Set Baud Rate as 9600 bps - 15MHz VPB Clock (PCLK)

U0DLL = 97; // Divisor Latch LSB
 Baud Rate Calculation
Fractional Baud Rate Generator

Default value of U0DLL = 0x01

Ex 1 : PCLK = 30 Mhz and Required Baud Rate is 9600 bauds.
Start with U0DLM = 0 , DIVADDVAL = 0 and MULVAL = 1
We have PCLK = 30 Mhz = 30 x 106 Hz

We get U0DLL = 195.3125 , since it must be an integer we use 195. ie.

U0DLL = 195
On substi. U0DLL = 195 in Baud Rate equation,
Baud Rate = 9615.38, Error = +15.28 from 9600.
Error - as low as possible by adjusting MULVAL and DIVADDVAL.
Max. value of MULVAL & DIVADDVAL is 15.

Substitute,
MULVAL=15 & DIVADDVAL=1.
We get U0DLL = 183
On substi. U0DLL = 183 in Baud Rate equation,
Baud rate = 9605.53, i.e ~9605!
Final Config,
PCLK = 30 x 106 Hz
U0DLL = 183
U0DLM = 0
MULVAL = 15
DIVADDVAL = 1
Ex 2 : PCLK = 60 Mhz and Required Baud Rate is 9600 bauds.
Start with U0DLM = 0 , DIVADDVAL = 0 & MULVAL = 1 with PCLK = 60
x 106 Hz

We get U0DLL = 390.625 (i.e. ~390 )

But U0DLL is 8-bit!
So, we set U0DLM = 1 and find U0DLL.
New U0DLL = 135
Substi. U0DLM and DLL in Baud Rate equation,
Baud Rate = 9590.79, Error = -9.21.
Substitute,
MULVAL = 15
New U0DLL = 110
Substi. New U0DLL in Baud Rate equation,
Baud Rate = 9605.53 which is ~9605!
Final Config,
PCLK = 60 x 106 Hz
U0DLL = 110
U0DLM = 1
MULVAL = 15
DIVADDVAL = 0
 Baud Rate Calculation
Fractional Baud Rate Generator

USART0Baudrate = 9600 bps

PCLK = 15 MHz
U0DLM = 0
MulVal = 1
DivAddVal = 0
U0DLL = ?

U0DLL = 97;
STEPS TO TRANSMIT A CHARACTER
(ARM To PC)

4) Disable Access To Divisor Latches

U0LCR = 0x03; // DLAB = 0 Bit – 7
 U0LCR (Line Control Register)

U0LCR = 0x03 0 0 0 0 0 0 1 1

0 3
 STEPS TO TRANSMIT A CHARACTER
(ARM To PC)

5) Wait until UART0 ready to send character

while((U0LSR & 0x20) == 0); // Line Status Register – THRE = 0

It can also be written as while(!(U0LSR & 0x20) );

 U0LSR (Line Status Register)

U0LSR & 0x20 0 0 THRE 0 0 0 0 0

2/0 0
STEPS TO TRANSMIT A CHARACTER
(ARM To PC)

6) Sent a character to UART Transmit Register

U0THR = ‘a’; // Transmit Holding Register
 STEPS TO RECIEVE A CHARACTER
(PC To ARM)

1) Set P0.0 pin as TxD & P0.1 pin as RxD - (USART0)

PINSEL0 = 0x00000005; // Pin Select 0
2) Set 8 bits - no Parity - 1 Stop bit for Txsion & DLAB = 1
U0LCR = 0x83; // Line Control Register
3) Set Baud Rate as 9600 bps - 15MHz VPB Clock (PCLK)
U0DLL = 97; // Divisor Latch LSB
4) Disable Access To Divisor Latches
U0LCR = 0x03; // DLAB = 0 Bit – 7
5) Wait until UART0 ready with the received Data
while(!(U0LSR & 0x01)); // Line Status Register – RDR
6) Read the received Data from U0RBR
data = U0RBR; // Receive Buffer Register
5) Wait
until UART0 ready with the received Data
while(!(U0LSR & 0x01)); // Line Status Register – RDR = 0
 U0LSR (Line Status Register)

U0LSR & 0x01 0 0 0 0 0 0 0 RDR

0 1/0
6) Read the received Data from U0RBR
data = U0RBR; // Receive Buffer Register
 Register Summary - UART
7 6 5 4 3 2 1 0

U0RBR

U0THR
U0DLL
U0DLM
Tx Fifo
U0FCR Rx Trigger Rx Fifo Rst Rx Enable
Reset

Sticky Even Parity No. of

U0LCR DLAB Set Break Word Length Select
Parity Par.Sel Enable StopBit

Rx
U0LSR TEMT THRE BI FE PE OE RDR
FIFOEr
U0FDR MulVal DivAddVal
UOTER TXEN
NXP’s LPC2148
ADC

Peeyush.K.P.
Amrita School of Engineering
Coimbatore
PIN DIAGRAM – ADC 0

ADC0 1:4 & ADC0 6:7

6 Channels
10 Bit
 1) Set P0.30 pin as AD0.3 (ADC Input Pin for ADC Channel 3)
PINSEL1 &= 0xDFFFFFFF; // xx01 01xx xxxx xxxx xxxx xxxx xxxx xxxx
STEPS FOR AD CONVERSION
PINSEL1 |= 0x10000000; // xx01 xxxx xxxx xxxx xxxx xxxx xxxx xxxx
2) Enable Power/Clock to ADC 0
PCONP |= (unsigned long)(0x00000001) << 12; // Power Control for Periph.
3) Select ADC Channel 3 (AD0.3)
AD0CR |= 0x00000008; // Control Register (Bits 7:0)
4) Set ADC Clock as VPB or (PCLK) / 8
AD0CR |= 0x00000700; // CLKDIV = 00000111 (Bits 15:8)
5) Disable Burst Mode
AD0CR &= 0xFFFEFFFF; // Busrt = 0 (Bit 16)
6) Set Resolution as 10 bit in 11 Clock Cycles
AD0CR &= 0xFFF1FFFF; // CLKS = 000 (Bits 19:17)
7) Activate ADC Module
AD0CR |= 0x00200000; // PDN = 1 (Bit 21)
10) Start the Conversion Now
AD0CR |= 0x01000000; // START = 001 (Bits 26:24)
11) Wait ADC Conversion to Complete (Global Data Register)
while ((AD0GDR & 0x80000000) == 0); // DONE = 1 (Bit 31)
12) Read ADC Data Register
val = (AD0DR3 >> 6) & 0x000003FF; // RESULT = 10 Bit Data (15:6)
13) Deactivate ADC Module (No Start)
AD0CR &= 0xF8FFFFFF; // START = 000 (Bits 26:24)
 STEPS FOR AD CONVERSION

1) Set P0.30 pin as AD0.3 (ADC Input Pin for ADC Channel 3)
PINSEL1<29:28> = 01

PINSEL1 &= 0xDFFFFFFF; // 11 0 1 1111 1111 1111 1111

1111 1111 1111
PINSEL1 |= 0x10000000; // 000 1 0000 0000 0000 0000
0000 0000 0000

Clear Set Split a Bit

1111 1101 1111

& 1101 | 0010 & 0010
1101 1111 0010
 PINSEL1 REGISTER

Bit Clear/Set

11100101
&11111011
11100001
| 00000010
11100010

11100101
| 00000010
11100110

ADC Channel 3 – AD0.3

PINSEL1 |= 0x10000000; // xx01 xxxx xxxx xxxx xxxx xxxx xxxx xxxx
 STEPS FOR AD CONVERSION

2) Enable Power/Clock to ADC 0

PCONP |= (unsigned long)(0x00000001) << 12; // Power
Control for Periph.
PCONP (Power Control for Peripherals)

1 0 0 0 0 0 0 0 0 0 0 0 0

PCONP |= (unsigned long)(0x00000001) << 12;

 STEPS FOR AD CONVERSION

3) Select ADC Channel 3 (AD0.3)

AD0CR |= 0x00000008; // Control Register (Bits 7:0)
 AD0CR (Control Register)

00000001 AD0.0 (ADC0 Channel 0)

00000010 AD0.1 (ADC0 Channel 1)
00000100 AD0.2 (ADC0 Channel 2)
00001000 AD0.3 (ADC0 Channel 3)
00010000 AD0.4 (ADC0 Channel 4)
00100000 AD0.5 (ADC0 Channel 5)
01000000 AD0.6 (ADC0 Channel 6)
10000000 AD0.7 (ADC0 Channel 7)

AD0CR |= 0x00000008;
 STEPS FOR AD CONVERSION

4) Set ADC Clock as VPB or (PCLK) / 8

AD0CR |= 0x00000700; //CLKDIV = 00000111 (Bits 15:8)
 AD0CR (Control Register)

00000000 ADC Clock = (PCLK)/1

00000001 ADC Clock = (PCLK)/2
00000010 ADC Clock = (PCLK)/3
00000011 ADC Clock = (PCLK)/4
00000100 ADC Clock = (PCLK)/5
00000101 ADC Clock = (PCLK)/6
00000110 ADC Clock = (PCLK)/7
00000111 ADC Clock = (PCLK)/8
………………………………………………………

AD0CR |= 0x00000700;
 STEPS FOR AD CONVERSION

5) Disable Burst Mode

AD0CR &= 0xFFFEFFFF; // Busrt = 0 (Bit 16)
AD0CR (Control Register)

AD0CR &= 0xFFFEFFFF;

 STEPS FOR AD CONVERSION

6) Set Resolution as 10 bit in 11 Clock Cycles

AD0CR &= 0xFFF1FFFF; //CLKS = 000 (Bits 19:17)
AD0CR (Control Register)

AD0CR &= 0xFFF1FFFF;

 STEPS FOR AD CONVERSION

7) Activate ADC Module

AD0CR |= 0x00200000; // PDN = 1 (Bit 21)
AD0CR (Control Register)

AD0CR |= 0x00200000;
 STEPS FOR AD CONVERSION

8) Start the Conversion Now

AD0CR |= 0x01000000; // START = 001 (Bits 26:24)
AD0CR (Control Register)

AD0CR |= 0x01000000;
 STEPS FOR AD CONVERSION

9) Wait ADC Conversion to Complete (Global Data Register)

while ((AD0GDR & 0x80000000) == 0);
// DONE = 1 (Bit 31)
AD0GDR (Global Data Register)

while ((AD0GDR & 0x80000000) == 0);

 STEPS FOR AD CONVERSION

10)Read ADC Data Register

val = (AD0DR3 >> 6) & 0x000003FF;
// RESULT = 10 Bit Data (15:6)
AD0DR3 (Data Register)

val = (AD0DR3 >> 6) & 0x000003FF;

 STEPS FOR AD CONVERSION

11)Deactivate ADC Module (No Start)

AD0CR &= 0xF8FFFFFF;
// START = 000 (Bits 26:24)
AD0CR (Control Register)

AD0CR |= 0x01000000;
 Register Summary - ADC
31 19
27 26 24 21 16 15 8 7 0
28 17

AD0CR START PDN CLKS BURST CLKDIV SEL

2
3
31 30 26 24 15 6 5 0
1
6

AD0GDR DONE OVERRUN CHN RESULT

31 13 12 11 0

PCONP PCAD0
NXP’s LPC2148
External
Interrupts

Peeyush.K.P.
Amrita School of Engineering
Coimbatore
 PIN DIAGRAM – External Interrupts
EINT0 - P0.1, P0.16
EINT – 9 Pins EINT1 - P0.3, P0.14
EINT2 - P0.7, P0.15
EINT3 - P0.9, P0.20, P0.30
Steps to Control an Led with External Interrupt
1) Configure P0.14 as EINT1
PINSEL0<29:28> = 10
2) Configure Edge Sensitive/Level Sensitive Interrupt for EINT1
EXTMODE<1> = 1 (Edge Sensitive)
3) Configure Rising/Falling Edge Sensitive Interrupt for EINT1
EXTPOLAR<1> = 0 (Falling)
4) Clear EINT1 Interrupt Flag Bit
EXTINT<1> = 1
5) Configure EINT1 (Interrupt No. 15) as FIQ/IRQ
VICIntSelect<15> = 0 (IRQ)
6) Enable EINT1 Interrupt
VICIntEnable<15> = 1
7) Configure the Interrupt No. of Interrupt Request assigned to
Vectored IRQ Slot (IRQ Slot 5)
VICVectCntl5<4:0> = 1111 (Decimal 15)
8) Enable Vectored IRQ Slot (IRQ Slot 5)
VICVectCntl5<5> = 1
9) Configure ISR Vector Address to VIC IRQ Slot
VICVectAddr5 = (unsigned int)Ext_ISR;
 1) Configure P0.14 as EINT1
PINSEL0<29:28> = 10

PINSEL0 = (PINSEL0 & 0xCFFFFFFF) | (1 << 29);

First make Bit 28 & 29 as '0' then make Bit 29 as '1'

Clear Set Split a Bit

1111 1101 1111

& 1101 | 0010 & 0010
1101 1111 0010
PINSEL0 REGISTER
External Interrupt Registers
External Interrupt Registers
2) Configure Edge Sensitive/Level Sensitive
Interrupt for EINT1
EXTMODE<1> = 1 (Edge Sensitive)

EXTMODE = 0x2;
External Interrupt Mode Register (EXTMODE)
3) Configure Rising/Falling Edge Sensitive Interrupt
for EINT1
EXTPOLAR<1> = 0 (Falling)

EXTPOLAR &= 0xFFFFFFFD;

External Interrupt Polarity Register (EXTPOLAR)
4) Clear EINT1 Interrupt Flag Bit
EXTINT<1> = 1;

EXTINT |= 0x2;

Flag bit is cleared by writing ‘1’ to it.

External Interrupt Flag Register (EXTINT)
External Interrupt Flag Register (EXTINT)
VIC Registers
VIC Registers
5) Configure EINT1 (Interrupt No. 15) as FIQ/IRQ
VICIntSelect<15> = 0 (IRQ)

VICIntSelect &= 0xFFFF7FFF;

VIC Interrupt Select Register (VICIntSelect)
6) Enable EINT1 Interrupt
VICIntEnable<15> = 1

VICIntEnable = 1<<15;
VIC Interrupt Enable Register (VICIntEnable)
7) Configure Interrupt No. of EINT1 (15) to
Vectored IRQ Slot (IRQ Slot 5)
VICVectCntl5<4:0> = 1111 (Decimal 15)

VICVectCntl5 = 15;
VIC Vector Control Registers (VICVectCntl0-15)
8) Enable Vectored IRQ Slot (IRQ Slot 5)
VICVectCntl5<5> = 1

VICVectCntl5 |= 1<<5;
VIC Vector Control Registers (VICVectCntl0-15)
9) Configure ISR Vector Address to VIC IRQ Slot
VICVectAddr5 = (unsigned int)Ext_ISR;

ISR should have “__irq” as the keyword.

void Ext_ISR() __irq
VIC Vector Address Registers (VICVectAddr0-15)
 External Interrupt Registers
31 - 4 3 2 1 0
EXTMODE EXTMODE3 EXTMODE2 EXTMODE1 EXTMODE0
EXTPOLAR EXTPOLAR3 EXTPOLAR2 EXTPOLAR1 EXTPOLAR0
EXTINT EINT3 EINT2 EINT1 EINT0

VIC Interrupt Select and Interrupt Enable Registers

VIC Control and Address Registers

31 - 6 5 4-0
VICVectCntl0-15 IRQSlot_en Int_request
31 - 0
VICVectAddr0-15 IRQ_vector
peeyushkp.in