entity bascule_RS is

port(R,S,H: in std_logic;
Q,Qb: out std_logic);
end bascule_RS;
Architecture arch of bascule_RS is begin
Process(H)
variable x: std_logic;
begin
if(H 'event and H='1') Then
if(S='0' and R='0') Then x:=x;
elsif(S='1' and R='0') Then x:='1';
elsif(S='0' and R='1') Then x:='0';
else x:='0';
end if;
end if;
Q<=x;
Qb<=not x;
end Process;
end arch;