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Implementation and verification of a generic universal memory controller

based on UVM

Conference Paper · April 2015

DOI: 10.1109/DTIS.2015.7127364

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 2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era
(DTIS)
Implementation and Verification of A Generic Universal
Memory Controller Based On UVM
Khaled Khalifa
Alexandria University
Alexandria, Egypt
khaled.khalifa.eg@ieee.org
Abstract‫ ـــــ‬This paper presents a coverage driven constraint
random based functional verification method based on the
Universal Verification Methodology (UVM) using System
Verilog for generic universal memory controller architecture.
This universal memory controller is looking forward to
improving the performance of the existing memory controllers
through a complete integration of the existing memory
controllers features in addition of providing novel features. It
also reduces the consumed power through providing high
power consumption control due to its proposed different
power levels supported to fit all power scenarios. While
implementing a worthy architecture like the proposed generic
universal memory controller, UVM is the best choice to build
well-constructed, high controlled and reusable verification
environment to efficiently verify it. More than 200 coverage
points have been covered to verify the validation of the
integrated features which makes the proposed universal
memory controller replaces the existing controllers on the
scene as it provides all of their powerful features in addition of
novel features to control two of the most dominated types of
memory; FLASH and DRAM through one memory controller.
Index Terms— Universal Memory Controller, low power
Memory Controller, Flash, DRAM, UVM, eMMC, ONFI, One-
NAND, UFS, HMC, WideIO, SSD, Verification Environment.
I. INTRODUCTION
Microprocessors communicate with memory cores
through memory controllers. The main aim of the memory
controllers is to provide the most suitable interface and
protocol between the host and the memories to efficiently
handle data, maximizing transfer speed, data integrity and
information retention. To improve this communication as a
solution for the memory bottleneck, the memory cores and
memory controllers can be improved. The most famous
existing memory controllers–based solution is to improve
the controller architectures and scheduling algorithms. Part
of the idea behind the solution is to unload low-level
memory management from the host processor, freeing up
resources [1]. The proposed memory controller optimizes
the features of the existing memory controllers on the scene
and integrates them in only one generic universal memory
controller. This generic universal memory controller can
replace the existing memory controllers due to its powerful
specifications which can be summarized in these points: (i)
Two dominated types of memory: FLASH and DRAM are
supported. (ii) All the most major, powerful and important
features for any existing memory controller are supported
and designed to be optionally enabled or disabled according
to the manufacturer desire. (iii) High control of power
978-1-4799-1999-4/15/$31.00 ©2015 IEEE
Khaled Salah
Mentor Graphics
Cairo, Egypt
khaled_mohamed@mentor.com
consumption due to different power levels supported to fit
all power scenarios. Our key contribution in this paper is to
provide some implementation and verification details which
are used in creating this universal memory controller.
The rest of paper is organized as follows. In Section II,
some implementation details are presented. In section III,
the architecture of the UVM verification environment is
provided. Results are discussed in section IV. Conclusions
are given in section V.
II. SOME IMPLEMENTATION DETAILS OF THE
UNIVERSAL MEMORY CONTROLLER
The methodology followed to accomplish this generic
universal memory controller architecture was a comparative
study between diverse and famous protocols which are Flex-
OneNAND [2], ONFI [3], eMMC [4], HMC [5], WideIO
[6], and UFS [7].
The interface between the host processor and the proposed
universal memory controller consists of six buses which
enable the host to send/receive to/from the memory
controller serially as shown in Fig.1. The host processor can
also select the desired memory core (FLASH or DRAM)
through the memory core select signal. This universal
memory controller enhances the problem of turning off the
clock to reduce the clock consumed power by a clock enable
signal which has a huge impact on the supported power
levels as shown in Fig.2 [8].
This universal memory controller proposes six different
partitions which are boot, enhanced, system code, high
speed, temporary and the user data area partition to benefit
from the permanent storage of the controlled memory as; for
example; the log feature exploits the high speed partition to
reduce the access consumed power and minimize the access
time of the most frequently used data, and the hibernate
power level in Fig.2 exploits the temporary partition to store
the last status of the universal memory controller before it is
turned off [9]-[10].
CLK
CLK_Enable
Reset Generic
Universal
Host CMD / Response
Memory
Data Bus Controller
Memory Core Select
Fig. 1 The proposed interface of the universal memory controller.
 !

!
VCC, CLKE, CLK IV. RES SULTS
are ON The proposed generic universsal memory controller has
VCC, CLKE, CLK
been implemented by Verilo og hardware description
Stand-By are OFF language and verified based on UVM
U using System Verilog.
(Im
mmediate Termination)
Through the test plan, more than n 200 coverage points have
Reset
Pre-Deep Deep Power been covered. Since all the sign nals are statically available,
Pre-Active
Power Down Down the interesting data signals of o the universal memory
controller interface (Clk, Reset, CMD_Response,
C Data_Bus)
are added to the wave viewer and a looking at their values
over time while the simulation is running as shown in Fig.4.
Pre-Power
Pre-Sleep Active
Down

Power
Sleep Hibernate Down

VCC, CLKE, CLK

VCC (Very Low) are OFF VCC, CLK are ON
CLKE, CLK are OFF (Store Status) CLKE is OFF

Fig.2 The proposed power levels of the universal mem mory controller are
stand-by, active, power down, sleep, hibernate and deep ppower down.

III.
THE ARCHITECTURE OF TH HE UVM
VERIFICATION ENVIRONE EMNET Fig. 4 Wave forms of the interesting signaals of the proposed interface.
The proposed architecture of the UVM M verification
environment for this universal memory conttroller in Fig.3 V. CONCL LUSIONS
shows that there are two different monitors. The expected This paper proposed an implem mentation of a system level
monitor is responsible for getting the expectedd data from the architecture of a generic univ versal memory controller
reference TLM model of the universal mem mory controller. verified by the Universal Verificaation Methodology (UVM).
The other one is responsible for getting the acttual data of the In order to accomplish more inteegrated memory controller;
implemented controller which called actual monitor. Both the proposed implemented mem mory controller incorporates
monitors are connected to the scoreboard throough the TLM the most powerful features from m six diverse protocols to
ports and exports. The two monitors send theirr captured data create a generic universal mem mory controller. It supports
to the scoreboard to be compared which repoorts the success both FLASH and DRAM memorry types to be controlled. It
or fail of the different operations [11]-[12]. also grants to the host processorr the ability of high power
consumption control due to its proposed different power
levels supported to fit all power scenarios, so the
Top controller is keeping up with thee global trend to save more
power and reduce its impact on the performance. The
Test integration used in the proposed d memory controller gives
the manufacturer the ability to use
u it in many applications
Scoreboard
Expected Actual
Enviironment which makes the proposed uniiversal memory controller
Sb_Expected Sb_Actual
replaces the existing controllers on
o the scene.
Agent_Expected Agent_Actual REFERE
ENCES
[1] R. Micheloni, L. Crippa, A. Marellli,"Inside NAND Flash memory,"
A
Agent DATE, 2010.
Mon_Expected Mon_Actual [2] Flex-OneNAND, Revision No 1.1, Au ug.14, 2008.
Monitor Monitor [3] www.onfi.org.
Expected Actual
Seequencer
[4] eMMC Standard (4.51 Device), JED84 4-B451, June 2012.
Seq_item_ex
[5] HMC, Technical Report Revision 1.0, January 2013.
Seq_item_port
[6] Wide I/O Single Data Rate, Revision 1.0,
1 December 2011.
DUT Interface
[7] UFS Standard (V.1.0), JESD220-1, Seep 2013.
DUT
(Main FSM)
Driver [8] Khalifa, K., Fawzy, H., El-Ashry, S., & Salah, K. (2014, May). A novel
REF Model Interface memory controller architecture. In Electrical Engineering/Electronics,
Computer, Telecommunications and d Information Technology (ECTI-
REF TLM CON), 2014 11th International Conference on (pp. 1-4). IEEE.
Model
[9] Khalifa, K., Fawzy, H., El-Ashry, S., & Salah, K. (2014). Memory
controller architectures: A comparaative study. In Design and Test
Symposium (IDT), 2013 8th Internatio
onal (pp. 1-6). IEEE.
[10] Jacob, Bruce, Spencer Ng, and Daviid Wang. Memory systems: cache,
Fig. 3 The proposed architecture of the UVM verificatioon environment for DRAM, disk. Morgan Kaufmann, 2010 0.
the generic universal memory controller. It consists of two monitors, [11] Accellera, UVM 1.0 Reference Manuaal, (2011).
reference TLM model, driver, sequencer, two interfaces aand scoreboard. [12] Accellera, UVM 1.1 User’s Guide, (20
011).

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