Design of Dynamic D-flip flop using umc 135nm
technology in cadence virtuoso
Hem Chaitanya Reddy
T19175
Digital MOS LSI
Instructor: Dr Rahul shrestaa
Date:20 nov 2019
Abstract—In this project, a Dynamic edge-triggered register
using a master-slave configuration is designed and analyzed in
cadence virtuoso.Various timing parameters such as setup time
and hold time are observed by skewing the clock and input
signal concerning each other. different metrics namely robustness,
performance, energy consumption are analyzed for this flip flop.
The layout is successfully designed and its timing parameters,
as well as other parameters, are successfully observed and
simulated.
Index Terms—Flipflop, Edge triggered register ,setuptime, hold
time, insert
I. L ITERATURE SURVEY
The egde triggered register is a sequential logic cir-
cuit.output of combinational circuits is function of current
input only.Virtually all useful systems in present day world
require storage of state information.This isn’t possible with
combinational circuits.This leads to new state of circuits called
as sequential circuits.In this circuits output not only depends
on current values of input but also on preceding values of
input.Generally this are made of latches and flipflops.The
most important competent of sequential circuit is flip flop.It
is designed with either with the help of latches or they
can be directly designed using registers.Latches are leval
sensitive circuits that gives output same as input when it is
in active state,it storess the last output in high impedance
state.Fliflop are bistable component formed by cross coupling
of gates called flipflop. In the above circuit memory elements
Fig. 1. Sequential circuits
refers to either flipflops or registers.The efficent design of
this componet is really important to design many important
components.
II. S TATIC D- FLIP FLOP
A. Latchs and registers
Latch is an essentialcomponent in building the ege triggered
register.It us keval sensitve circuit which passes the D input to
Q output when clock is high(low),is said to be in transparent
mode,when clock is low(high) the input is sampled at the
faling(raising) edge of clock is held stable,is ssaid to be in
hold mode.The latch operating in above mentioned conditions
is called as positive(negitive) latch.
The registers are edge triggered circutis that sampplse the
one input on clock transistion either from 0-¿1 for positive
edge triggerd register or 1¿0 for negitive edge triggerd reg-
ister.Generally we can directly built this ckt or we can use
master slave configaration which is combination of positive
and negitive latches.In this experiment we are going to built
this static masterslave configaration
B. Timing parameters of flipflop
There are three important timing parameters assosiated
with registers.They are setuptime(tsu ,hold time(thold ),worst
case propagation delay(tc−q .Set up time is the time the
data must be valid beforeclock transistion.Hold time is the
time the data must be valid after the clock transistion.The
propagation delayis the worst case delay from D input to Q
output.Every sequential circutis have some constraints called
system leval constraints which impacts the performance of the
ckt.In sequential circuits,next cycle cannot begin unless all
computaion have completed and system comes to rest .Thus
clock period should accomade all the things that system takes
time.So mimimum clock period require for proper operation
of sequential circuits is
T = tc−q + tsu + tc−q
Here tsu is setup time which imposes constraint on clock time
period.Adherence to setup tiimeensures that the data launched
at pervious clock edge is succesfully captured at the currrent
edge.
one more constraint in circuit is hold time.It is given by
tcdregister + tcdlogic ≥thold
where tcd is condatamiantion dela defined as minimum delay.
Adherence to hold time ensures that the data launched at the
current eqge does not get captured at the same edge.
Fig. 2. Sequential circuits
III. DYNAMIC D- FLIPFLOP USING MULTIPLEXER BASED
DESIGN
Dynamic flipflop can be designed using various topolo-
gies.In this experiment Dynamic edgetriggereed register is
designed using tow transmission gates and two inerters as
shown in belwo figure.When CLK = 0 the input node is sam-
pled at node one and which consists of equilvalent capcitence
which includes gate capacitence and diffusion capacitences of
T1.During this period the slaave is in hold mode with node
2 in floating mode.On rising edge of clock,the transmission
gate T2 is in transperent mode and the value sampled on
node 1 before risisng edge clcok proppagtes to output Q.The
implementation of this edge triggered register is very efficient
because it requires eight transistors.For higher performance
and low power systems transmission gates can be replaced by
transmission gates resulting in even simpler six transistor
Fig. 3. Sequential circuits
A. Timing properties
The setuptime of this circuit is simply the delay of transmis-
sion gate and it corresponds to the time it takes node 1 to sam-
ple the D input.The hold time is approximately zero,since the
transmission gate us turned off on the clock edge and further
input changes are further ignored.The propagation delay(tc−q
is equa to two inverter delay plus delay of transmission gate.
B. Disadvantages of this topology
The storage nodes tends to have charge leakage ,diode
laekage or subthresold currents which result in loss of state.We
have to periodically refresh the circuit inorder to prevent above
mentioned losses
Another disadvantage is clock overlap.During (0 − 0) over-
lap,The nmos of T1 and PMOS of T2 are simultaneosuly on
creating race condition.The output Q changes on faling edge
of clock during thsi overlap which is an undesirable effect for
positive edge triggerd register.
Fig. 4. dynamic flipflop
1) Schematic: The above figure is schematic designed in
Virtuso.In this experiment we have to dofollowing analysis
setup time and hold time for both schematic and for also the
layout designed.first we willl analyze the scematic version.
To obtain set up time in cadence we have skew the input with
respect to the clock edge untill the circuit fails.below figure is
the output of the staticflipflop.In that one we have to skew the
data with respect to clk until circuit fails.The point at which
the circuit fails is setuptiem(tsu .The set time is
As mentioned in above section The hold time is 0. The
propagation delay is calculated by mesuring from the 50
percent of clock edge to 50 percent of outputQ. The propation
delay is tpdhl = 28.14pS, tpdlh = 28.14P s we are succesfully
able tocalculate the setuptime and hold time and propagation
delay of schematic successfully.
From above figure we can calculate the delay and power
consumed by the inverter.The delay can be calculated by
calculating tpHL , tpLH and delay is given as tp = (tpHL +
+pLH)/2
tpHL = 28.14ps, tpLH = 26.32ps
tp = 27.16ps
The average power consumed bythis flipflop is 896 nw
succesfully calculated from results. setup time is 9.6 PS
setuptime 10.4ps
Hold time 0
Propagation delay 27.16ps
 Fig. 5. dynamic results

Fig. 7. Results of inverter

Fig. 6. symmetrical VTC

C. Layout
Generally the results we calculated from the schematic will
be differnt from the actual results when we calculate from
realstic flipflop made from silicon.To get the actual results we Fig. 8. Layout for dynamic
will use layout.
In layout we have to check DESIGN RULE CHECK and
layout versus schematic.If we didn’t have any errors we can
proceed to next step that is parasitic extraction(pex analysis)
and attach it to schematic to get layout results.
The width of PMOS and NMOS we will same for layout
as we calculated from schematic. now we have to calculate
the setuptime and propagation delay and power consumed for
layout simulation which will be differnt from actual schematic
version
The delay can be calculated by calculating tpHL , tpLH and
delay is given as tp = (tpHL + +pLH)/2
tpHL = 71ps, tpLH = 54ps
tp = 62.5ps Fig. 9. Layout versus Sche,atic for dynamic inverter
The average power consumed by this Dynamic-flipflop is
829.6n Wand peakpower is 378.8n W Set
IV. C ONCLUSION
From above experiment we are successfully able to calculate
the optimized size for inverter to get maximum noise mar-
gin,minimum delay,and power consumption.The results had
been derived from both the schematic and layout succesfuly

Fig. 10. Layout Result