08-03-2018

Today program

Lexical Conventions
Data Types
Digital System Design System Tasks and Compiler Directives
Verilog® HDL
Basic Concepts

Verilog HDL 2

Lexical Conventions Lexical Conventions (cont’d)

 Very similar to C  Whitespace  Comments

Verilog is case-sensitive Blank space (\b) Used for readability and
All keywords are in lowercase Tab (\t) documentation
A Verilog program is a string of tokens Newline (\n) Just like C:
 Whitespace  // single line comment
 Whitespace is ignored
 Comments  /* multi-line
in Verilog except comment
 Operators
In strings */
 Numbers
When separating /* Nested comments
 Strings /* like this */ may not
tokens
 Identifiers be acceptable (depends
 Keywords on Verilog compiler) */

Verilog HDL 3 Verilog HDL 4

Lexical Conventions (cont’d) Lexical Conventions (cont’d)

Operators Number Specification

Unary Sized numbers
a = ~b; Unsized numbers
Binary Unknown and high-impedance values
a = b && c;
Negative numbers
Ternary
a = b ? c : d; // the only ternary operator

Verilog HDL 5 Verilog HDL 6

1
 08-03-2018

Lexical Conventions (cont’d) Lexical Conventions (cont’d)

 Sized numbers  Unsized numbers  X or Z values
 General syntax:  Default base is decimal  Unknown value: lowercase x
<size>’<base><number>  Default size is at least 32  4 bits in hex, 3 bits in octal, 1 bit in binary
 <size> number of bits (in (depends on Verilog compiler)  High-impedance value: lowercase z
decimal)  Examples  4 bits in hex, 3 bits in octal, 1 bit in binary
 <number> is the number in  23232
radix <base>  Examples
 ’habc  12’h13x
 <base> :
 ’o234  6’hx
• d or D for decimal (radix 10)
• b or B for binary (radix 2)  32’bz
• o or O for octal (radix 8)  Extending the most-significant part
• h or H for hexadecimal  Applied when <size> is bigger than the specified value
(radix 16)
• Filled with x if the specified MSB is x
 Examples: • Filled with z if the specified MSB is z
• 4’b1111
• Zero-extended otherwise
• 12’habc
• 16’d255
 Examples:
• 6’hx

Verilog HDL 7 Verilog HDL 8

Lexical Conventions (cont’d) Lexical Conventions (cont’d)

 Negative numbers  Strings
Put the sign before the <size>  As in C, use double-quotes
 Examples:
Examples:  “Hello world!”
 -6’d3  “a / b”
 4’d-2 // illegal  “text\tcolumn1\bcolumn2\n”
 2’s complement is used to store the value
 Underscore character and question marks  Identifiers and keywords
 identifiers: alphanumeric characters, ‘_’, and ‘$’
Use ‘_’ to improve readability
 Should start with an alphabetic character or ‘_’
 12’b1111_0000_1010  Only system tasks can start with ‘$’
 Not allowed as the first character  Keywords: identifiers reserved by Verilog
‘?’ is the same as ‘z’ (only regarding numbers)  Examples:
 4’b10?? // the same as 4’b10zz  reg value;
 input clk;

Verilog HDL 9 Verilog HDL 10

Lexical Conventions (cont’d)

 Escaped identifiers
Start with ‘\’
End with whitespace (space, tab, newline)
Can have any printable character between start and end Basic Concepts
The ‘\’ and whitespace are not part of the identifier
Examples: Data Types
\a+b-c // a+b-c is the identifier
\**my_name** // **my_name** is the
identifier
Used as name of modules

Verilog HDL 11

2
 08-03-2018

Data Types Value Set

 Value set and strengths Verilog concepts to model hardware

 Nets and Registers circuits
 Vectors Value level
 Integer, Real, and Time Register Data Types Value strength
 Arrays Used to accurately model
• Signal contention
 Memories • MOS devices
 Parameters • Dynamic MOS
• Other low-level details
 Strings

Verilog HDL 13 Verilog HDL 14

Value Set Nets

Value level HW Condition Strength level Type  Used to represent connections between HW elements
supply Driving  Values continuously driven on nets
0 Logic zero, false

1 Logic one, true strong Driving

 Keyword: wire
pull Driving  Default: One-bit values
x Unknown
large Storage  unless declared as vectors
z High imp., floating  Default value: z
weak Driving  For trireg, default is x
medium Storage  Examples
 wire a;
small Storage
 wire b, c;
highz High  wire d=1’b0;
Impedance

Verilog HDL 15 Verilog HDL 16

Registers Vectors
 Registers represent data storage elements  Net and register data types can be declared as
Retain value until next assignment vectors (multiple bit widths)
NOTE: this is not a hardware register or flipflop
 Syntax:
Keyword: reg
wire/reg [msb_index : lsb_index] data_id;
Default value: x
Example:  Example
reg reset; wire a;
initial wire [7:0] bus;
begin
wire [31:0] busA, busB, busC;
reset = 1’b1;
#100 reset=1’b0; reg clock;
end reg [0:40] virtual_addr;
Verilog HDL 17 Verilog HDL 18

3
 08-03-2018

Integer, Real, and Time

Vectors (cont’d) Register Data Types
 Consider  Integer
wire [7:0] bus; Keyword: integer
wire [31:0] busA, busB, busC; Very similar to a vector of reg
reg [0:40] virtual_addr;  integer variables are signed numbers
 reg vectors are unsigned numbers
 Access to bits or parts of a vector is possible:
busA[7] Bit width: implementation-dependent (at least 32-bits)
bus[2:0] // three least-significant bits of bus  Designer can also specify a width:
integer [7:0] tmp;
// bus[0:2] is illegal.
virtual_addr[0:1] /* two most-significant bits Examples:
integer counter;
* of virtual_addr
initial
*/
counter = -1;
Verilog HDL 19 Verilog HDL 20

Integer, Real, and Time Integer, Real, and Time

Register Data Types (cont’d) Register Data Types (cont’d)
 Real
 Keyword: real
Time
 Values: Used to store values of simulation time
 Default value: 0
 Decimal notation: 12.24 Keyword: time
 Scientific notation: 3e6 (=3x106)
 Cannot have range declaration Bit width: implementation-dependent (at least 64)
 Example:
real delta;
$time system function gives current simulation
initial time
begin
delta=4e10; Example:
delta=2.13;
end
time save_sim_time;
integer i; initial
initial
i = delta; // i gets the value 2 (rounded value of 2.13) save_sim_time = $time;

Verilog HDL 21 Verilog HDL 22

Arrays Memories
 Only one-dimensional arrays supported  RAM, ROM, and register-files used many times in digital
 Allowed for reg, integer, time systems
 Not allowed for real data type
 Syntax:  Memory = array of registers in Verilog
<data_type> <var_name>[start_idx : end_idx];  Word = an element of the array
 Examples:
 Can be one or more bits
integer count[0:7];
reg bool[31:0];  Examples:
time chk_point[1:100]; reg membit[0:1023];
reg [4:0] port_id[0:7];
reg [7:0] membyte[0:1023];
integer matrix[4:0][4:0]; // illegal
membyte[511]
count[5]  Note the difference (as in arrays):
chk_point[100]
reg membit[0:127];
port_id[3]
 Note the difference between vectors and arrays reg [0:127] register;
Verilog HDL 23 Verilog HDL 24

4
 08-03-2018

Parameters Strings
 Similar to const in C  Strings are stored in reg variables.
But can be overridden for each module at compile-time  8-bits required per character
 Syntax:  The string is stored from the least-significant part to the
parameter <const_id>=<value>; most-significant part of the reg variable
 Example:
 Gives flexibility reg [8*18:1] string_value;
Allows to customize the module initial
 Example: string_value = “Hello World!”;
parameter port_id=5;  Escaped characters
parameter cache_line_width=256;  \n: newline \t: tab
parameter bus_width=8;  %%: % \\: \
wire [bus_width-1:0] bus;  \”: “ \ooo: character number in octal
Verilog HDL 25 Verilog HDL 26

System Tasks

System Tasks: standard routine

operations provided by Verilog
Basic Concepts Displaying on screen, monitoring values,
stopping and finishing simulation, etc.
System Tasks and All start with $
Compiler Directives

Verilog HDL 28

System Tasks (cont’d) System Tasks (cont’d)

 $display: displays values of variables, strings,  $display examples:
expressions.  $display(“Hello Verilog World!”);
 Syntax: $display(p1, p2, p3, …, pn); Output: Hello Verilog World!
 p1,…, pn can be quoted string, variable, or expression
 Adds a new-line after displaying pn by default  $display($time);
 Format specifiers: Output: 230
 %d, %b, %h, %o: display variable respectively in decimal, binary,
hex, octal  reg [0:40] virtual_addr;
 %c, %s: display character, string  $display(“At time %d virtual address is %h”,
 %e, %f, %g: display real variable in scientific, decimal, or $time, virtual_addr);
whichever smaller notation Output: At time 200 virtual address is 1fe000001c
 %v: display strength
 %t: display in current time format
 %m: display hierarchical name of this module

Verilog HDL 29 Verilog HDL 30

5
 08-03-2018

System Tasks (cont’d) System Tasks (cont’d)

 reg [4:0] port_id;
 $display(“ID of the port is %b”, port_id);
Output: ID of the port is 00101
 reg [3:0] bus;
 $display(“Bus value is %b”, bus);
Output: Bus value is 10xx
 $display(“Hierarchical name of this module is
%m”);
Output: Hierarchical name of this module is top.p1
 $display(“A \n multiline string with a %% sign.”);
Output: A
multiline string with a % sign.
Verilog HDL
 $monitor: monitors a signal when its value
changes
 Syntax: $monitor(p1, p2, p3, …, pn);
p1,…, pn can be quoted string, variable, or signal names
Format specifiers just as $display
Continuously monitors the values of the specified variables
or signals, and displays the entire list whenever any of them
changes.
$monitor needs to be invoked only once (unlike
$display)
 Only one $monitor (the latest one) can be active at any time
 $monitoroff to temporarily turn off monitoring
 $monitoron to turn monitoring on again
31 Verilog HDL 32

System Tasks (cont’d) System Tasks (cont’d)

 $monitor Examples:  $stop: stops simulation
initial  Simulation enters interactive mode when reaching a $stop
begin system task
$monitor($time, “Value of signals clock=%b,  Most useful for debugging
reset=%b”, clock, reset);  $finish: terminates simulation
end  Examples:
initial
 Output: begin
0 value of signals clock=0, reset=1
clock=0;
5 value of signals clock=1, reset=1
10 value of signals clock=0, reset=0
reset=1;
#100 $stop;
#900 $finish;
end
Verilog HDL 33 Verilog HDL 34

Compiler Directives Compiler Directives (cont’d)

 General syntax:  `include: Similar to #include in C, includes
`<keyword>
entire contents of another file in your Verilog
 `define: similar to #define in C, used to source file
define macros
 `<macro_name> to use the macro defined by  Example:
`define `include header.v
 Examples: ...
`define WORD_SIZE 32 <Verilog code in file design.v>
`define S $stop ...

`define WORD_REG reg [31:0]

`WORD_REG a_32_bit_reg;
Verilog HDL 35 Verilog HDL 36

6
 08-03-2018

What we learned

 Basic concepts in Verilog

Verilog is very similar to C
 Various data types available in Verilog
Verilog uses 4-valued logic: 0, 1, x, z
 System tasks are Verilog statements used to
request something from simulator
 Compiler directives instruct the compiler to do
something for us at compile-time

Verilog HDL 37