Assignment 4

MEL G631 VLSI DESIGN

Piyush parashar
2019H1230523G

Task 1: Construct D flip-flop as shown below. Use minimum sized NMOS and PMOS for
transmission gate and symmetric gates for other components of flip-flop. Find out setup time
and hold time of flip-flop. Show waveforms used in the setup time and hold time
calculations. Generate clock complement using additional inverter.
TASK 1: The D flip flop consists of Inverter, Transmission Gates, Tristate Buffer.
The Schematic of Inverter is as shown in fig 1.1.

Fig 1.1 Inverter Schematic

Fig 1.2 Inverter Symbol

Fig 1.3 Transmission Gate Schematic

Fig 1.4 Transmission Gate Symbol

Fig 1.5 Tristate Buffer Schematic

Fig 1.6 Tristate Buffer Symbol

 Fig1.7 D Flip-Flop Schematic

Fig 1.8 D Flip-Flop symbol

 Fig 1.9 D Flip-Flop working

2) Setup0:

Fig 2.1: circuit for setup time 0

Fig 2.2 shows the various values of time for the falling edge of Input (D), the Setup time is
satisfied for some falling edges but it is violated for the some falling edges.

Fig 2.2: Parametric Analysis of Input (D) for setup time 0

Fig 2.3 violation for setup 0

Fig 2.4 Calculation of values for Tdc for setup 0 using calculator.

Fig 2.5: Calculation of values for Tdq using calculator.

 Fig 2.6 Calculation of values for Tcq using calculator.

table1
tdc tcq slope

2.41E-11 2.28E-11 0.00E+00

2.39E-11 2.28E-11 -3.33E-01
2.36E-11 2.29E-11 -5.00E-01
2.34E-11 2.30E-11 0.00E+00
2.31E-11 2.30E-11 -1.00E+00
2.29E-11 2.32E-11 0.00E+00
 Tsetup0= 2.31E-11

3) Setup1:

Figure 3.1 circuit for setup 1

Fig 3.2 shows the various values of time for the rising edge of Input (D), the Setup time is
satisfied for some rising edges but it is violated for the other some rising edges.

Fig 3.2 Parametric Analysis of Input (D) for setup time 1

 Fig 3.3 violation for setup time 1

Fig 3.4 Calculation of values for Tdc for tsetup1 using calculator.
Fig 3.5 Calculation of values for Tdq using calculator.

Fig 3.4: Calculation of values for Tcq using calculator

 Table no.2
tdc tcq slope

2.09E-11 2.63E-11 0.00E+00

2.06E-11 2.63E-11 -5.00E-01
2.04E-11 2.64E-11 3.33E-01
2.01E-11 2.63E-11 -1.00E+00
1.99E-11 2.65E-11 -3.33E-01
1.96E-11 2.66E-11 -5.00E-01

Tsetup1=2.01E-11
4) Hold0:

Fig 4.1 circuit for thold0

Fig 4.2 shows the various values of time for the rising edge of Input (D), the Hold time is
satisfied for some rising edges but it is violated for some other rising edges.

Fig 4.2 Parametric Analysis of Input (D) for hold time 0

Fig 4.3 violation for hold time 0

Fig 4.4 Calculation of values for Tdc using calculator

Fig 4.5 Calculation of values for Tdq using calculator

 Fig 4.6 Calculation of values for Tcq using calculator.

Fig 4.7 for hold0 graph

From table 1 we get the value of tcq=2.30E-11 we get -1 slope
 Table 3
Tdc_hold0 tcq

2.73E-11 2.32E-11
2.72E-11 2.31E-11
2.71E-11 2.32E-11
2.70E-11 2.30E-11
2.69E-11 2.29E-11
2.68E-11 2.28E-11
2.67E-11 2.27E-11
So hold0 value is -2.70E-11

fig 4.8 for hold0

5)Hold1

Fig 5.1: Circuit for hold1

Fig 5.2 shows the various values of time for the falling edge of Input (D), the Hold time is
satisfied for some falling edges but it is violated for some other falling edges.
Fig 5.2 Parametric Analysis of Input (D) for hold time 1

Fig 5.3 violation for hold time 1

Fig 5.4 Calculation of values for Tdc using calculator

Fig 5.5 Calculation of values for Tdq using calculator.

Fig 5.6 Calculation of values for Tcq using calculator

Fig 5.7 for thold1

From table 2 we get tcq= 2.63E-11 we get slope =-1

 Table 4
tdc tcq

2.39E-11 2.64E-11
2.38E-11 2.64E-11
2.37E-11 2.64E-11
2.36E-11 2.64E-11
2.35E-11 2.64E-11
2.34E-11 2.63E-11

So we get thold1 = -2.34E-11

Fig 5.8 for thold1

Task 2: Observations
1. Negative hold time is depends on the race condition between data and clock. If clock
manages to reach first ,hold time is said to be negative .
2. We use tristste inveter in feedback to stablish the output of transmission get when
the transmission get is switchoff’
3. The inverter is used in the input so the noise can isolated from the input of
transmission get.
4. The propagation time is different for cmos for different transmission so setup1 and
setup0 comes different