Reconfigurable Computing

CS G553

Dr. A. Amalin Prince

BITS - Pilani K K Birla Goa Campus
Department of Electrical and Electronics Engineering

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Lecture –35
Mapping Design to Reconfigurable Platform: LUT Based
Technology Mapping, Packing LUTs to CLBs

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FPGA Physical Design Flow

Design Synthesis Logic

Entry Optimization

Placement Packing LUTs Mapping

to CLBs to k-LUT

Routing Simulation Configure an

FPGA

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Packing LUTs into CLBs

 Logic block packing

groups several LUTs and
registers into one logic
block.
 This step is necessary
whenever the FPGA logic
block contains more than a
single LUT.

Highly connected LUTs

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Packing

 Logic Block packing groups several LUTs and registers into

one Configurable Logic Block (CLB), respecting limitations
such as:
o Number of LUTs a CLB may contain
o The number of distinct input signals/clocks a CLB may contain
 The optimization goals in this phase are to pack connected
LUTs together to Minimize:
o The number of signals to be routed between logic blocks
o The number of logic blocks used (by filling each logic block to its
capacity)
 This problem is a form of clustering.

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Packing

 Clustering and partitioning are essentially the same

problem:
o divide a net list into several pieces, such that certain constraints,
such as maximum partition size, are respected, and some goal,
such as minimizing the number of connections that cross partitions,
is optimized.
• When a circuit is to be divided into only a few pieces, the problem is
called partitioning.
• When a circuit is to be divided into many small pieces in one step (as
opposed to recursively partitioning into a few partitions in each step) the
problem is usually called clustering.

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Clustering

net1 cluster net1 cluster

A B A B A B

C D C D C D
net2
net2 net2
before clustering after
clustering clustering

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Circuit Partitioning

Partition 0 Partition 1
Modules
0 1 2 3 4 5
Net 3 1 0 1 1 0 0 0
Net 2
2 0 0 1 1 1 0

Nets
M1 M5 M0 M2 M4 M3 3 1 0 0 0 0 1
4 0 0 0 0 1 1
Net 1 5 1 0 1 0 0 0
Net 5
Net 4

Module
0 1 2 3 4 5
0 0 1
0 1 1 10 Objective Value = 23
(Uncut Nets)

Block
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Packing
 Shin and Kim [1] describe a greedy algorithm to transform a netlist of
circuit blocks into a netlist of clusters where:
 Each cluster contains approximately the same number of circuit blocks
 The circuit blocks in each cluster tend to be highly connected.
 The “closeness” of two clusters is a function of:
1. How many nets the two clusters share and
2. The size of the cluster that would result from merging them
 Closeness(C,D) = NumCommonNet (C,D) - ALP. ClusterSize(C,D)
min(NumPin(C), NumPin(D)) AverageClusterSize

where ALP is a weighting factor controlling how balanced cluster sizes should be.
 The two clusters with the largest closeness value are merged, and the closeness
values of all the other clusters are updated to reflect the change.
 The merging process terminates when the number of clusters in the net list falls
below some user-specified value.

[1] H. Shin and C. Kim, “A Simple Yet Effective Technique for Partitioning”, IEEE Trans on VLSI 1993 pp. 380 - 386

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Mapping & Packing: Summary

 A key factor in the development of modern complex

digital technology has been the use of automated
design tools (CAD).
 Optimization of logic circuits is becoming very
important to reduce area, power and delay.
 Mapping and packing algorithms are playing an even
more important role today in RCS especially for large
FPGAs.
 Mapping algorithms have to be modified for medium
grain FPGAs.

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The End

 Questions ?

 Thank you for your attention

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