L1: 6.

111 Course Overview

Acknowledgements: Rex Min

L1: 6.111 Spring 2004 Introductory Digital Systems Laboratory 1

 6.111 Staff Contact Information

„ In-charge
† Prof. Anantha P. Chandrakasan – anantha@mtl.mit.edu (38-107, 8-7619)
† Course Assistant: Margaret Flaherty – meg@mtl.mit.edu (38-107, 3-0016)
„ Lecturers
† Prof. Anantha P. Chandrakasan – anantha@mtl.mit.edu (38-107, 8-7619)
† Prof. Donald E. Troxel – troxel@mit.edu (36-287, 3-2570)

„ Teaching Assistants (TAs)

† Cemal Akcaba– akcabac@mit.edu (38-600, 3-7350)
† Jia Fu Cen– jiafu@mit.edu (38-600, 3-7350)
† David Milliner– dlm@mit.edu (38-600, 3-7350)
„ Lab Aides (LAs)
† TBD
„ Technician
† Marty O. Hughes – marty@mit.edu (38-500, 3-4628)
„ Technical Instructor
† Alexandra Andersson - alexxx@mit.edu (38-583)
„ Sixth Floor Stock Clerk
† Arlin Mason - arlin@mit.edu (38-600, 3-4674)

L1: 6.111 Spring 2004 Introductory Digital Systems Laboratory 2

 Recommended Books

„ Logic Design:
† Randy H. Katz, Contemporary Logic Design, Addison Wesley, MA,
1993 .

„ Verilog: there are plenty of good Verilog books. We

strongly recommend that you get a Verilog book. A couple
of suggestions are given below:

† Samir Palnitkar, Verilog HDL, Pearson Education (2nd edition).

† Donald Thomas, Philip Moorby, The Verilog Hardware Description

Language, Fifth Edition, Kluwer Academic Publishers.

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 6.111 Goals and Prerequisite
„ Design and Implement Complex Digital Systems
† Fundamentals of logic design : combinational and sequential blocks
† System integration with multiple components (memories, discrete
components, FPGAs, etc.)
† Use a Hardware Design Language (Verilog) for digital design
† Understand different design methodologies and mapping strategies (FPGAs
vs. custom integrated circuits)
† Interfacing issues with analog components (ADC, DAC, sensors, etc.)
† Understand different design metrics: component/gate count and
implementation area, switching speed, energy dissipation and power
† Design for test
† Demonstrate a large scale digital or mixed-signal signal system

„ Prerequisite
† Prior digital design experience is NOT Required
† 6.004 is not a prerequisite!
 Take 6.004 before 6.111 or
 Take 6.004 after 6.111 or
 Take both in the same term
† Must have basic background in circuit theory
† Some basic material might be a review for those who have taken 6.004

L1: 6.111 Spring 2004 Introductory Digital Systems Laboratory 4

 Objectives

„ On completion of 6.111 students will have confidence to

conceive and carry out a complex digital systems design
project
„ More broadly, they will be ready to handle substantial,
challenging design problems. In particular, students will
be able to:
1. Explain the elements of digital system abstractions such as digital
logic, Boolean algebra, flip-flops, and finite-state machines (FSMs).
2. Design simple digital systems based on these digital abstractions,
and the “digital paradigm” including discrete, sampled information.
3. Use basic digital tools and devices such as logic analyzers, digital
oscilloscopes, PALs, PROMs, FPGAs, and Verilog.
4. Work in a design team that can propose, design, successfully
implement, and report on a digital systems design project.
5. Communicate the purpose and results of a design project in written
and oral presentations.

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 Overview of Labs

„ Lab 1
† Learn about the lab kit and wire something
† Learn about lab equipment in the Digital Lab (38-600): oscilloscopes
and logic analyzers
† Program and test a PAL (Programmable Array Logic Device)
† Introduction to Verilog

„ Lab 2
† Design and implement a Finite State Machine (FSM)
† Use Verilog to program an FPGA
† Learn how to use an SRAM
† Report and its revision will be evaluated for CI-M

„ Lab 3
† Design a complicated system with multiple FSMs (Major/Minor FSM)
† Implement RAMs and ROMs in an FPGA
† Interfacing to analog components (ADC and DAC)

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 Final Project

„ Done in groups of two or three

„ Open ended
„ You and the staff negotiate a project proposal
† Must emphasize digital concepts, but inclusion of analog interfaces (e.g.,
data converters, sensors or motors) common and often desirable
† Proposal Conference
† Design Review(s)
z Early
z Detailed

„ Design presentation in class (% of the final grade for the in-class

presentation)
„ Top projects will be considered for design awards
„ Staff will provide help with project definition and scope, design,
debugging, and testing
„ It is extremely difficult for a student to receive an A without completing
the final project.

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 Grading and Collaboration
„ Grading Policy
† We start with a number. Then discuss everyone, especially performance in
labs and project. Approximate breakdown:
z Quiz 10%
z Writing (Lab 2 revision- part of CIM requirement) 10%
z 3 Problem Sets (emphasis on lab concepts) 5%
z Participation (lecture, recitation, labs) 5%
z 3 Lab Exercises
 Lab 1 10%
 Lab 2 10%
 Lab 3 15%
z Final Project 35%
„ We impose late penalties
† No late problem sets will be accepted and solutions handed out at the end of
class
† Labs are penalized 20% per day
† Final Project MUST be done on time

„ Cooperation
† Please be courteous with shared resources as lab computers and equipment
„ Collaboration
† Discuss problem sets and labs with anyone, staff, former students, other
students, etc.
Then do them individually
z
Do not copy anything, including computer files, from anyone else
z
† Collaboration on the project is desirable (especially with your partners)
z Project reports should be joint with individual authors specified for each section
z Copy anything you want (with attribution) for your project report

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 Early Digital Systems

Arithmometer Comptometer Difference Engine

(Thomas de Colmar, (Dorr Eugene Felt, (Charles Babbage,
1820) 1887) 1832)

„ The first digital systems were mechanical and used base-10

representation.
„ Most popular applications: arithmetic and scientific computation
„ Prone to failure, difficult to fix, often slower than skilled humans

L1: 6.111 Spring 2004 Introductory Digital Systems Laboratory 9

 Meanwhile, in the World of Theory…

AND OR Inversion

0 0
0 0
0 0

0 0
0 1 0 1
1 1

1 1
0 1 1 0
0 0

1 1
1 1
1 1

„ 1854: George Boole shows that logic is math, not just

philosophy!
„ Boolean algebra: the mathematics of binary values

L1: 6.111 Spring 2004 Introductory Digital Systems Laboratory 10

 The Key Link Between Logic and Circuits
(The Vacuum Tube)

0
0
1
1
1
+
0

Lee de Forest, 1906

Digital
Electronics

„ Despite existence of relays and introduction of vacuum tube in 1906,

digital electronics did not emerge for thirty years!
„ Claude Shannon notices similarities between Boolean algebra
and electronic telephone switches
„ Shannon’s 1937 MIT Master’s Thesis introduces the world to
binary digital electronics
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 65 Years of Digital Electronics

Vacuum Tubes Transistors VLSI Circuits

UNIVAC, 1951 IBM System/360, 1964 Intel Itanium, 2003

1900 adds/sec 500,000 adds/sec 2,000,000,000

adds/sec

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 Building Digital Systems

„ Goal of 6.111: Building binary digital solutions to

computational problems

„ Problem sets
Problem Statement „ Labs & Design project
„ Product specs
algorithm selection,
flowcharts, etc.
„ Algorithms, RTL, etc.
Behavioral Description „ Flowcharts
„ State transition diagrams
conversion to binary,
Booelan algebra
„ Logic equations
Boolean Logic and State „ Circuit schematics
device selection
and wiring
„ TTL Gates (AND,OR,XOR…)
Hardware Implementation „ Modules (counter, shifter,…)
„ Programmable Logic

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 Building Digital Systems with HDLs

„ Logic synthesis using a Hardware Description Language (HDL)

automates the most tedious and error-prone aspects of design

„ Problem sets
Problem Statement „ Labs & Design project
„ Product specs
algorithm selection,
flowcharts, etc.
„ Algorithms, RTL, etc.
Behavioral Description „ Flowcharts
„ State transition diagrams
software-like
programming
„ Verilog code
HDL Description „ VHDL code

automated synthesis

„ Programmable Logic
Hardware Implementation „ Custom ASICs

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 Verilog and VHDL

VHDL
„ Commissioned in 1981 by
Department of Defense;
now an IEEE standard
„ Initially created for ASIC
synthesis
„ Strongly typed; potential
for verbose code
Verilog
„ Created by Gateway Design
Automation in 1985;
now an IEEE standard
„ Initially an interpreted
language for gate-level
simulation
„ Less explicit typing (e.g.,
compiler will pad arguments
of different widths)

„ Strong support for package „ No special extensions for

management and large large designs
designs

Hardware structures can be modeled effectively in either

VHDL and Verilog. Verilog is similar to c and a bit easier to learn.

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 Levels of Modeling in Verilog

„ Behavioral or Algorithmic Level

† Highest level in the Verilog HDL
† Design specified in terms of algorithm (functionality) without hardware
details. Similar to “c” type specification
† Most common level of description

„ Dataflow Level
† The flow of data through components is specified based on the idea of how
data is processed
„ Gate Level
† Specified as wiring between logic gates
† Not practical for large examples

„ Switch Level
† Description in terms of switching (modeling a transistor)
† No useful in general logic design – we won’t use it

A design mix and match all levels in one design is possible.

In general Register Transfer Level (RTL) is used for a
combination of Behavioral and Dataflow descriptions

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 Embedded Digital System

Analog Inputs Analog

(sensors, audio, A/D Memory Outputs
video, tablet)
D/A (actuators, motors,
multimedia)
digitize
Control
synchronize
Digital Inputs Digital
Data
(peripherals, Sync. Outputs
Processing (peripherals,
buses, switches)
buses, lights)

„ Digital processing systems consist of a datapath, memory, and control.

Early machines for arithmetic had insufficient memory, and often
depended on users for control
„ Today’s digital systems are increasingly embedded into everyday places
and things
„ Richer interaction with the user and environment

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 Intersil 54 Mbps 802.11a System

5 GHz Baseband Digital Processing

Analog Analog and Control

L1: 6.111 Spring 2004 Introductory Digital Systems Laboratory 18

 TI Digital Camera Controller

Motors and Mechanical Sensors

Peripheral
Interfaces
Audio/Video In
Memory Subsystem

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 A Wireless Microsensor System
(MIT MEng Thesis)
Implemented
on an FPGA
Mic. Threshold Antenna
Static RAM Flash ROM Control
Detector
Amp
Low-Pass Clock Radio
ADC Processor FIFO Recovery
Filter IC
Power
Battery DC/DC Converter FIFO Shifter Amp.

Sensor Processor Radio

4-channel acoustic 206MHz StrongARM 2.4GHz ISM band

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 Real-World Performance Metrics

Cost Speed Energy

commodity products scientific computing,

portable applications
simulation

„ Commercial digital designs seek the most appropriate

trade-offs for the target application…
„ …keeping time-to-market in mind

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 Implementation Strategies

„ Start with gates: AND, OR, NAND, NOR, NOT, etc.

† These blocks are implemented with SSI (requires the most wiring)
„ Progress to building blocks: Registers, Counters, Shift
Registers, Multiplexors, Selectors, etc.
† These blocks are implemented with MSI (requires less wiring)
„ Progress to PALs, FPGAs, ASICs, Custom VLSI chips
† These blocks require the least wiring
† We will not use ASICs or Custom VLSI chips

„ FPGA chips are very complicated

† Designing them with gates is not very productive and error prone
† We need a higher level language such as Verilog (or VHDL) to
specify the programming of FPGAs
† We will use Verilog this term

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 HDL Misconceptions

„ The coding style or clarity does not matter as long as it

works
„ Two different Verilog encodings that simulate the same
way will synthesize to the same set of gates
„ Synthesis just can’t be as good as a design done by
humans
† Shades of assembly language versus a higher level language
„ Synthesis tool can’t be wrong, there is no need for
extensive simulation

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 What Can be Synthesized?

„ What can be Synthesized

† Combinational Functions
z Multiplexors, Encoders, Decoders, Comparators, Parity Generators,
Adders, Subtractors, ALUs, Multipliers
z Random logic

† Control Logic
z FSMs

„ What can’t be Synthesized

† Precisetiming blocks (e.g., delay a signal by 2ns)
† Large memory blocks (can be done, but very inefficient)

Understand what constructs are used in

simulation vs. hardware mapping

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 Verification and Testing

„ Design can be fun. Verification/testing is hard work.

„ Untested designs are rarely good designs.
„ Verification by simulation (and formally through
testbenches) is a critical part of the design process.
„ The physical hardware must be tested to debug the
mapping process and manufacturing defects.
„ Physical realizations often do not allow access to internal
signals. We will introduce formal methods to observe and
control internal state.

Verification and Design for Test (DFT) are important

components of digital design

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 Lab Hours - Equipment

„ The normal lab hours are:

z Monday through Thursday – 9:00 AM to 10:45 PM
z Friday – 9:00 AM to 5:15 PM
z Saturday – 12:00 noon to 5:45 PM
z Sunday – 12:00 noon to 10:45 PM
z Hours for Holidays, Spring Break, etc. is posted on the course website

„ Please be out by the indicated time

„ Please report any equipment malfunctions (Logic

Analyzers, Computers, etc.) by tagging such equipment
with your name. Also send email to 6.111staff@mit.edu
„ Send email to 6.111staff@mit.edu if you have questions,
etc. All of us read that list and you will get an earlier
response than by sending to an individual member of the
teaching staff

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 6.111 Software
„ Use ‘setup 6.111’
† ‘setup 6.111’ sources /mit/6.111/.attachrc which attaches 6.111-nfs
and sources /mit/6.111-nfs/.attachrc which sets up your path and
environment variables, etc.
„ We will use the following tools installed on the new PCs
(courtesy of Intel):
† Warp (to program PALs)
† PAL programming software on two dedicated windows ’98 PCs in
the lab
† ModelSim (powerful front-end simulator for Verilog)
† MAX+PlusII (simulator and programming software for Altera FPGAs)
† Office (Microsoft word, power point, etc.)

„ In addition, some of the tools are supported on Athena Sun

platforms (Solaris and Linux). Please check the course web
site for instructions on using them.
„ You can use WinSCP to transfer files between the lab PCs
and athena

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 Turn in Your Schedule Sheet

„ Fill in the information and permission form on the last page

of the handout (you can change your election at any time
during the semester). We need this information to create
computer accounts. Please turn it in at the end of lecture.
„ Recitation assignments will be posted by Friday on the
bulletin board in the Digital Lab and on the 6.111 web page
„ Extra handouts are stored in the filing cabinet in the back
left corner of the digital lab. Lecture notes will be available
on the web site
„ web.mit.edu/6.111/www/s2004
† Also available from the EECS department web page
† Shorthand which works (from MIT) is ‘web/6.111’

„ Pick up lab kits starting Thursday at 1 pm

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