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Intel” may make changes to specications and product descriptions at any time, without notice Designers must not ely onthe absence or characteristics ofa listens rare reserved" or undefined” mel resrves tnse Yor future deation snd shal have no fasponsiaity weatsanver fr covets ot Incompataie sng Fem future changes to them The information Mere Is sublecto change wnout novice, bo et fnalee = design wrth ti Information iat Soc nriber ae nora measure of pearance SoC numbers deena eres wun exh SOc fly, ot arose iret Se fale See Mpvlerintel oreforoductaleat-nurbar for deta ‘The products desefbedn ths document may conta desi defects or errorsknown as erata which may cause the product to devate rom published specheatone: Current chartered rat ae svete enrequest. ‘The code names presented inthis document are ony for use by intl” toldentty products, tchnologes or services development that have not been made ‘array sable Toth pubic ey announced aunchador sipped. they sent core hares or produto erte ana are not inendad to Contact your loc ntl sales ofce or your stibutor to obtain the ates pecfiations and belore placing your product oxde. Coples of documents which have an order number and ae referencedin ths dacumer,or ater intl" IRerature may be cbtaned by calling 1-800-548-4725 SPby ashing inlet ss) cara in erst Tac) a twp-uie communications bus/protool developed by Phils. SMSus iy a subset of the|2Cbus/protoce and was dewaloped by Intl. mplementatins ithe Zeb ahprotocol nay ere canes hom aos enon inavang aps acwontes and Nor Amenean Supe Comparten. ures a sytem wth ite” Turbo Soost Technology. Intel” Turbo Boos Technology and intel” Turbo Boost Technology 2.0 are only avalable on select intl” Sede Canalyour Ac manutorturer. Bertonmance eres depending on hardare sevwree, and sytem coniguravon, far moreinformation sist Intel” Skylake-D isa trademark of intel” Corporation orn the US and other countries Copyright © 2016, tel” Corporation. All rights reserved * Other brands and names may be clamed asthe property of others.Revision History i) Comments Date Initial Release May 2016 Various dimensional updates August 2016Contents * Thermal Model Archive Contents + References * Definition of Terms + Model DetailsThermal Model Archive Contents The Skylake-D SoC package thermal model is created for system level thermal solution development using thermal analysis tools. The package thermal model is called “model” throughout this document. Only the Skylake-D SoC TTV package named “Goat Rock” is represented in the model, and is intended for import into a system level thermal model. The dimensions and thermal properties used in the models are based on the current best estimates, and are subject to change. The model archive include the following items: 1. 2. 3. 4. User’s Guide GoatRock_rev1 Thermal Model in | k* GoatRock_rev1 Thermal Model in F! ~ —‘m* , GoatRock_rev1 Thermal Model in 6SigmaET*References Document Reference Notes ‘Skylake-D Thermal Mechanical Specification and Design Guide | 568201 1 ‘Skylake-D SoC Product Family Electrical Design Specification | 568202 1 (€08) NOTES: 11. Contact your Intel field sales representative forthe latest revision and order number of these documents, Definition of Terms Teen noe HS: Integrated Heat Spreader SoC. System On a Chip. r The case temperature of the processor measured at specific locations on the topside of the IHS, this is typically ase above the geometric center ofa particular die (but may not coincide with the geometric center ofthe IHS) Tenucenie The CPU junction temperature is measured atthe geometric center of the CPU, Tova canien “The PCH junction temperature ls measured atthe geometric center of the PCH. TOP ‘Thermal Design Power thermal solution should be designed to dissipate this target SOC power level TDP Is not the maximum power that the SoC can dissipateModel Format The model was created inl , .k* 15.0 and is provided in TZR format, in Fi_..._-.“4* 10.1 and provided in PDML format and in 6SigmaET* in EQUIPMENT format. It is not a stand alone model and should be merged into asystem model assembly. The following model filenames are used: + GoatRock_rev1.tzr * GoatRock_rev1.pdml * GoatRock_rev1.equipmentModel Components The model is comprised of cuboids that represent the package stackup, along with a source to simulate package heating. The following components are modeled: 1. chip accion, where = ieatioen 2. correct for sch uniform heating of the actual silicon. Ref" *2 *he Skulake-1 Sac Thermal and Machnnical Snaritirntinne and Design Guide > -rraction factors. 3. Burrs an orthotranic cubaid tn model the conduction thzsugh £4 hnmns that provide the interface hetween die and ciihetrate, 4, Sustaic ~an ortho uboid representing the substrate, 5. Note: Figure does not show IHS and is not to scale motherboard. and is for reference only.Model Components PEE TIE Sera = 6 Wik Esubsiate fa vhy=0.7,Ka=9. Wimk (Eo <== 2: 2.9mm wimk KD ame oo W/mK w/mk oo oe Kz=C. W/mK TOP = sku specific k= w/mk z Kz=0. W/mK Wink sku specific = wimk w/mkModel Inputs and Boundary Conditions The model is provided as a conduction only model, and no boundary conditions are defined. Users are expected to set the appropriate boundary conditions in the system level thermal model. The user needs to set the source power to latest SoC TDP for the SKU of interest found in the Skylake-D SoC Thermal and Mechanical Specifications and Design. Example: For a SoC TDP of 35 W 2.0W (CPU) + 1W (PCH) = 35 W The model X and Z coordinate axes define the package in-plane direction, and the Y axis defines the package normal direction. Material thermal conductivities are assigned based on these directions. The user should check whether orthotropic conductivity remains unchanged after importing the model into a system model.Model Mesh The meshing constraints provided in the model are intended as a starting point and users should modify the model according to the accuracy requirements of their system level model. Note: The T ase value may be affected by a coarse mesh around the die area. If you are using a coarse mesh, please compare the monitor point temp. Monitor Points A monitor point for case temperature (Tease) is included in the model defined in the Thermal Mechanical Design guide. A Tcase-cpy Monitor point is included to monitor the CPU case temperature, which requires correction for non-uniform heating. A Tease-ocy monitor point is also included to monitor the case temperature of the PCH, which requires correction for non-uniform heating. Non-uniform Heating Correction Factors The thermal model requires correction from uniform heating to non-uniform heating of the actual silicon. The model is intended to simulate case temperatures for a given sku when using their respective correction factors. It is not intended to predict package thermal resistances or junction temperatures. Refer to the Skylake-D SoC Thermal and Mechanical Specifications and Design Guide for correction factors.Temperature Monitor Point Measurement Locations Note: Figure is not to scale and is for reference only.Technical Support I-- . k* modeling questions should be directed to.” ~“S* product support. Fi _ M* modeling questions should be directed to **_..t2r Graphics* product support. 6SigmaET* modeling questions should be director to Future Facilities* product support. For questions on the construction of the package model, please contact your Intel field sales representative.