module FABCD4BITSLCD

(/*input[3:0]s, C2,*/ output [6:0]ssd_u,ssd_d);

display7seg ssd0 (u,ssd_u);

display7seg ssd1 (d,ssd_d);

endmodule

module display7seg(s, output reg [6:0]L);

always @(s) begin
case (s)

4'd0:L=~7'h7e;
4'd1:L=~7'h30;
4'd2:L=~7'h6d;
4'd3:L=~7'h79;
4'd4:L=~7'h33;
4'd5:L=~7'h5b;
4'd6:L=~7'h5f;
4'd7:L=~7'h70;
4'd8:L=~7'h7f;
4'd9:L=~7'h7b;

default:L=~7'h00;
endcase
end
endmodule

/////////******************************** FA BCD 4 BITS*********************

module FABCD
(
input Ci,
input [3:0]a, b,
output Co,
output [3:0]s
);
wire [3:0]z;
wire d;
wire C1,C2;

SUMADORCOMPLETO4BITS FA0(Ci, a, b , C1, z);

assign d=((z[1] | z[2]) & z[3])| C1;

SUMADORCOMPLETO4BITS FA1(1'b0, z,{1'b0,d,d,1'b0},C2,s );

assign Co= d;
endmodule

module SUMADORCOMPLETO4BITS
(
input Ci,
input [3:0]a, b,
output Co,
output [3:0]s
 );
wire X1,X2,X3;
sumadorcompleto FA0(a[0], b[0], Ci, X1, s[0]);
sumadorcompleto FA1(.a(a[1]), .b(b[1]), .Ci(X1), .Co(X2), .s(s[1]));
sumadorcompleto FA2(.a(a[2]), .b(b[2]), .Ci(X2), .Co(X3), .s(s[2]));
sumadorcompleto FA3(.a(a[3]), .b(b[3]), .Ci(X3), .Co(Co), .s(s[3]));

endmodule
////////////////////////////////
module sumadorcompleto (input a,b,Ci, output Co,s);

wire X0,X1,X2;

ha HA0 (a,b, X0,X1);

//instanciar por posicion

//ha HA1 (X1,Ci, X2,s);

//instanciar por nombre

ha HA1 (.a(X1),.b(Ci), .Co(X2), .s(s));

assign Co =X2|X0;

endmodule

module ha
(input a,b, output Co,s);
and (Co,a,b);
assign s=a^b;
endmodule
///////////////////////