De La Salle University

Electronics and Communications Engineering Society

An Affiliate of IEEE

ADVELIN Reviewer rev 0

Quiz I

I. Identify what is being described on each of the given statements.

1. The earliest form of integrated circuit that utilizes logic gating by placing transistors in series
or in parallel.
2. The fastest non-saturating digital logic family.
3. CMOS stands for ______.
4. Refers to the number of parallel compatible logic outputs that can be used to drive another IC.
5. The measure of the ability of a device to attenuate all signals that are similar to both inputs.
6. A circuit devised so that the output current remains essentially constant despite variations in
load resistance.
7. To form an ideal differential amplifier, the two transistors used must be ___.
8. The measure of the reduction of the open loop gain.
9. The name “operational” was coined to op-amps since it is capable of performing a large
number of ______.
10. The time rate of change of the output voltage of an op-amp having a closed loop gain of one.
11. The equivalent dc voltage that must be applied to one of the input terminals of an op-amp in
order to produce a zero output with the other input terminal grounded.
12. Metal heat radiators designed to remove heat from components by thermal conduction,
convection or radiation.
13. A part in the IC package that denotes pin number 1.
14. Constructed from a single crystal or other single piece of material.
15. A miniaturized version of an electronic circuit formed by using layers of P-type and N-type
materials.
16. IC’s that respond to two voltage (or current) levels only.
17. Counters, multiplexers and adder digital circuits are classified under what scale of
integration.
18. The magnitude at which the noise voltage must exceed before it could cause an adverse effect
on the performance of the digital logic circuit.
19. LCCC stands for _______.
20. QFP stands for _________.
21. The fastest saturating bipolar logic family.
22. These circuits help to reduce noise and interference normally used for long distance
transmission lines.
23. A circuit that produces an output voltage which is proportional to the area (amplitude
multiplied by time) contained under the input waveform.
24. A circuit that accepts millivolt units of input voltages derived from transducers and produces
a linearly scaled amplified version of these inputs.
25-30. What are the differences between a differential amplifier, difference amplifier and a
differentiator.

Electronics and Communications Engineering Society Page 1 of 10

ADVELIN Reviewer
II. Determine the output voltage expression for the given circuit.

R
V1 R

+V
7R
R R
R Vo

+V
R 4R
2R
V2 R
+V

R
R

Figure 1

III. Design an op-amp circuit that will satisfy the given output voltage expressions. Draw the circuit.

Assume Rmin = 10 kΩ for both conditions.

a) Vo = 2A + 4B – 8C + 6D – 6E
b) Vo = 3w – 2x + 4y – 4z
Where: A,B,C,D,E,w,x,y,z = input voltages

IV. The output voltage of a unity gain op-amp circuit rises from 15V in 20 µs. Find the slew rate.

V. Determine the required value of R to translate 0-5V to 0-2 mA

Vi R R
+V

(0-2mV) + Vo
+V

RL R

Figure 2

VI. Calculate the input impedance, output

impedance and the closed loop gain for
the given circuit.

Vi
+ Vo
+V

Zi (intrinsic) = 100 kΩ
+V

Zo (intrinsic) = 0.3 Ω
9K AOL = 100,000
1K

Figure 3

Electronics and Communications Engineering Society Page 2 of 10

ADVELIN Reviewer
VII. Show how we can implement the given Boolean functions using RTL family.

a) F = A’+B’+C’
b) F = WXYZ

VIII. R2 in the figure is an LDR (Light Dependent Resistor) whose resistance varies from 20 kΩ to
20.5 kΩ. Determine Rx if it is desired to translate this change in resistance form 0 to 10V.
R = 300 kΩ
R1 = R3 = R4 = 20 kΩ

R2
+
R1 R4 R
+ R3
15V R
R
Vo

+V
Rx
R R
R

Figure 4

Quiz II

I. Identify what is being described on each of the given statements.

1. A delay equalizer network that introduces a constant phase shift as a function of the input frequency.
2. The slope in a filter response as the input frequency is increased or decreased beyond the cut-off
frequency.
3. A circuit that detects whether or not an input voltage is within two specified voltage limits.
4. A comparator having an grounded reference voltage.
5. Unwanted transitions in a comparator circuit due to rapid changes of input voltage due to noise.
6. The phase difference between two similar frequencies may be determined by _____ the two inputs.
7. The difference between the upper and lower threshold voltages in a Schmitt circuit is called ____.
8. The ratio of tOFF to the period is known as ______.
9. A waveform having equal rise (+slope) and fall (-slope) time.
10. A filter formed by placing a low pass having a cut-off frequency of fHC in series with a high pass filter
whose cut-off frequency equals fLC.
11. A term that implies phase inversion of 90 degrees.
12. A circuit that produces an output dc voltage proportional to the phase difference of the two similar
input frequencies.
13. An active filter that provides equal ripple response on the pass band.
14. A level detector circuit that provides +Vsat if the reference voltage falls below a fixed reference
voltage.
15. This determines the steepness of the roll-off rate.

Electronics and Communications Engineering Society Page 3 of 10

ADVELIN Reviewer
16. Filters that employs passive devices with active devices such as transistors and op-amps and provides
amplification.
17. The –3dB point is also known as ______.
18. At the –3dB point, the input frequency equals _______.
19. A circuit that may be employed to eliminate the effects of false comparator chattering.
20. A multivibrator circuit that has a single stable state, which is also referred to as a one shot
multivibrator.
21. In a single supply ac amplifier, the reference of the ac signal is set to ______ of the supply voltage.
22. A filter that rolls off at the rate of 120 dB per decade.
23. A figure of merit for amplifiers used to determine the available open loop gain in reference with the
operating frequency.
24. Pin no 7 of the 555 IC timer refers to the ______ pin.
25. The maximum possible output voltage of an op amp is the ______.
26. Filters that attenuates all frequencies above the higher cut-off frequency and frequencies below the
lower cut-off frequency.
27. The attenuation introduced by an oscillating circuit that causes a damped signal.
28. A filter that has essentially flat amplitude response on the pass band.
29. The number of poles in a filter also denotes the ______.
30. A comparator circuit whose output voltage equals –Vsat when the input voltage is above the reference
voltage.

II. 1. Solve for the Ra and C so that the cut-off frequency equals 20 kHz with:
a) Bessel response
b) Butterworth response

C
+
Vi 50K 50K + Vo
+V

+V
+

C
10K
Ra

RESPONSE Rf / Ra Low pass High pass

Bessel 0.268 1.274 fc 0.785 fc
Butterworth 0.586 1.000 fc 1.000 fc
1 dB Chebyshev 0.955 0.863 fc 1.159 fc
2 dB Chebyshev 1.105 0.852 fc 1.174 fc
3 dB Chebyshev 1.233 0.841 fc 1.189 fc

Electronics and Communications Engineering Society Page 4 of 8

ADVELIN Reviewer
2. Determine:
a) The output frequency and the minimum value of Rf in order to sustain oscillation.
b) The maximum output frequency fmax for the given circuit if the GBP of the op-amp is
10 MHz.

4.7uF
20K +

+ Vo

+V
4.7uF 20K
Rf
10K

3. Determine the ACL, fmin, fmax and the input impedance if the GBP = 2 MHz

15V
+V
Vi 0.47uF
+ 80uF Vo
+V

+V
200K
20K 2K
15V 20K
+V

20K 10uF
2K

1uF

4. Determine the output frequency of the given oscillator circuit.

60K 60K 60K

Vo
+V

10K
0.47uF
5K

Electronics and Communications Engineering Society Page 5 of 8

ADVELIN Reviewer
5. Design an astable multivibrator circuit whose OFF duty cycle is 40% at 50 Hz. Assume C = 4.7 µF
6. Determine Vo (dc) if Vi = 30 sin (12566.37t)

5K

5K
Vo
multiplier

+V
20K
47uF
Vi
+V

7. Determine the states of D1, D2, LED1, LED2 and LED3 if:
a) 0 < Vi < Vref2
b) Vref2 < Vi < Vref1
c) Vref1 < Vi < 9V
Compute also for Vref1 and Vref2

9V
+V

15K
+ D1
Vref1
10K 9V LED1
20K
Vi +V
D2
+V

+ LED3
Vref2 2K
LED2
+V 20K
5K
-9V

8. Design a non-inverting Schmitt trigger with zero reference using + Vsat = + 13V with Ra = 10 kΩ
whose upper and lower thresholds equals +2V and –2V, respectively. Plot the transfer characteristic
and label them properly.

Electronics and Communications Engineering Society Page 6 of 8

ADVELIN Reviewer
 Quiz III

I. Identify / Enumerate / Discuss

1. Measure of consistency and repeatability of measurements.

2. Device that converts one form of energy to another form.
3. Degree of exactness of the measured value in reference with the most probable value.
4. Types of errors due to harsh conditions such as high temperature, pressure or humidity.
5. Errors due to friction in the bearings, incorrect spring tension or improper calibration.
6. An observational error due to the apparent displacement of the position of an object caused by a shift
in the point of observation.
7. A device or mechanism used to determine the present value of the quantity under observation.
8. These circuits are required to process the incoming electrical signal to make it suitable for the
application of the indicating device.
9. What is PMMC?
10. The process of comparing an unknown quantity with an accepted standard quantity.
11. The minimum error introduced when measuring the quantity equivalent to the instrument’s full-scale
deflection.
12. Another name for Ayrton shunt.
13. The most widely used ADCs as they go through a series of approximations to obtain the digital
representation of the analog input voltage.
14. The type of inaccuracy introduced in an ADC that occurs when the input changes before the
conversion process is completed.
15-16. Disadvantages of binary weighted DAC
17-20. Measurement error standards.
21-30. Draw the sample and hold circuit and discuss its operation as to why they are significant in the
operation of an ADC.

II.
1. Design a 5-bit binary weighted digital-to-analog converter whose resolution equals 0.1V. Use Vr =
5V and Rf = 5 kΩ.

2. Draw the circuit for a 4-bit R-2R resistor ladder digital-to-analog converter and solve for the
appropriate value of Rf so that the resolution equals 0.2V with Vr = 2V and Ra = 10kΩ

3. Design a 2 bit Flash ADC whose resolution equals 0.5V. plot the truth table with respect to the analog
inputs.

4. An inductance and capacitance meter are to be used to measure the resonant frequency in an LC
circuit. The inductance meter and capacitance meter are guaranteed to be accurate within + 3% and
+5%, respectively, at maximum reading. If the inductance meter reads 40 mH on its 100-mH range
and the capacitance meter reads 45 µF on its 100 µF range, determine the approximate percentage
limiting error on resonant frequency calculation.

5. Using a meter movement whose IFSD = 100 µA with an internal resistance of 2 kΩ, design a multi-
range Ayrton shunt circuit with given desired ranges:
0-50 mA, 0-100 mA, 0-500 mA and 0-1A,

Electronics and Communications Engineering Society Page 7 of 8

ADVELIN Reviewer
6. Determine the %E when a 5-ohm ammeter is used to measure the current along points X and Y

Electronics and Communications Engineering Society Page 8 of 8

ADVELIN Reviewer