Introduction

This is a training program for all the newly hired FPGA designers. The aim here is to give you
some hands-on training of the RTL coding in VHDL language and to make you understand the
basic coding strategies to be followed. May be you are already aware of these things, still, we are
sure it will be fruitful for you to go through this training program. It will definitely boost your
confidence. The time duration of this training program will be roughly 1 month.

Why to do Training Program

Motivation behind this training program:-

 Understanding all software tools utilized by FPGA team for FPGA development.
 Develop solid understanding of the RTL design.
 Understanding complete FPGA design cycle from design to on-board testing.
 Newly joined engineers will get some time to understand organization’s work culture
and to gel with the team members.

Directory Structure of Training Program

 There are eight projects to be done as a part of training program. “Project Block
Diagram” directory contains Data Flow block diagrams for each of the project.

 “Projects” directory contains eight sub-directories by the name project_x, one sub-
directory for each project.

 “Reference Tutorial” directory contains all the tutorials required for this training
program.

 DiagramDesignerSetup1.27.3.msi is the installer for Diagram Designer tool. We have

used this tool to create Data Flow block diagrams. Even though this tool is freely
available on internet, we are providing the installer because all these block diagrams are
created in this particular version of the tool. May be these block diagram files are not
compatible with the latest version of the tool.
  FPGA Training Program Guide document is the one you are currently reading.

 FPGA training Program Milestones.xlsx is the excel sheet in which all milestone details
are provided.

A mentor will be assigned to you who will help you in achieving all your training program
milestones. It is our understanding that if all the above milestones are properly achieved, you
will get thorough understanding of the RTL coding and FPGA design cycle and you will be ready
for executing tasks in live projects.

Milestone Execution Details

We have created one excel sheet which lists down all the milestones to be achieved during
training period. The mentor assigned to you will be the assignee of these milestones and you
will be the owner of these milestones. Whenever any milestone is completed, you have to
discuss the completed milestone with your mentor. Once, your mentor is satisfied with the
completion status of that milestone, he will update the milestone excel sheet. Once, all the
milestones get over, your training program will get over. We will give you a rough idea about
how much time it should take to complete each task in the training program but little variation
in this schedule is acceptable. The aim here is to get maximum learning out of training program.

Software Tools Required

The following software tools will be required to complete the training program:-

 Diagram Designer
 Modelsim 10.1c
 Xilinx ISE 14.7

If other tools are required, mentor will provide.

Training Program Feedback

At the end of this program, your mentor will be asked to give your feedback regarding your
performance during the training program. Mentor’s feedback really matters to the organization.
Your performance will depend upon the following factors:-

 How much effort you have put in to complete your milestones.

 What type of attitude you have shown towards your mentor.
 How much mentor’s time you have taken to achieve your milestones.
 How much time you have taken to complete your training program.
 How much energy you have shown during the training program.
 What type of approach you have followed during on-board debugging.