Data Flow Modeling

Prof. A. K. Swain
Asst. Prof., ECE Dept., NIT Rourkela

EC6203: Reconfigurable System Design

 Data Flow Modeling
Learning Objectives:
o Describing the continuous assignment (assign) and multiple assignment
statement.
o Explaining net declaration assignment
o Explaining the delays: inertial, transport and net delays.
o Using data flow constructs to model digital circuits.

Data Flow Modeling EC6203 Reconfigurable System Design

 Continuous Assignment
A continuous assignment assigns a value to a net (it cannot be used to
assign a value to a register).
Syntax:
assign [delay] LHS _ target = RHS_expression ;
Example:
wire [3 :0 ] Y, B, C ; // Net declaration
assign Y = B & C ; // Continuous assignment

When does a continuous assignment execute?

• Whenever an event (an event is a change of value) occurs on an operand
used in the right-hand side expression,
• The expression is evaluated and if the result value is different,
• It is then assigned to the left-hand side target.

Data Flow Modeling EC6203 Reconfigurable System Design

 Multiple Assignments
Multiple assignments can be written in one continuous statement.
Example:
assign Mux = (S == 0) ? A : 'bz, assign Mux = (S == 0) ? A : 'bz;
Mux = (S == 1) ? B : 'bz, => assign Mux = (S == 1) ? B : 'bz;
Mux = (S == 2) ? C : 'bz, assign Mux = (S == 2) ? C : 'bz;
Mux = (S == 3) ? D : 'bz; assign Mux = (S == 3) ? D :'bz;

The target in a continuous assignment can be one of the following:

• Scalar net // a , b
• Vector net //wire [6:0] Y
• Constant bit-select of a vector // Y[1] , Y[5]
• Constant part-select of a vector // Y [3:1]
• Concatenation of any of the above // {a , b}

Example:
wire Cout , Cin;
wire [3:0] Sum, A, B;
…
assign {Cout, Sum} = A + B + Cin;

Data Flow Modeling EC6203 Reconfigurable System Design

 Example
Example: 1- bit full adder.
module FA (A , B, Cin, Sum, Cout) ;
input A, B, Cin;
output Sum, Cout ;
assign Sum = A ^ B ^ Cin;
assign Cout = (A & Cin) | (B & Cin) | (A & B) ;
endmodule

• There are two continuous assignments.

• These assignments are concurrent. (order independent)
• Execution based on events that occur on operands used in the right hand
side expression.
• If A changes, both the continuous assignments are evaluated.
• The right-hand side expressions are evaluated and the results are
assigned to the left-hand side targets concurrently.
Data Flow Modeling EC6203 Reconfigurable System Design
 Net Declaration Assignment
• A continuous assignment can appear as part of a net declaration itself. (implicit continuous
assignment)
• A net declaration assignment declares the net along with a continuous assignment.
• It is a convenient form of declaring a net and then writing a continuous assignment.
Example:
wire Clear ;
assign Clear = 'b1 ; //is equivalent to the net declaration assignment.
wire Clear = 'b1 ;
wire #10 clear = 'b1 ; //implicit continuous assignment delay.
Example:
wire [3:0 ] Sum = 4' b0;
wire Clear = 'b1 ;
....
wire A_GT_B = A > B,
B_GT_A = B > A;

• Multiple net declaration assignments on the same net are not allowed.
• If multiple assignments are necessary, continuous assignments must be used.

Data Flow Modeling EC6203 Reconfigurable System Design

 Delay
• A delay can be explicitly specified in a continuous assignment.
• If no delay is specified in a continuous assignment: the assignment of the right-hand side
expression to the left-hand side target occurs with zero delay.
Example:
assign #6 Y = A | B;
• The delay specified, #6, is the delay between the right-hand side and the left hand side.
• If a change of value occurs on Late at time 5, then the expression on the right-hand side of the
assignment is evaluated at time 5,
• A will be assigned a new value at time 11 (= 5 + 6).

Data Flow Modeling EC6203 Reconfigurable System Design

 Delay
What happens if the right-hand side changes before it propagates to the left-hand side?
Answer: The latest value change is applied.
Example:
assign #4 C = D;

Value changes faster than delay

• The rising edge on “D” at 5 gets scheduled to appear on “C” at 9, but “D” goes back to 0
at 8, Hence the scheduled value on “C” is deleted.
• The pulse on “D” occurring between 18 and 20 gets filtered out.
• *The changes on the right-hand side that occur within the delay interval are filtered out.

Data Flow Modeling EC6203 Reconfigurable System Design

 Delay
There are 2 types of delay models described as below:
i. Transport delay and ii. Inertial delay.

Transport delay:
• This delay represents pure propagation delay,
• Any changes on an input is transported to the output after the specified delay.
• Spikes would be propagated through instead of being ignored as in the inertial delay
case.

Inertial delay:
• It represents the time for which an input value must be stable before the value is
allowed to propagate to the output.
• If the value on the right-hand side changes within the delay period, the former
value does not propagate to the output.
• This delay model is often used to filter out unwanted spikes and transients on
signals.
• In addition, the value appears at the output after the specified delay.
Data Flow Modeling EC6203 Reconfigurable System Design
 Delay
For each delay specification, up to three delay values can be specified.
i. Rise delay
ii. Fall delay
iii. Turn-off delay
Syntax:
assign #( rise , fall , turn-off ) LHS _ target = RHS _ expression ;

Example:
assign #4 A = Q | L ; // One delay value.
assign #(4, 8) A = Q ; // Two delay values.
assign #(4, 8, 6) A = - B & D; // Three delay values
assign Bus = MemAddr [ 7 : 4 ] ; //No delay value .

Data Flow Modeling EC6203 Reconfigurable System Design

 Net Delays
• A delay can also be specified in a net declaration as follows:
wire #5 A;
This delay indicates the delay between a change of value of a driver for A
and the net A itself.
assign #2 A = B & C;

• First the assignment delay is used and then any net delay is added on.
• An event on B, say at time 10, causes the right-hand side expression to be
evaluated.
• If the result is different, it is assigned to A after 2 time units, that is, at time 12.
• Since A has a net delay specified, the actual assignment to the net A occurs at
time 17 time units (= 10 + 2 + 5).
Data Flow Modeling EC6203 Reconfigurable System Design
 Design Example
Example-1: Master-slave D flip flop (data flow model)

Data Flow Modeling EC6203 Reconfigurable System Design

 Design Example
Example-2 : 8-bit parameterized magnitude comparator (data Flow Model)

Data Flow Modeling EC6203 Reconfigurable System Design

References
Books:
A Verilog HDL Primer: by J Bhasker.
Design Through Verilog HDL: T.R. Padmanavan, B. Bala Tripura Sundari
Verilog Digital Design Synthesis: Samir Palnitkar.

website:
asic-world.com
www.xilinx.com