Transistor: Building Block of Computers

Microprocessors contain millions of transistors

• Intel Pentium 4 (2000): 48 million
• IBM PowerPC 750FX (2002): 38 million

Chapter 3 • IBM/Apple PowerPC G5 (2003): 58 million

Digital Logic Logically, each transistor acts as a switch

Structures
Based on slides © McGraw-Hill
Additional m aterial © 2004/2005 Lewis/Martin
Combined to implement logic functions
• AND, OR, NOT
Combined to build higher-level structures
• Adder, multiplexer, decoder, register, …
Combined to build processor
• LC-3

CSE 240 3-2

How do we represent data in a computer? A Transistor Analogy: Computing with Air

At the lowest level, a computer has electronic “plumbing” Use air pressure to encode values
• Operates by controlling the flow of electrons • High pressure represents a “1” (blow)
• Low pressure represents a “0” (suck)
Easy to recognize two conditions: Valve can allow or disallow the flow of air
1. Presence of a voltage – we’ll call this state “1”
• Two types of valves
2. Absence of a voltage – we’ll call this state “0”
N-Valve P-Valve

Low (Off) Low (On)

Computer use transistors as switches to manipulate bits
• Before transistors: tubes, electro-mechanical relays (pre 1950s) hole
• Mechanical adders (punch cards, gears) as far back as mid-1600s
Before describing transistors, we present an analogy… High (On) High (Off)
CSE 240 3-3 CSE 240 3-4

1
 Pressure Inverter Pressure Inverter (Low to High)

High High

P-Valve P-Valve

In Out Low High

N-Valve N-Valve

Low Low

CSE 240 3-5 CSE 240 3-6

Pressure Inverter Pressure Inverter (High to Low)

High High

P-Valve P-Valve

High Low

N-Valve N-Valve

Low Low

CSE 240 3-7 CSE 240 3-8

2
 Analogy Explained Transistors as Switches
Pressure differential → electrical potential (voltage)
• Air molecules → electrons Two types N-Valve N-MOSFET
• High pressure → high voltage • N-type
• Low pressure → low voltage • P-type

Air flow → electrical current Properties

• Pipes → wires • Solid state (no moving parts) P-Valve P-MOSFET
• Air only flows from high to low pressure • Reliable (low failure rate)
• Electrons only flow from high to low voltage • Small (90nm channel length)
• Flow only occurs when changing from 1 to 0 or 0 to 1 • Fast (<0.1ns switch latency)

Valve → transistor
• The transistor: one of the century’s most important inventions
CSE 240 3-9 CSE 240 3-10

MOS + FET N-type MOS Transistor

gate
insulator • When Gate has positive voltage,
source drain short circuit between #1 and #2
channel (switch closed)
(cross-section view of a MOSFET) • When Gate has zero voltage,
MOS: three materials needed to make a transistor open circuit between #1 and #2
(switch open)
• Metal (Al, W, Cu): conductor
• Oxide (SiO2 ): insulator Gate = 1
• Semiconductor (doped Si): conducts under certain conditions
FET: field effect (the mechanism) transistor
• Voltage on gate: current flows source to drain (transistor on)
• No voltage on gate: no current (transistor off)
Terminal #2 connected
Gate = 0
Recall, two types of MOSFET: n and p
to GROUND (0V).

CSE 240 3-11 CSE 240 3-12

3
 P-type MOS Transistor Inverter (NOT Gate)
P-type is complementary to n-type Power
• When Gate has positive voltage,
open circuit between #1 and #2
(switch open)
• When Gate has zero voltage,
short circuit between #1 and #2
(switch closed)

Gate = 1 Truth table

Ground
In Out

Terminal #1 connected 0 1
to POWER Gate = 0
1 0
(in this example, +2.9V)

CSE 240 3-13 CSE 240 3-14

CMOS Circuit NAND Gate (NOT-AND)

Inverter is an example of Complementary MOS (CMOS) Power
Uses both n-type and p-type MOS transistors
• p-type
Attached to POWER (high voltage)
Pulls output voltage UP when input is zero
• n-type
Attached to GROUND (low voltage)
Pulls output voltage DOWN when input is one
A B C

For all inputs, make sure that output is either connected to GROUND 0 0 1
or to POWER, but not both! (why?) 0 1 1
1 0 1
Ground
1 1 0
CSE 240 3-15 CSE 240 Note: Parallel structure on top, serial on bottom. 3-16

4
 AND Gate NOR Gate (NOT-OR)
A B C
Power Power
0 0 0
0 1 0
1 0 0
1 1 1

A B C
0 0 1
0 1 0
Add inverter to NAND. 1 0 0
Ground Ground
1 1 0
CSE 240 3-17 CSE 240 Note: Serial structure on top, parallel on bottom. 3-18

OR Gate Basic Gates

A B C
Power From Now On… Gates
0 0 0 • Covered transistors mostly so that you know they exist
0 1 1 • Note: “Logic Gate” not related to “Gate” of transistors
1 0 1
Will study implementation in terms of gates
1 1 1
• Circuits that implement Boolean functions

NOT/INV NAND AND NOR OR

Ground More complicated gates from transistors possible

Add inverter to NOR. • XOR, Multiple-input AND-OR-Invert (AOI) gates

CSE 240 3-19 CSE 240 3-20

5
 More than 2 Inputs? Visual Shorthand for Multi-bit Gates
AND/OR can take any number of inputs Use a cross-hatch mark to group wires
• AND = 1 if all inputs are 1 • Example: calculate the AND of a pair of 4-bit numbers
• OR = 1 if any input is 1 • A3 is “high-order” or “most-significant” bit
• Similar for NAND/NOR • If “A” is 1000, then A3 = 1, A2 = 0, A1 = 0, A0 = 0
Implementation
• Multiple two-input gates or single CMOS circuit A0 Out0
B0

A1 4
Out1 A 4
B1 Out
B
A2 Out2 4
B2

A3 Out3
B3

CSE 240 3-21 CSE 240 3-22

Shorthand for Inverting Signals Logical Completeness

Invert a signal by adding either AND, OR, NOT can implement ANY truth table
• A before/after a gate A B Cin S A B Cin
• A “bar” over letter 0 0 0 0
1. AND combinations
0 0 1 1
A that yield a "1" in the
B A AND B 0 1 0 1 truth table
0 1 1 0
1 0 0 1 S
A A AND B
B 1 0 1 0
1 1 0 0 2. OR the results
of the AND gates
1 1 1 1
A A OR B
B

CSE 240 3-23 CSE 240 3-24

6
 Logical Completeness via PLAs DeMorgan's Law
Any truth table as a Programmable Logic Array (PLA) Converting AND to OR (with some help from NOT)
• Traditionally a grid of AND and OR gates
Consider the following gate: To convert AND to OR
• Configurable by removing wires
(or vice versa),
A AND B = A OR B
Single-output custom PLA (as on previous slide): invert inputs and output.
• One AND gate per row with “1” in output in truth table
A AND B = A OR B
• Maximum number of AND gates: 2n for n inputs
• One OR gate
A B A B A AND B A AND B
0 0 1 1 1 0
Multiple-output custom PLA:
• Build multiple single-output PLAs 0 1 1 0 0 1 A AND B = A OR B
• Share AND gates “in common” 1 0 0 1 0 1
• One OR gate per output column in truth table
1 1 0 0 0 1

CSE 240 3-25 CSE 240 Why might this be useful? 3-26

Summary Next Time

MOS transistors are used as switches to implement Lecture
logic functions • Combinational Logic Circuits
• n-type: connect to GROUND, turn on (with 1) to pull down to 0
• p-type: connect to POWER, turn on (with 0) to pull up to 1 Reading
• Chapter 3.3
Basic gates: NOT, NOR, NAND
• Logic functions are usually expressed with AND, OR, and NOT Quiz
• Universal: any truth table to simple gates (via a PLA) • Online (as always)

DeMorgan's Law Upcoming

• Convert AND to OR (and vice versa) by inverting inputs/output • HW2 due next Friday

CSE 240 3-27 CSE 240 3-28

7
 AND, OR, NOT Gates: What Good Are They?
Last time:
• Transistors and gates
• Can implement any logical function using gates (using PLAs)

Chapter 3 Today:
• We’ll use gates to create some building blocks of a processor
Digital Logic • One goal: automate binary arithmetic from Chapter 2
• Continuing on our bottom-up journey
Structures Next time:
• Storing bits (memory)
Based on slides © McGraw-Hill • Circuits with “state”
Additional m aterial © 2004/2005 Lewis/Martin

CSE 240 3-30

Incrementer One-bit Incrementer

16 16
Let’s create a incrementer A +1 S Implement a single-column of an incrementer
• Input: A (as a 16-bit 2’s complement integer) CarryInn
• Output: A+1 (also as a 16-bit 2’s complement integer) 00001011
1 1
+00000001 An +1 Sn
Approach #1 (impractical):
00001100
• Use PLA-like techniques to implement circuit CarryOutn
An Cin
• Problem: 216 or 65536 rows, 16 output columns
• In theory, possible; in practice, intractable An Cin Sn Cout
0 0 0 0
Approach#2 (pragmatic): S
0 1 1 0
• Create a 1-bit incrementer circuit
1 0 1 0
• Replicate it 16 times
1 1 0 1
Cout
CSE 240 3-31 CSE 240 3-32

8
 Aside: XOR N-bit Incrementer
Chain N 1-bit incrementers together
An Cin Sn Cout CarryIn0
A 1 1
0 0 0 0 S A0 S0
+1
0 1 1 0
CarryOut0
CarryIn1
1 0 1 0
1 1
1 1 0 1 Cout A1 +1 S1
Cin
CarryOut1 …but how do we
4-bit CarryIn2
A Cin correctly handle the
example 1 1
A2 +1 S2 least-significant bit?
XOR
CarryOut2
A CarryIn3
S 1 1
Cin A3 +1 S3
CarryOut3
CSE 240 3-33 CSE 240 3-34

N-bit Incrementer, continued Adder

How do we handle the least-significant bit? Conceptually similar to an incrementer
1 • Build a one-bit slice, replicate n times

00001011 CarryIn0 CarryInn

1 1 00001011 1
+00000001 A0 +1 S0 An 1
CarryOut0 +00110011 1 Add Sn
00001100 CarryIn1 Bn
1 1 00111100
A1 +1 S1 CarryOutn
00001011 Cin = 1 CarryOut1
CarryIn2
+00000000 1 1
A2 +1 S2
00001100
CarryOut2
No longer needed;
implicitly encoded
...

CSE 240 with Cin 3-35 CSE 240 3-36

9
 One-bit Adder CarryInn N-bit Adder
1 CarryIn
Add two bits and carry-in An 1 CarryIn
produce one-bit sum and carry-out 1 Add Sn 16
Bn
CarryIn0 A 16
CarryOutn A0 + S
S0 16
A B Cin S Cout B0 Add
B
0 0 0 0 0 CarryOut0
CarryIn1 CarryOut
0 0 1 1 0 A1
0 1 0 1 0 Add S1
B1
0 1 1 0 1 CarryOut1 CarryOut: useful for
CarryIn2
1 0 0 1 0
A2
detecting overflow
1 0 1 0 1 S2
B2 Add
1 1 0 0 1
CarryOut2 CarryIn: assumed to
1 1 1 1 1
be zero if not present

...
CSE 240 3-37 CSE 240 3-38

Aside: Efficient Adders Subtracter

Full disclosure: Build a subtracter from an adder
• Our adder: Ripple-carry adder • Calculate A - B = A + -B
• No one (sane) actually uses ripple-carry adders • Negate B
• Why? way too slow • Recall -B = NOT(B) + 1
• Latency proportional to n
Approach#1: Approach#2:
We can do better CarryIn 1
• Many ways to create adders with latency proportional to log2(n) 16 16 CarryIn
• In theory: constant latency (build a big PLA) A 16 A 16
• In practice: too much hardware, too many high-degree gates S S
16 16 16 16 16
• “Constant factor” matters, too B +1 B
• More on this topic in CSE371

Now, let’s create an adder/subtracter

CSE 240 3-39 CSE 240 3-40

10
 …But First, The Multiplexer (MUX) The Multiplexer (MUX)
Selector/Chooser of signals In general
• Multi-way switch • N select bits chooses from 2N inputs
2-to-1 Mux 4-to-1 Mux • An incredibly useful building block

0 1 00 01 10 11
2 2 2 2 Multi-bit muxes
• Can switch an entire “bus” or group of signals
• Switch n-bits with n muxes with the same select bits
S
16 2
S 16
16
A 16
O
16
B

CSE 240 3-41 CSE 240 3-42

Adder/Subtracter - Approach #1 Adder/Subtracter - Approach #2

Adder Subtracter Adder Subtracter
CarryIn CarryIn
16 1 16 1
16 CarryIn 16 CarryIn
A 16 A 16
S A 16 S A 16
16 S 16 S
B 16 16 B 16 16
B B
CarryOut CarryOut
Adder/Subtracter Adder/Subtracter
16
Add/Sub 1
A 16 Add/Sub
16 CarryIn
16 1
B 16 A
S 16
16 S
16 B 16

16
CSE 240 3-43 CSE 240 3-44

11
 Ok, So We Can Add and Subtract

Other arithmetic operations similar

• Even floating point operations

We can calculate; but we can’t remember

Chapter 3
• Next time: storage and memory
• After that: simple “state machines”
Digital Logic
• After that: a simple processor Structures
Remember: Readings, Quizzes, and Homework
• We’ll return Homework 1 on Wednesday Based on slides © McGraw-Hill
Additional m aterial © 2004/2005 Lewis/Martin
• Homework 2 due Friday

CSE 240 3-45

Combinational vs. Sequential Logic Storage - Cross-Coupled Inverters

Combinational Circuit Cross-coupled inverters (INV) gates
• Always gives the same output for a given set of inputs • Holds value Q and Q’ (Q’ is the same as Q)
For example, adder always generates sum and carry,
regardless of previous inputs 1 0 0 1
Sequential Circuit Q’ Q Q’ Q
• Stores information
• Output depends on stored information (state) plus input
Given input might produce different outputs, depending on • Read: get value from either Q or Q’
stored information
• Example: ticket counter Maintains its “state”, but how do we change the state?
Advances when you push the button • Write: Option #1: put opposite values on Q and Q’ simultaneously
Output depends on previous state
Requires “analog” overdriving of Q and Q’
• Useful for building “memory” elements and “state machines”

CSE 240 3-47 CSE 240 3-48

12
 Storage - NANDs Storage - Cross-Coupled NANDs (R-S Latch)
Option #2: “Digital” alternative for changing state Write either a zero or one
Write: change Q to one Maintains state • When S=1 and R=1, “quiescent” state; maintains value
1 1
1 even after S = 1 S S
1Q 0Q
0 1
S S S 0 1
1 0Q 0 1Q 0 1Q
1 1
R R
Write: change Q to zero • When S=0 and R=1, state changes to one (“set”)
• When S=1 and R=0, state changes to zero (“reset” or “clear”)

0 1Q 1 0Q 1 0Q 0 1
S S
0 1Q 1 0Q
1 0 1
R R R
Maintains state 1 0
even after R = 1 3-49 R R
CSE 240 CSE 240 3-50

Storage - Cross-Coupled NANDs (R-S Latch) Gated D-Latch

What happens with S=0 and R=0? Add logic to an R-S latch
• Short answer: bad things • Create a better interface
• Long answer: value stored will depend on timing on circuit Two inputs: D (data) and WE (write enable)
0
• When WE = 1, latch is set to value of D
S S = NOT(D), R = D
1 1Q
• When WE = 0, latch continues to hold previous value
S = R = 1
0
R • Does not allow S=0, R=0 case to occur

• Does S or R go to one first? 1

If they change at the same time? Q
WE 0 1
Oscillation or meta-stability can result D
0
• Let’s make sure this can never happen…
1

CSE 240 3-51 CSE 240 3-52

13
 Register Aside: More on Representing Multi-bit Values
A register stores a multi-bit value Number bits from right (0) to left (n-1)
• A collection of D-latches, controlled by a common WE • Just a convention -- could be left to right, but must be consistent
• When WE=1, n-bit value D is written to register Use brackets to denote range:
WE D[l:r] denotes bit l to bit r, from left to right
15 12 8 4 0
Q0
D0 A = 0101 0011 0101 0101
WE

3 3
Q1 D D Q A[14:9] = 101001 A[2:0] = 101
D1
16

3
May also see A<14:9> [2:0]
Q1 • Especially in hardware block diagrams. 6
D2 [14:9]
CSE 240 3-53 CSE 240 3-54

Let’s Try to Build a Counter What’s Missing? The Clock

1 A clock controls when registers are “updated”
• Oscillating global signal with fixed period
3 3 3
Cnt +1 • Typical clock frequencies today: a couple of gigahertz

“1”
“0”
How quickly will this count? One time→

• Timing dependent Cycle

• Corresponds to <1 nanosecond between one rise and the next
Will it even work?
• Generated on-chip by special circuitry (for example, oscillating
• Probably not
ring of inverters)
• D-latches are “transparent”
Allows next input to immediately flow to output
Outputs will never be “stable”

CSE 240 3-55 CSE 240 3-56

14
 Let’s Try Again: a Counter Example of Incorrect Operation
Clock Initial state: 0102
3 3 3 WE 1
Cnt +1 0
1 D 0 A0 S
+1 1 0
latch

Solves half the problem 0

• Controls the rate of updates 1 D 1 A1 1 S1
+1
latch

Remaining problem 0
0 D 0 A2 0 S2
• When clock=1, same problem +1
latch
• D-latches are still transparent

CSE 240 3-57 CSE 240 3-58

Example of Incorrect Operation Example of Incorrect Operation

Set WE (Write Enable) to 1 D latches write new value: 0112
Goal: 1002
WE 1 WE 1
1 1
1 D 0 A0 S 1 D 1 A0 S
+1 1 0 +1 1 0
latch latch

0 0
1 D 1 A1 S 1 D 1 A1 S
+1 1 1 +1 1 1
latch latch

0 0
0 D 0 A2 S 0 D 0 A2 S
+1 0 2 +1 0 2
latch latch

CSE 240 3-59 CSE 240 3-60

15
 Example of Incorrect Operation Example of Incorrect Operation
Incrementer calculates 1st bit Incrementer calculates 2nd bit, 1st bit latched

WE 1 WE 1
1 1
0 D 1 A0 S 0 D 0 A0 S
+1 0 0 +1 0 0
latch latch

1 1
1 D 1 A1 1 S1 0 D 1 A1 0 S1
+1 +1
latch latch

0 1
0 D 0 A2 0 S2 0 D 0 A2 0 S2
+1 +1
latch latch

CSE 240 3-61 CSE 240 3-62

Example of Incorrect Operation Example of Incorrect Operation

Incrementer calculates 3rd bit, 2nd bit latched, 1st and 3rd bits latched
1st bit re-calculated value is: 1012 (not the desired 1002)
WE 1 WE 1
1 1
1 D 0 A0 S 1 D 1 A0 S
+1 1 0 +1 1 0
latch latch

0 0
0 D 0 A1 S 0 D 0 A1 S
+1 0 1 +1 0 1
latch latch

1 1
1 D 0 A2 S 1 D 1 A2 S
+1 1 2 +1 1 2
latch latch

CSE 240 3-63 CSE 240 3-64

16
 Correct Operation Correct Operation
Additional D-latches, WE is NOT(Clock) and Clock Clock switches to 1, 2nd latch WE = 1
Initial state: 0102
Clock 1 Clock 1
0 1
1 D 1 Q0 D 0 A0 1 S0 1 D 1 Q0 D 0 A0 1 S0
+1 +1
latch latch latch latch

0 0
1 D 1 Q1 D 1 A1 1 S1 1 D 1 Q1 D 1 A1 1 S1
+1 +1
latch latch latch latch

0 0
0 D 0 Q2 D 0 A2 S 0 D 0 Q2 D 0 A2 S
+1 0 2 +1 0 2
latch latch latch latch

CSE 240 3-65 CSE 240 3-66

Correct Operation Correct Operation

D latches write new value: 0112 Incrementer begins calculation
Goal: 1002
Clock 1 Clock 1
1 1
1 D 1 Q0 D 1 A0 S 0 D 1 Q0 D 1 A0 S
+1 1 0 +1 0 0
latch latch latch latch

0 1
1 D 1 Q1 D 1 A1 S 1 D 1 Q1 D 1 A1 S
+1 1 1 +1 1 1
latch latch latch latch

0 0
0 D 0 Q2 D 0 A2 S 0 D 0 Q2 D 0 A2 S
+1 0 2 +1 0 2
latch latch latch latch

CSE 240 3-67 CSE 240 3-68

17
 Correct Operation Correct Operation
Incrementer calculates 2nd bit, Incrementer calculates 3rd bit,
First bit not written to latch 1st, 2nd bits not written to latch
Clock 1 Clock 1
1 1
0 D 1 Q0 D 1 A0 0 S0 0 D 1 Q0 D 1 A0 0 S0
+1 +1
latch latch latch latch

1 1
0 D 1 Q1 D 1 A1 0 S1 0 D 1 Q1 D 1 A1 0 S1
+1 +1
latch latch latch latch

1 1
0 D 0 Q2 D 0 A2 S 1 D 0 Q2 D 0 A2 S
+1 0 2 +1 1 2
latch latch latch latch

CSE 240 3-69 CSE 240 3-70

Correct Operation Correct Operation

Correct value ready to latch (1002), circuit quiescent Clock changes to 0

Clock 1 Clock 1
1 0
0 D 1 Q0 D 1 A0 S 0 D 1 Q0 D 1 A0 S
+1 0 0 +1 0 0
latch latch latch latch

1 1
0 D 1 Q1 D 1 A1 S 0 D 1 Q1 D 1 A1 S
+1 0 1 +1 0 1
latch latch latch latch

1 1
1 D 0 Q2 D 0 A2 S 1 D 0 Q2 D 0 A2 S
+1 1 2 +1 1 2
latch latch latch latch

CSE 240 3-71 CSE 240 3-72

18
 Correct Operation Correct Operation
2nd set of latches write correct value, circuit quiescent Clock changes back to 1, next increment begins

Clock 1 Clock 1
0 1
0 D 0 Q0 D 1 A0 0 S0 0 D 0 Q0 D 0 A0 0 S0
+1 +1
latch latch latch latch

1 1
0 D 0 Q1 D 1 A1 0 S1 0 D 0 Q1 D 0 A1 0 S1
+1 +1
latch latch latch latch

1 1
1 D 1 Q2 D 0 A2 S 1 D 1 Q2 D 1 A2 S
+1 1 2 +1 1 2
latch latch latch latch

CSE 240 3-73 CSE 240 3-74

D Flip-Flop (or master-slave flip-flop) D Flip-Flop - WE = 0 Latch #2

D Flip-Flop is a pair of D latches Latch #1
• Stupid name, but it stuck Qinter Q
D
• Isolate next state from current state

D Q 0 1
WE 0 1
Clock
x

WE
Clock When WE = 0
• Latch 1: writing disabled (output is stable Q inter)
Two phases:
• Latch 2: writing enabled (Q = Q inter)
• Clock = 1, Clock = 0

CSE 240 3-75 CSE 240 3-76

19
 D Flip-Flop - Phase 1 Latch #2 D Flip-Flop - Phase 2 Latch #2
Latch #1 Latch #1
Qinter Q Qinter Q
D D

0 1 1 0
WE 1 1 WE 1 0
Clock Clock
1
Phase 2 0
Phase 1 • Clock = 0
• Clock = 1 • Latch 1: writing enabled (Qinter = D)
• Latch 1: writing disabled (output is stable Q inter) • Latch 2: writing disabled (output is stable Q)
• Latch 2: writing enabled (Q = Q inter) Back to Phase 1
• Q becomes Q inter

CSE 240 3-77 CSE 240 3-78

Working Counter Memory

Use a clocked register (made of D flip-flops) Now that we know how to store bits, we can build a
1 memory – a logical k by m array of stored bits
Clock WE
3 3 3
Cnt +1

More simply Address Space:

k = 2n
• If WE = 1 assumed if WE is not present number of locations locations •
(usually a power of 2) •
•
3 3 3
Cnt +1

Addressability:
Use WE input for conditional counter (stop watch) number of bits per location m bits
(e.g., byte-addressable)

CSE 240 3-79 CSE 240 3-80

20
 Memory Interface 22 by 3-bit memory
n Read operation 2
A A
m
Din
WE

3 3 3 3
D0 D0

Decoder Memory
3 3 3 3
(2n by m-bit)
D1 m
D1 3
Dout Dout
22 or 4 registers
3 3 3 3
D2 D2

3 3 3 3
D3 D3
CSE 240 3-81 CSE 240 3-82

22 by 3-bit memory The Decoder

Write operation 2 n inputs, 2n outputs
A • Exactly one output is 1 for each possible input pattern
3
Din
WE

3 3
D0
Decoder

3 3
3
D1 Dout 2-bit
3 3
decoder
D2

3 3
D3
CSE 240 3-83 CSE 240 3-84

21
 22 by 3-bit memory - Multiple “Ports” 22 by 3-bit memory - Multiple Read Ports
Independent Read/Write AR1
2 2
AR AR2
3 3
DW DW
WE WE
AW AW
2 3 3 3 3
D0 D0

Decoder

Decoder
3 3 3 3 3
3 DR1
D1 DR D1 3
DR2
3 3 3 3
D2 D2

3 3 3 3
D3 D3
CSE 240 3-85 CSE 240 3-86

An Efficient 22 by 3-bit Memory - Single Port More Memory Details

word select word WE
address input This is still not the way actual memory is implemented
bits
• Real mem: Fewer transistors, much more dense, relies on analog
write properties
enable
But the logical structure is similar
• Address decoder
• Word select line, word write enable
latch
• Bit line
(not flip-flop)
Two basic kinds of RAM (Random Access Memory)
Static RAM (SRAM)
• Fast, maintains data as long as power applied
Dynamic RAM (DRAM)
• Slower but denser, bit storage decays – must be periodically
address refreshed
decoder
CSE 240 output bits mux 3-87 CSE 240 Also, non-volatile memories: ROM, PROM, flash, … 3-88

22
 State Machine Combinational vs. Sequential
Another type of sequential circuit Two types of “combination” locks
• Combines combinational logic with storage
• “Remembers” state, and changes output (and state)
based on inputs and current state
30
25 5

State Machine 4 1 8 4 20 10
15

Inputs Combinational Outputs

Combinational Sequential
Logic Circuit
Success depends only on Success depends on
the values, not the order in the sequence of values
Storage
Elements
which they are set. (e.g, R-13, L-22, R-3).

CSE 240 3-89 CSE 240 3-90

State State of Sequential Lock

The state of system is snapshot of all relevant elements
of system at moment snapshot is taken
Examples
• The state of a basketball game can be represented by
the scoreboard
Number of points, time remaining, possession, etc.
• The state of a tic-tac-toe game can be represented by
the placement of X’s and O’s on the board (and turn)
Our lock example has four different states, labeled A-D:
A: The lock is not open,
and no relevant operations have been performed
B:The lock is not open,
and the user has completed the R-13 operation
C:The lock is not open,
and the user has completed R-13, followed by L-22
D:The lock is open

CSE 240 3-91 CSE 240 3-92

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 Sequential Lock State Diagram Finite State Machine
Shows states and actions that cause a transition A description of a system with the following
between states components:

1. A finite number of states

2. A finite number of external inputs
3. A finite number of external outputs
4. An explicit specification of all state transitions
5. An explicit specification of what determines each
external output value

Often described by a state diagram

(open) • Inputs trigger state transitions
• Outputs are associated with each state (or with each transition)

CSE 240 3-93 CSE 240 3-94

Implementing a Finite State Machine Storage

Combinational logic Master-slave flip-flop stores one state bit
• Determine outputs and next state.
Storage elements Number of storage elements (flip-flops)
• Maintain state representation. • Determined by number of states (and representation of states)

State Machine
Examples
Inputs Outputs • Sequential lock
Combinational
Logic Circuit Four states – two bits
• Basketball scoreboard
8 bits for each score, 5 bits for minutes, 6 bits for seconds,
Storage
Elements
1 bit for possession arrow, 1 bit for half, …
Clock

CSE 240 3-95 CSE 240 3-96

24
 Complete Example Traffic Sign State Diagram
A blinking traffic sign
• No lights on
• 1 & 2 on
3
• 1, 2, 3, & 4 on 4
1
• 1, 2, 3, 4, & 5 on 5
2
Switch on
• (repeat as long as switch
is turned on) Switch off

DANGER
MOVE
RIGHT State bit S1
State bit S0
Outputs

CSE 240 3-97 CSE 240 3-98

Transition on each clock cycle.

Traffic Sign State Diagram: State 00 Traffic Sign State Diagram: State 01

CSE 240 3-99 CSE 240 3-100

Transition on each clock cycle. Transition on each clock cycle.

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 Traffic Sign State Diagram: State 10 Traffic Sign State Diagram: State 11

CSE 240 3-101 CSE 240 3-102

Transition on each clock cycle. Transition on each clock cycle.

Traffic Sign State Diagram: State 00 Traffic Sign Truth Tables

Outputs Next State: S1’S0’
(depend only on state: S1S0) (depend on state and input)
Lights 1 and 2 Switch

Lights 3 and 4 In S1 S 0 S 1’ S 0’
Light 5
0 X X 0 0
S1 S0 Z Y X Don’t care 1 0 0 0 1
(1 or 0)
0 0 0 0 0 1 0 1 1 0
0 1 1 0 0 1 1 0 1 1

1 0 1 1 0 1 1 1 0 0
1 1 1 1 1
Whenever In=0, next state is 00.

CSE 240 3-103 CSE 240 3-104

Transition on each clock cycle.

26
 Traffic Sign Logic Programmable State Machines
What if we want to change the pattern of the sign?
• An alternative state machine implementation
In/S1 /S0 S
• Use a memory indexed by state number
000 00
001 00
1 23 by 2-bit 010 00
Input [2] 3 2
011 00
S1’ 2
[1:0] 100 01
2 3 101 10
Output
(Z, Y, X) 110 11
S0’
22 by 3-bit 111 00
S1 S X/Y/Z
Master-slave 00 000
flip-flop
2 01 100

State
S0 10 110
11 111
CSE 240 3-105 CSE 240 3-106

Programmable State Machines From Logic to Data Path

Change to a two-state pattern: The data path of a computer is all the logic used to
• All off process information.
In/S1 /S0 S
• All on • See the data path of the LC-3 on next slide
State: 00 State: 10 State: 00 000 00
001 --
1 23 by 2-bit 010 00 Combinational Logic
Input [2] 3 2
011 -- • Decoders -- convert instructions into control signals
[1:0] 100 10
2 • Multiplexers -- select inputs and outputs
2 3 101 --
Output • ALU (Arithmetic and Logic Unit) -- operations on data
(Z, Y, X) 110 00
111 --
Sequential Logic
22 by 3-bit
S Z/Y/Z • State machine -- coordinate control signals and data movement
00 000 • Registers and latches -- storage elements
2 01 --
State

10 111
11 --
CSE 240 3-107 CSE 240 3-108

27
 LC-3 Data Path Looking Forward…
We’ve touched upon basic digital logic
Combinational • Transistors
Logic • Gates
• Storage (latches, flip-flops, memory)
• State machines
Storage
Build some simple circuits
• Incrementer, adder, subtracter, adder/subtracter
• Counter (consisting of register and incrementer)
• Hard-coded traffic sign state machine
• Programmable traffic sign state machine
State Machine

Up next: a computer as a (simple?) state machine

CSE 240 3-109 CSE 240 3-110

Next Time

Topic
• The von Neumann Model

Readings
• Chapter 4.0 - 4.2

Online quiz
• You know the drill!

CSE 240 3-111

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