1956 C03

1956_C03.
fm Page 215 Thursday, August 7, 2003 10:10 PM
3
Positive Output Super-Lift Luo-Converters
Voltage lift (VL) technique has been successfully employed in design of DC/
DC converters, e.g., three series Luo-converters. However, the output voltage
increases in arithmetic progression. Super-Lift (SL) technique is more pow-
erful than VL technique, its voltage transfer gain can be a very large number.
SL technique implements the output voltage increasing in geometric pro-
gression. It effectively enhances the voltage transfer gain in power series.
3.1 Introduction
This chapter introduces positive output super lift Luo-converters. In order
to differentiate these converters from existing VL converters, these convert-
ers are called positive output super-lift Luo-converters. There are several sub-
series:
• Main series — Each circuit of the main series has only one switch
S, n inductors for nth stage circuit, 2n capacitors, and (3n – 1) diodes.
• Additional series — Each circuit of the additional series has one
switch S, n inductors for nth stage circuit, 2(n + 1) capacitors, and
(3n + 1) diodes.
• Enhanced series — Each circuit of the enhanced series has one switch
S, n inductors for nth stage circuit, 4n capacitors, and (5n – 1) diodes.
• Re-enhanced series — Each circuit of the re-enhanced series has one
switch S, n inductors for nth stage circuit, 6n capacitors, and (7n – 1)
diodes.
• Multiple (j)-enhanced series — Each circuit of the multiple (j times)-
enhanced series has one switch S, n inductors for nth stage circuit,
2(1 + j)n capacitors and [(3 + 2j)n – 1] diodes.
In order to concentrate the voltage enlargement, assume the converters

are working in steady state with continuous conduction mode (CCM). The
conduction duty ratio is k, switch frequency is f, switch period is T = 1/f,
© 2003 by CRC Press LLC

1956_C03.fm Page 216 Thursday, August 7, 2003 10:10 PM
the load is resistive load R. The input voltage and current are Vin and Iin, out
voltage and current are VO and IO. Assume no power losses during the
conversion process, Vin × Iin = VO × IO. The voltage transfer gain is G:
VO
G=
Vin
3.2 Main Series

The first three stages of positive output super-lift Luo-converters — main
series — are shown in Figure 3.1 through Figure 3.3. For convenience, they
are called elementary circuits, re-lift circuit, and triple-lift circuit respectively,
and are numbered as n = 1, 2, and 3.
3.2.1 Elementary Circuit

The elementary circuit and its equivalent circuits during switch-on and -off
are shown in Figure 3.1. The voltage across capacitor C1 is charged to Vin.
The current iL1 flowing through inductor L1 increases with voltage Vin during
switch-on period kT and decreases with voltage –(VO – 2Vin) during switch-
off period (1 – k)T. Therefore, the ripple of the inductor current iL1 is
Vin V − 2Vin
∆iL1 = kT = O (1 − k )T (3.1)
L1 L1
2−k
VO = V (3.2)
1 − k in
The voltage transfer gain is
VO 2 − k
G= = (3.3)
Vin 1 − k
The input current iin is equal to (iL1 + iC1) during switch-on, and only equal
to iL1 during switch-off. Capacitor current iC1 is equal to iL1 during switch-
off. In steady–state, the average charge across capacitor C1 should not change.
The following relations are obtained:
iin−off = iL1−off = iC1−off iin−on = iL1−on + iC1−on kTiC1−on = (1 − k )TiC1−off

Iin D1 D2
IO
+
+
L1 C1 VC1
+ +
Vin –
C2 VC2 R VO
– –
S
–
(a) Circuit diagram

Iin
IO
+
+ + +
Vin L1 C1 Vin C2 VC2 R VO
– – –
–
(b) Equivalent circuit during switching-on
I in L1 C1
IO
+ VL1
– Vin + + +
Vin C2 VC2 R VO
– –
–
(c) Equivalent circuit during switching-off
FIGURE 3.1
Elementary circuit.
If inductance L1 is large enough, iL1 is nearly equal to its average current IL1.
Therefore,
1− k I 1− k
iin−off = iC1−off = I L1 iin−on = I L1 + I L1 = L1 iC1−on = I
k k k L1
and average input current
I in = kiin−on + (1 − k )iin−off = I L1 + (1 − k )I L1 = (2 − k )I L1 (3.4)
Considering
Vin 1 − k 2 VO 1− k 2
=( ) =( ) R
I in 2 − k IO 2−k

Iin D1 D2 V1 D4 D5
IO
+ + +
L1 C1 VC1 L2 C3 VC3
– – +
Vin R VO
D3 –
+ +
C2 VC2 S C4
– VC4
– –
(a) Circuit diagram
Iin
V1
IO
+
+ + + + +
C4
Vin L1 C1 Vin C2 VC2 L2 C3 V1 VC4 R VO
– – – – –
–
Iin L1 C1 V1 L2 C3
IO
+ VL1 VL2
– Vin + + – V1 + + +
Vin C2 V1 C4 VC4 R VO
– – –
–
FIGURE 3.2
Re-lift circuit.
the variation ratio of current iL1 through inductor L1 is
∆iL1 / 2 k(2 − k )TVin k(1 − k )2 R

ξ1 = = = (3.5)
I L1 2L1 I in 2(2 − k ) fL1
Usually ξ1 is small (much lower than unity), it means this converter nor-
mally works in the continuous mode.
The ripple voltage of output voltage vO is
∆Q I O (1 − k )T 1 − k VO
∆vO = = =
C2 C2 fC2 R
Therefore, the variation ratio of output voltage vO is
∆vO / 2 1− k
ε= = (3.6)
VO 2 RfC2
I in D1 D2 V1 D4 D5 V2 D7 D8
IO
+ + +
+ L1 C1 VC1 L2 C3 VC3 L3 C5 VC5 +
Vin _ _ _
R VO
_
D3 + D6 + S +
_
C2 VC2 C4 VC4 C6 VC6
_ _ _
(a) Circuit diagram

I in IO
V1 V2
+ + + + C6 +
+ + +
L2 C4 L3
Vin L1 C1 Vin C2 C3 V1 C5 V2 VC6 VO
V1 V2 _ R
_ _ _ _ _ _ _
(b) Equivalent circuit during switch-on
I in L1 C1 V1 L2 C3 V2 L3 C5
IO
_ _ _
+ V L1 Vin
+ V L2 V1
+ V L3 V2
+
+
+ + +
Vin C2 V1 C6 VC 6 VO
_ C4 V2 _ R
_ _
_
(c) Equivalent circuit during switch-off
FIGURE 3.3
Triple-lift circuit.
Usually R is in kΩ, f in 10 kHz, and C2 in µF, this ripple is smaller than 1%.
3.2.2 Re-Lift Circuit

The re-lift circuit is derived from elementary circuit by adding the parts (L2-
D3-D4-D5-C3-C4). Its circuit diagram and equivalent circuits during switch-
on and -off are shown in Figure 3.2. The voltage across capacitor C1 is charged
to Vin. As described in previous section the voltage V1 across capacitor C2 is
2−k
V1 = V
1 − k in
The voltage across capacitor C3 is charged to V1. The current flowing

through inductor L2 increases with voltage V1 during switch-on period kT
and decreases with voltage –(VO – 2V1) during switch-off period (1 – k)T.
Therefore, the ripple of the inductor current iL2 is

V1 V − 2V1
∆iL 2 = kT = O (1 − k )T (3.7)
L2 L2
2−k 2−k 2
VO = V =( ) Vin (3.8)
1− k 1 1− k
VO 2−k 2
G= =( ) (3.9)
Vin 1− k
Similarly, the following relations are obtained:
Vin I in
∆iL1 = kT I L1 =
L1 2−k
V1 2−k I
∆iL2 = kT I L2 = ( − 1)I O = O
L2 1− k 1− k
Therefore, the variation ratio of current iL1 through inductor L1 is
∆iL1 / 2 k(2 − k )TVin k(1 − k ) 4 R

ξ1 = = = (3.10)
I L1 2L1 I in 2(2 − k ) 3 fL1
The variation ratio of current iL2 through inductor L2 is
∆iL 2 / 2 k(1 − k )TV1 k(1 − k )2 TVO k(1 − k )2 R

ξ2 = = = = (3.11)
I L2 2L2 I O 2(2 − k )L2 I O 2(2 − k ) fL2
and the variation ratio of output voltage vO is
∆vO / 2 1− k
ε= = (3.12)
VO 2 RfC4
3.2.3 Triple-Lift Circuit

Triple-lift circuit is derived from re-lift circuit by double adding the parts
(L2-D3-D4-D5-C3-C4). Its circuit diagram and equivalent circuits during switch-
on and -off are shown in Figure 3.3. The voltage across capacitor C1 is charged
to Vin . As described before the voltage V 1 across capacitor C 2 is
V1 = (2 − k 1 − k )Vin , and voltage V2 across capacitor C4 is V2 = (2 − k 1 − k ) Vin .
2

The voltage across capacitor C5 is charged to V2. The current flowing

through inductor L3 increases with voltage V2 during switch-on period kT
and decreases with voltage –(VO – 2V2) during switch-off (1 – k)T. Therefore,
the ripple of the inductor current iL2 is
V2 V − 2V2
∆iL 3 = kT = O (1 − k )T (3.13)
L3 L3
2−k 2−k 2 2−k 3

VO = V =( ) V1 = ( ) Vin (3.14)
1− k 2 1− k 1− k
VO 2−k 3
G= =( ) (3.15)
Vin 1− k
Analogously,
Vin I in
∆iL1 = kT I L1 =
L1 2−k
V1 2−k
∆iL2 = kT I L2 = I
L2 (1 − k )2 O
V2 IO
∆iL3 = kT I L3 =
L3 1− k
∆iL1 / 2 k(2 − k )TVin k(1 − k )6 R

ξ1 = = = (3.16)
I L1 2L1 I in 2(2 − k ) 5 fL1
∆iL 2 / 2 k(1 − k ) 2 TV1 kT (2 − k ) 4 VO k(2 − k ) 4 R

ξ2 = = = = (3.17)
I L2 2(2 − k )L2 I O 2(1 − k ) 3 L2 I O 2(1 − k ) 3 fL2
∆iL 3 / 2 k(1 − k )TV2 k(1 − k )2 TVO k(1 − k )2 R

ξ3 = = = = (3.18)
I L3 2 L3 I O 2(2 − k )L2 I O 2(2 − k ) fL3
∆vO / 2 1− k
ε= = (3.19)
VO 2 RfC6
3.2.4 Higher Order Lift Circuit

Higher order lift circuit can be designed by just multiple repeating the parts
(L2-D3-D4-D5-C3-C4). For nth order lift circuit, the final output voltage across
capacitor C2n is
2−k n
VO = ( ) Vin
1− k
VO 2−k n
G= =( ) (3.20)
Vin 1− k
The variation ratio of current iLi through inductor Li (i = 1, 2, 3, …n) is
∆iLi / 2 k(1 − k )2( n−i +1) R

ξi = = (3.21)
I Li 2(2 − k )2( n−i )+1 fLi
∆vO / 2 1− k
ε= = (3.22)
VO 2 RfC2 n
3.3 Additional Series

Using two diodes and two capacitors (D11-D12-C11-C12), a circuit called double/
enhance circuit (DEC) can be constructed, which is shown in Figure 3.4, which
is same as the Figure 1.22 but with components renumbered. If the input
voltage is Vin, the output voltage VO can be 2Vin, or other value that is higher
than Vin. The DEC is very versatile to enhance DC/DC converter’s voltage
transfer gain.
All circuits of positive output super-lift Luo-converters-additional series
are derived from the corresponding circuits of the main series by adding a
DEC. The first three stages of this series are shown in Figure 3.5 to Figure 3.7.
Iin
D11 D12
IO
+ +
C11 VC11
– +
Vin R VO
–
S +
– C12 VC12
–
FIGURE 3.4
Double/enhanced circuit (DEC).
For convenience they are called elementary additional circuit, re-lift addi-
tional circuit, and triple-lift additional circuit respectively, and numbered as
n = 1, 2, and 3.
3.3.1 Elementary Additional Circuit

This circuit is derived from elementary circuit by adding a DEC. Its circuit
and switch-on and -off equivalent circuits are shown in Figure 3.5. The
voltage across capacitor C1 is charged to Vin and voltage across capacitor C2
and C11 is charged to V1. The current iL1 flowing through inductor L1 increases
with voltage Vin during switch-on period kT and decreases with voltage
–(VO – 2Vin) during switch-off (1 – k)T. Therefore,
2−k
V1 = V (3.23)
1 − k in
and
k
VL1 = V (3.24)
1 − k in
The output voltage is
3−k
VO = Vin + VL1 + V1 = V (3.25)
1 − k in
VO 3 − k
G= = (3.26)
Vin 1 − k
Iin D1 D2 V1 D11 D12
IO
+ + +
L1 C1 VC1 C11 VC11
– – +
Vin R VO
–
+ +
S
– C2 VC2 C12 VC12
– –
(a) Circuit diagram
Iin
V1
IO
+
+ + + + +
C11 C12
Vin L1 C1 Vin C2 V1 V1 VC12 R VO
– – – – –
–
(b) Equivalent circuit during switching–on
C11
Iin L1 IO
C1 – V1 +
+ – VL1 + V1
+ +
Vin – Vin + + C12 VC12 R VO
C2 V1 – –
– –
(c) Equivalent circuit during switching–off
FIGURE 3.5
Elementary additional (enhanced) circuit.
The following relations are derived:
2IO IO
iin−off = I L1 = iC11−off + iC1−off = iin−on = iL1−on + iC1−on = I L1 +
1− k k
1− k I IO
iC1−on = iC1−off = O iC1−off = iC 2−off =
k k 1− k
k k I 1− k I
iC 2−off = i = i = O iC11−on = i = O
1 − k C 2−on 1 − k C11−on 1 − k k C11−off k
k I k kI
iC11−off = I O + iC12−off = I O + iC12−on = O iC12−off = iC12−on = O
1− k 1− k 1− k 1− k
I In V1
D1 D2 D4 D5 V2 D11 D12
IO
+ + +
+ L1 C1 VC1 L2 C3 VC3 C11 VC11 +
Vin _ _ _
_ R VO
D3 +
S + +
_
C2 V_C2 C4 VC4 C12 VC12
_ _
(a) Circuit diagram

I in
V1 V2 IO
+ + +
+
C2 +
C4 + C12 + +
C1 C3 C11
Vin Vin L2 V2 VC12 VO
L1 V2 _ R
_ V1 V1
_ _
_ _ _ _
C11
I in L1 _ IO
C1 V1 L2 C3 V2 +
_ _ V2
+ + +
Vin V1 +
Vin + +
+ C12
C2 V1 VO
_ _ V2 VC12 R
_ C4 _
FIGURE 3.6
Re-lift additional circuit.
If inductance L1 is large enough, iL1 is nearly equal to its average current

IL1. Therefore,
2IO IO 2 1 1+ k
iin−off = I L1 = iin−on = I L1 + =( + )I = I
1− k k 1 − k k O k(1 − k ) O
Verification:
1+ k 3−k
I in = kiin−on + (1 − k )iin−off = ( + 2) I O = I
1− k 1− k O
Considering
Vin 1 − k 2 VO 1− k 2
=( ) =( ) R

Iin D1 D2 V1 D4 D5 V2 D7 D8 D11 D12
IO
+ + + + +
L1 C1 VC1 L2 C3 VC3 L3 C5 VC5 C11 VC11
– – – – +
Vin R VO
D3 D6 + –
+ + +
C6 VC6
C2 VC2 C4 V S C12 VC12
– C4
–
– – –
(a) Circuit diagram
Iin
V1 V2 V3
IO
+
+ + + + + + + + +
C1 C2 C3 C4 C5 C6 C11 C12
Vin L1 Vin VC2 L2 V1 VC4 L3 V2 VC6 V3 VC12 R VO
– – – – – – – – –
–
C11
Iin L1 C1 V1 L2 C3 V2 L3
– V3 + IO
C5
+ V3
– Vin + – V1 + + + +
+
Vin C2 V1 C4 V2 – V1 + + C12 VC12 R VO
– C6 V3 – –
–
– –
FIGURE 3.7
Triple-lift additional circuit.
The variation of current iL1 is

kTVin
∆iL1 =
L1
∆iL1 / 2 k(1 − k )TVin k(1 − k )2 R

ξ1 = = = (3.27)
I L1 4L1 I O 4(3 − k ) fL1
∆Q I O (1 − k )T 1 − k VO
∆vO = = =
C12 C12 fC12 R
∆vO / 2 1− k
ε= = (3.28)
VO 2 RfC12
3.3.2 Re-Lift Additional Circuit

This circuit is derived from the re-lift circuit by adding a DEC. Its circuit
diagram and switch-on and switch-off equivalent circuits are shown in
Figure 3.6. The voltage across capacitor C1 is charged to Vin. As described in
previous section the voltage across C2 is
2−k
V1 = V
1 − k in
The voltage across capacitor C3 is charged to V1 and voltage across capac-

itor C4 and C11 is charged to V2. The current flowing through inductor L2
increases with voltage V1 during switch-on period kT and decreases with
voltage –(VO – 2V1) during switch-off (1 – k)T. Therefore,
2−k 2−k 2
V2 = V1 = ( ) Vin (3.29)
1− k 1− k
and
k
VL2 = V (3.30)
1− k 1
2−k 3−k
VO = V1 + VL 2 + V2 = V (3.31)
1 − k 1 − k in
VO 2 − k 3 − k
G= = (3.32)
Vin 1 − k 1 − k
Analogously,
Vin 3−k
∆iL1 = kT I L1 = I
L1 (1 − k )2 O
V1 2IO
∆iL2 = kT I L2 =
L2 1− k
∆iL1 / 2 k(1 − k )2 TVin k(1 − k ) 4 R

ξ1 = = = (3.33)
I L1 2(3 − k )L1 I O 2(2 − k )( 3 − k ) fL1
2
and the variation ratio of current iL2 through inductor L2 is
∆iL 2 / 2 k(1 − k )TV1 k(1 − k )2 R

ξ2 = = = (3.34)
I L2 4L2 I O 4(3 − k ) fL2
∆Q I O (1 − k )T 1 − k VO
∆vO = = =
C12 C12 fC12 R
∆vO / 2 1− k
ε= = (3.35)
VO 2 RfC12
3.3.3 Triple-Lift Additional Circuit

This circuit is derived from the triple-lift circuit by adding a DEC. Its circuit
diagram and equivalent circuits during switch-on and -off are shown in
Figure 3.7. The voltage across capacitor C1 is charged to Vin. As described in
previous section the voltage across C2 is
2−k
V1 = V
1 − k in
and voltage across C4 is
2−k 2−k 2
V2 = V1 = ( ) Vin
1− k 1− k
The voltage across capacitor C5 is charged to V2 and voltage across capac-

itor C6 and C11 is charged to V3. The current flowing through inductor L3
increases with voltage V2 during switch-on period kT and decreases with
voltage –(VO – 2V2) during switch-off (1 – k)T. Therefore,
2−k 2−k 2 2−k 3

V3 = V2 = ( ) V1 = ( ) Vin (3.36)
1− k 1− k 1− k
and
k
VL3 = V (3.37)
1− k 2
2−k 2 3−k
VO = V2 + VL 3 + V3 = ( ) V (3.38)
1 − k 1 − k in
VO 2−k 2 3−k
G= =( ) (3.39)
Vin 1− k 1− k
Analogously,
Vin (2 − k )( 3 − k )
∆iL1 = kT I L1 = IO
L1 (1 − k ) 3
V1 3−k
∆iL2 = kT I L2 = I
L2 (1 − k )2 O
V2 2IO
∆iL3 = kT I L3 =
L3 1− k
Considering
Vin 1 − k 2 VO 1− k 2
=( ) =( ) R
∆iL1 / 2 k(1 − k )3 TVin

ξ1 = =
I L1 2(2 − k )(3 − k )L1IO
(3.40)
k(1 − k )3 T (1 − k )3 k(1 − k )6 R
= VO =
2(2 − k )(3 − k )L1IO (2 − k ) ( 3 − k )
2
2(2 − k )3 ( 3 − k )2 fL1

∆iL 2 / 2 k(1 − k )2 TV1

ξ2 = =
IL2 2(3 − k )L2 IO
(3.41)
k(1 − k )2 T (1 − k )2 k(1 − k )4 R
= VO =
2(3 − k )L2 IO (2 − k )(3 − k ) 2(2 − k )(3 − k )2 fL2
∆iL 3 / 2 k(1 − k )TV2 k(1 − k )T 1 − k k(1 − k )2 R

ξ3 = = = VO = (3.42)
I L3 4 L3 I O 4 L3 I O 3 − k 4(3 − k ) fL3
∆Q I O (1 − k )T 1 − k VO
∆vO = = =
C12 C12 fC12 R
∆vO / 2 1− k
ε= = (3.43)
VO 2 RfC12
3.3.4 Higher Order Lift Additional Circuit

The higher order lift additional circuit is derived from the corresponding
circuit of the main series by adding a DEC. For nth order lift additional circuit,
the final output voltage is
2 − k n −1 3 − k
VO = ( ) V
1− k 1 − k in
VO 2 − k n −1 3 − k
G= =( ) (3.44)
Vin 1− k 1− k
Analogously, the variation ratio of current iLi through inductor Li (i = 1, 2, 3,

…n) is
∆iLi / 2 k(1 − k )2( n−i +1) R

ξi = = h ( n− i ) 2 ( n − i ) +1 2 u( n− i −1)
(3.45)
I Li 2[2(2 − k )] (2 − k ) (3 − k ) fLi

where
0 x>0
h( x) =  is the Hong function
1 x≤0
and
1 x≥0
u( x) =  is the unit-step function
0 x<0
∆vO / 2 1− k
ε= = (3.46)
VO 2 RfC12
3.4 Enhanced Series

All circuits of positive output super-lift Luo-converters-enhanced series —
are derived from the corresponding circuits of the main series by adding a
DEC in each stage circuit. The first three stages of this series are shown in
Figures 3.5, 3.8, and 3.9. For convenience they are called elementary
enhanced circuit, re-lift enhanced circuit, and triple-lift enhanced circuit
respectively, and numbered as n = 1, 2 and 3.
3.4.1 Elementary Enhanced Circuit

This circuit is same as the elementary additional circuit shown in Figure 3.5.
3−k
VO = Vin + VL1 + V1 = V (3.25)
1 − k in
VO 3 − k
G= = (3.26)
Vin 1 − k
The variation of current iL1 is

Iin D1 D2 V1 D11 D12 D4 D5 V2 D21 D22
IO
+ + + + +
L1 C1 VC1 C11 VC11 L2 C3 VC3 C21 VC21
– – – – +
Vin R VO
D3 –
+ + + +
C2 VC2 C12 S C4 VC4 C22
– VC12 VC22
– – – –
(a) Circuit diagram

Iin
V1 V2
IO
+
+ + + + + + + + +
C1 C2 C11 C12 C3 C4 C21 C22
Vin L1 Vin V1 V1 VC12 L2 VC12 V2 V2 VC22 R VO
– – – – – – – – –
–
C11 L2 C21
Iin L1 IO
– VL2 +
– V1 + – V2 +
– VL1 + C1 C3
+ V1 V2
+ + +
C12 C22
Vin – Vin + + VC12 – VC12 + + VC22 R VO
C2 V1 – C4 V2 – –
– – –
FIGURE 3.8
Re-lift enhanced circuit.
kTVin
∆iL1 =
L1
∆iL1 / 2 k(1 − k )TVin k(1 − k )2 R

ξ1 = = = (3.27)
I L1 4L1 I O 4(3 − k ) fL1
∆Q I O (1 − k )T 1 − k VO
∆vO = = =
C12 C12 fC12 R

Iin D1 D2 V1 D11 D12 D4 D5 V2 D21 D22 D7 D8 V3 D31 D32
IO
+ + + + + + +
L1 C1 VC1 C11 VC11 L2 C3 VC3 C21 VC21 L3 C5 VC5 C31 VC31
– – – – – – +
Vin R VO
D3 D6 –
+ + + + + +
C2 VC2 C12 C4 VC4 C22 S C6 VC6 C32
– VC12 VC22 VC32
– – – – – –
(a) Circuit diagram

Iin
V1 V2 V3
IO
+
+ C2 + + C12 + + C4 + + C22 + + C6 + + C32 + +
C1 C11 L2 C3 C21 L3 C5 C31
Vin L1 Vin V1 V1 VC12 VC12 V2 V2 VC22 VC22 V3 V3 VC32R VO
– – – – – – – – – – – – –
–
C11 L2 C21 L3 C31

Iin L1 IO
– VL2 + – VL3 +
– V1 + – V2 + – V3 +
– VL1 + C1 C3 C5
+ V1 V2 V3
+ + + +
C12 C22 C32
Vin – Vin + + VC12 – VC12 + + VC22 – VC22 + + VC32 R VO
C2 V1 – C4 V2 – C6 V3 – –
– – – –
FIGURE 3.9
Triple-lift enhanced circuit.
∆vO / 2 1− k
ε= = (3.28)
VO 2 RfC12
3.4.2 Re-Lift Enhanced Circuit

This circuit is derived from the re-lift circuit of the main series by adding
the DEC in each stage circuit. Its circuit diagram and switch-on and switch-
off equivalent circuits are shown in Figure 3.8. As described in the previous
section the voltage across capacitor C12 is charged to
3−k
VC12 = V
1 − k in
The voltage across capacitor C3 is charged to VC12 and voltage across

capacitor C4 and C21 is charged to VC4,
2−k 2−k 3−k

VC 4 = V = V (3.47)
1 − k C12 1 − k 1 − k in
The current flowing through inductor L2 increases with voltage VC12 during
switch-on period kT and decreases with voltage –(VO – VC4 – VC12) during
switch-off (1 – k)T. Therefore,
k 1− k
∆iL 2 = V = (VO − VC 4 − VC12 ) (3.48)
L2 C12 L2
3−k 3−k 2
VO = VC12 = ( ) Vin (3.49)
1− k 1− k
VO 3−k 2
G= =( ) (3.50)
Vin 1− k
Analogously,
Vin 3−k
∆iL1 = kT I L1 = I
L1 (1 − k )2 O
V1 2IO
∆iL2 = kT I L2 =
L2 1− k
∆iL1 / 2 k(1 − k )2 TVin k(1 − k ) 4 R

ξ1 = = = (3.51)
I L1 2(3 − k )L1 I O 2(2 − k )( 3 − k )2 fL1
∆iL 2 / 2 k(1 − k )TV1 k(1 − k )2 R

ξ2 = = = (3.52)
I L2 4L2 I O 4(3 − k ) fL2
∆Q I O (1 − k )T 1 − k VO
∆vO = = =
C22 C22 fC22 R

∆vO / 2 1− k
ε= = (3.53)
VO 2 RfC22
3.4.3 Triple-Lift Enhanced Circuit

This circuit is derived from triple-lift circuit of the main series by adding the
DEC in each stage circuit. Its circuit diagram and equivalent circuits during
switch-on and -off are shown in Figure 3.9. As described in the previous
section the voltage across capacitor C12 is charged to VC12 = (3 − k 1 − k )Vin ,
and the voltage across capacitor C22 is charged to VC 22 = (3 − k 1 − k ) Vin .
2
The voltage across capacitor C5 is charged to VC22 and voltage across

capacitor C6 and C31 is charged to VC6.
2−k 2−k 3−k 2

VC 6 = VC 22 = ( ) Vin (3.54)
1− k 1− k 1− k
The current flowing through inductor L3 increases with voltage VC22 during
switch-on period kT and decreases with voltage –(VO – VC6 – VC22) during
switch-off (1 – k)T.
k 1− k
Therefore, ∆iL 3 = V = (VO − VC 6 − VC 22 ) (3.55)
L3 C 22 L3
3−k 3−k 3
VO = VC 22 = ( ) Vin (3.56)
1− k 1− k
VO 3−k 3
G= =( ) (3.57)
Vin 1− k
Analogously,
Vin (2 − k )( 3 − k )
L1 (1 − k ) 3
V1 3−k
∆iL2 = kT I L2 = I
L2 (1 − k )2 O

V2 2IO
∆iL3 = kT I L3 =
L3 1− k
Considering
Vin 1 − k 2 VO 1− k 2
=( ) =( ) R
∆iL1 / 2 k(1 − k )3 TVin

ξ1 = =
I L1 2(2 − k )(3 − k )L1IO
(3.58)
k(1 − k )3 T (1 − k )3 k(1 − k )6 R
= VO =
2(2 − k )(3 − k )L1IO (2 − k ) ( 3 − k )
2
2(2 − k )3 ( 3 − k )2 fL1
∆iL 2 / 2 k(1 − k )2 TV1

ξ2 = =
IL2 2(3 − k )L2 IO
(3.59)
k(1 − k )2 T (1 − k )2 k(1 − k )4 R
= VO =
2(3 − k )L2 IO (2 − k )(3 − k ) 2(2 − k )(3 − k ) fL2
2
∆iL 3 / 2 k(1 − k )TV2

ξ3 = =
IL3 4L3 IO
(3.60)
k(1 − k )T 1 − k k(1 − k )2 R
= VO =
4L3 IO 3 − k 4(3 − k ) fL3
∆Q I O (1 − k )T 1 − k VO
∆vO = = =
C32 C32 fC32 R
∆vO / 2 1− k
ε= = (3.61)
VO 2 RfC32
3.4.4 Higher Order Lift Enhanced Circuit

The higher order lift enhanced circuit is derived from the corresponding
circuit of the main series by adding the DEC in each stage circuit. For the
nth order lift enhanced circuit, the final output voltage is VO = (3 − k 1 − k ) Vin .
n
VO 3−k n
G= =( ) (3.62)
Vin 1− k

…n) is
∆iLi / 2 k(1 − k )2( n−i +1) R

ξi = = h ( n− i )
(3.63)
I Li 2[2(2 − k )] (2 − k )2( n−i )+1 (3 − k )2 u( n−i −1) fLi
where
0 x>0
1 x≤0
and
1 x≥0
0 x<0
∆vO / 2 1− k
ε= = (3.64)
VO 2 RfCn 2
3.5 Re-Enhanced Series

All circuits of positive output super-lift Luo-converters-re-enhanced series
— are derived from the corresponding circuits of the main series by adding
the DEC twice in each stage circuit.
The first three stages of this series are shown in Figure 3.10 to Figure 3.12.
For convenience they are named elementary re-enhanced circuits, re-lift re-
enhanced circuits, and triple-lift re-enhanced circuits respectively, and num-
bered as n = 1, 2 and 3.
Iin D1 D2 V1 D11 D12 V3 D13 D14

IO
+ + C11 + C13 +
L1 C1 VC1 VC11 VC13
– – – +
Vin R VO
–
+ C12 + C14 +
– C2 VC2 S VC12 VC14
– – –
(a) Circuit diagram

Iin
V1 V2
IO
+
+C2 + +C12 + + C14 + +
L1 C1 C11 C13
Vin Vin V1 V1 V2 V2 VC14 R VO
– – – – – – –
–
C13
IO
Iin C1 C11 – V2 +
L1 V1 V2
+ +
+ – V1 + C14
– Vin + + + VC14 R VO
Vin C2 V1 C12 V2 – –
– –
–
FIGURE 3.10
Elementary re-enhanced circuit.
3.5.1 Elementary Re-Enhanced Circuit

This circuit is derived from the elementary circuit by adding the DEC twice.
Its circuit and switch-on and -off equivalent circuits are shown in Figure 3.10.
4−k
VO = Vin + VL1 + VC12 = V (3.65)
1 − k in

Iin D1 D2 V1 D11 D12 D13 D14 D4 D5 D21 D22 D23 D24

IO
+ + + + + + +
L1 C1 VC1 C11 VC11 C13 VC13 L2 C3 VC3 C21 VC21 C23 VC23
– – – – – – +
Vin R VO
D3 –
+ C12 + + + C22 + C24 +
– C2 VC2 VC12 C14 VC14 C4 VC4 S VC22 VC24
– – – – – –
(a) Circuit diagram

Iin
V1
IO
+
+C2 + + C12 + C13 + C14 + +C4 + + C22 + + C24 + +
C1 C11 C3 C21 C23 R
Vin L1 Vin V1 V1 VC12 VC12 VC14 L2 VC14 VC4 VC4 VC22 VC22 VC24 VO
– – – – – – – – – – – – –
–

Iin L1 C13 L2 C23
+ – – – – C21 –
– + IO
C1 Vin C11 V1 V2+ C3 VC14 VC4
+ + +
+ +
Vin + +
V1 C14 C24 R
VC14 + VC24 VO
+ + +
C2 V1 C12 VC12 – C4 C22 VC22 – –
VC4
– – – – –
FIGURE 3.11
Re-lift re-enhanced circuit.
VO 4 − k
G= = (3.66)
Vin 1 − k
where
2−k
VC 2 = V (3.67)
1 − k in
3−k
VC12 = V (3.68)
1 − k in
and
k
VL1 = V (3.69)
1 − k in

Iin
D1 D2 V1 D11 D12 D13 D14 D4 D5 D21 D22 D23 D24 D7 D8 D31 D32 D33 D34
IO
+ + + + + + + + + +
L1 C1 VC1 C11 VC11 C13 VC13 L2 C3 VC3 C21 VC21 C23 VC23 L3 C5 VC5 C31 VC31 C33 VC33
– – – – – – – – – +
Vin R VO
D3 D6 –
+ C12 + + + C22 + + + C32 + C34 +
C2 VC2 VC12 C14 VC14 C4 VC4 VC22 C24 VC24 C6 VC6 S VC32 VC34
–
– – c – – – – – –
(a) Circuit diagram

Iin
V1
IO
+
+ + + + + + + + + + + + + + + + + + +
C1 C2 C11 C12 C13 C14 C3 C4 C21 C22 C23 C24 C5 C6 C31 C32 C33 C34 R
L2 L3
Vin L1 Vin V1 V1 VC14 VC14 VC4 VC4 VC22 VC22 VC24 VC24 VC6 VC6 VC32 VC34 VO
VC12 VC12
VC32
– – – – – – – – – – – – – – – –
– –
–
–
Iin L1 C13 L2 C23 L3 C33
– – – –
+ – – – – – IO
C1 Vin C11 V1 + C21 + C31 +
VC12 VC22 VC24 VC6 VC32
C3 VC14 VC4 C5
+ + + +
+ +
+ + + +
Vin V1 C14 C24 C34 R
VC14 VC24 VC34 VO
+ + + + + +
C2 C12 VC12 C4 VC4 C22 VC22 C6 VC6 C32 VC32
V1 – – – –
– – – –
– – –

FIGURE 3.12
Triple-lift re-enhanced circuit.

The following relations are obtained:
2IO IO
1− k k
1− k I IO
k k 1− k
k k I 1− k I
iC 2−off = iC 2−on = iC11−on = O iC11−on = iC11−off = O
1− k 1− k 1− k k k
k I k kI
1− k 1− k 1− k 1− k
If inductance L1 is large enough, iL1 is nearly equal to its average current

IL1. Therefore,
2IO IO 2 1 1+ k
iin−off = I L1 = iin−on = I L1 + =( + )I = I
1− k k 1 − k k O k(1 − k ) O
Verification:
1+ k 3−k
1− k 1− k O
Considering
Vin 1 − k 2 VO 1− k 2
=( ) =( ) R
the variation of current iL1 is
kTVin
∆iL1 =
L1
∆iL1 / 2 k(1 − k )TVin k(1 − k )2 R

ξ1 = = = (3.70)
I L1 4L1 I O 4(3 − k ) fL1
∆iL 2 / 2 k(1 − k )TV1 k(1 − k )2 R

ξ2 = = = (3.76)
I L2 4L2 I O 4(3 − k ) fL2
∆Q I O (1 − k )T 1 − k VO
∆vO = = =
C24 C24 fC24 R
∆vO / 2 1− k
ε= = (3.77)
VO 2 RfC24
3.5.3 Triple-Lift Re-Enhanced Circuit

This circuit is derived from triple-lift circuit of the main series by adding the
DEC twice in each stage circuit. Its circuit and switch-on and -off equivalent
circuits are shown in Figure 3.12. The voltage across capacitor C14 is
4−k
VC14 = V (3.78)
1 − k in
The voltage across capacitor C24 is
4−k 2
VC 24 = ( ) Vin (3.79)
1− k
By the same analysis
4−k 4−k 3
VO = VC 24 = ( ) Vin (3.80)
1− k 1− k
VO 4−k 3
G= =( ) (3.81)
Vin 1− k
Analogously,

Vin (2 − k )( 3 − k )
L1 (1 − k ) 3
V1 3−k
∆iL2 = kT I L2 = I
L2 (1 − k )2 O
V2 2IO
∆iL3 = kT I L3 =
L3 1− k
Considering
Vin 1 − k 2 VO 1− k 2
=( ) =( ) R
∆iL1 / 2 k(1 − k )3 TVin

ξ1 = =
I L1 2(2 − k )(3 − k )L1IO
(3.82)
k(1 − k )3 T (1 − k )3 k(1 − k )6 R
= VO =
2(2 − k )(3 − k )L1IO (2 − k ) ( 3 − k )
2
2(2 − k )3 ( 3 − k )2 fL1
∆iL 2 / 2 k(1 − k )2 TV1

ξ2 = =
IL2 2(3 − k )L2 IO
(3.83)
k(1 − k )2 T (1 − k )2 k(1 − k )4 R
= VO =
2(3 − k )L2 IO (2 − k )(3 − k ) 2(2 − k )(3 − k )2 fL2
∆iL 3 / 2 k(1 − k )TV2 k(1 − k )T 1 − k k(1 − k )2 R

ξ3 = = = VO = (3.84)
I L3 4 L3 I O 4 L3 I O 3 − k 4(3 − k ) fL3
∆Q I O (1 − k )T 1 − k VO
∆vO = = =
C34 C34 fC34 R

∆vO / 2 1− k
ε= = (3.85)
VO 2 RfC34
3.5.4 Higher Order Lift Re-Enhanced Circuit

Higher order lift additional circuits are derived from the corresponding
circuit of the main series by adding DEC twice in each stage circuit. For the
nth order lift additional circuit, the final output voltage is
4−k n
VO = ( ) Vin
1− k
VO 4−k n
G= =( ) (3.86)
Vin 1− k

…n) is
∆iLi / 2 k(1 − k )2( n−i +1) R

ξi = = h ( n− i ) 2 ( n − i ) +1 2 u( n− i −1)
(3.87)
I Li 2[2(2 − k )] (2 − k ) (3 − k ) fLi
where
0 x>0
1 x≤0
and
1 x≥0
0 x<0
∆vO / 2 1− k
ε= = (3.88)
VO 2 RfCn 4

1 2.. j
Iin D1 D2 V1 D11 D12 D1(2j–1) D1(2j)

IO
+ + + +
L1 C1 VC1 C11 VC11 C1(2j–1) VC1(2j–1)
– – – +
Vin R VO
–
+ + +
S
– C2 VC2 C12 VC12 C12j VC12j
– – –
(a) Circuit diagram

Iin
V1
IO
+
+ C2 + + + C12j + +
C1 C11 C1(2j–1)
Vin L1 Vin V1 V1 VC1(2j–1) VC12jR VO
– – – – – –
–
C11 C1(2j–1)
Iin L1 IO
– V1 + – VC1(2j–1) +
+ – VL1 + C1
V1
+ C12j + +
C12
Vin – Vin + + VC12 VC12jR VO
C2 V1 – – –
– –
FIGURE 3.13
Elementary multiple-enhanced circuit.
3.6 Multiple-Enhanced Series

All circuits of positive output super-lift Luo-converters — multiple-
enhanced series — are derived from the corresponding circuits of the main
series by adding the DEC multiple (j) times in each stage circuit. The first
three stages of this series are shown in Figure 3.13 through Figure 3.15. For
convenience they are called elementary multiple-enhanced circuits, re-lift
multiple-enhanced circuits, and triple-lift multiple-enhanced circuits respec-
tively, and numbered as n = 1, 2, and 3.
Iin D1 D2 V1 D11 D12 D1(2j–1) D1(2j) D4 D5 D21 D22 D2(2j–1) D2(2j)
IO
+ + + + + + +
L1 C1 VC1 C11 VC11 C1(2j–1) VC1(2j–1) L2 C3 VC3 C21 VC21 C2(2j–1) VC2(2j–1)
– – – – – – +
Vin R VO
D3 D6 –
+ + + + + +
C2 VC2 C12 C12j S C4 VC4 C22 C22j
– VC12 VC12j VC22 VC22j
– – – – – –
(a) Circuit diagram

Iin
V1
IO
+
+ C2 + + C1(2j–1) + C12j + + C4 + + C2(2j–1) + C22j + +
C1 C11 C3 C21
Vin L1 Vin V1 V1 VC1(2j–1) VC12jL2 VC3 VC4 VC21 VC2(2j–1) VC22jR VO
– – – – – – – – – – –
–
Iin L1 C11 C1(2j–1) L2 C21 C2(2j–1)

IO
+ – VL1 + – VL2 +
– V1 + VC1(2j–1) + – –VC21+ – VC2(2j–1) +
C1 C3
V1
+ + + + +
Vin C12 C12j C22 C22j
– Vin + + VC12 VC12j – VC3 + + VC22 VC22jR VO
C2 V1 – – C4 VC4 – – –
– – –

FIGURE 3.14
Re-lift multiple-enhanced circuit.

Iin
D1 D2 V1 D11 D12 D1(2j–1) D1(2j) D4 D5 D21 D22 D2(2j–1) D2(2j) D7 D8 D31 D32 D3(2j–1) D3(2j)
IO
+ + + + + + + + + +
L1 C1 VC1 C11 VC11 C1(2j–1) VC1(2j–1) L2 C3 VC3 C21 VC21 C2(2j–1) VC2(2j–1) L3 C5 VC5 C31 VC31 C3(2j–1) VC3(2j–1)
– – – – – – – – – +
Vin R VO
D3 D6 –
+ + + + + + + + +
S
C2 VC2 C12 VC12 C12j VC12j C4 VC4 C22 VC22 C22j VC22j C6 VC6 C32 VC32 C32j VC32j
–
– – – – – – – – –
Iin (a) Circuit diagram

V1
IO
+
+ + + + C12j + + + + + + + + + + + +
C1 C2 C11 C1(2j–1) C3 C4 C21 C2(2j–1) C22j C5 C6 C31 C3(2j–1) C32j
Vin L1 Vin V1 V1 VC1(2j–1) VC12j L2 VC3 VC4 VC21 VC2(2j–1) VC22jL3 VC5 VC6 VC31 VC3(2j–1) VC32j R VO
– – – – – – – – – – – – – – – –
–
Iin L1 C11 C1(2j–1) L2 C21 C2(2j–1) L3 C31 C3(2j–1)
IO
+ – VL1 + – VL2 + VL3 +
– – V1 + – VC21 + – VC31 +
–VC1(2j–1) + – VC2(2j–1) + – VC3(2j–1) +
C1 Vin – –
+ C3 VC3 C5 VC5
V1 + + + + + + + + +
Vin C12 C12j C22 C22j C32 C32j
VC12 VC12j VC22 VC22j VC32 VC32j R VO
+ + +
C2 V1 C4 VC4 C6 VC6
– – – – – – –
– – –
–

FIGURE 3.15
Triple-lift multiple-enhanced circuit.

3.6.1 Elementary Multiple-Enhanced Circuit

This circuit is derived from the elementary circuit of the main series by
adding the DEC multiple (j) times. Its circuit and switch-on and -off equiv-
alent circuits are shown in Figure 3.13. The output voltage is
j+2−k
VO = Vin (3.89)
1− k
VO j + 2 − k
G= = (3.90)
Vin 1− k
Following relations are obtained:
2IO IO
1− k k
1− k I IO
k k 1− k
k k I 1− k I
iC 2−off = iC 2−on = iC11−on = O iC11−on = iC11−off = O
1− k 1− k 1− k k k
k I k kI
1− k 1− k 1− k 1− k
If inductance L1 is large enough, iL1 is nearly equal to its average current IL1.
Therefore,
2IO IO 2 1 1+ k
iin−off = I L1 = iin−on = I L1 + =( + )I O = I
1− k k 1− k k k(1 − k ) O
Verification:
1+ k 3−k
1− k 1− k O
Considering
Vin 1 − k 2 VO 1− k 2
=( ) =( ) R

the variation of current iL1 is
kTVin
∆iL1 =
L1
∆iL1 / 2 k(1 − k )TVin k(1 − k )2 R

ξ1 = = = (3.91)
I L1 4L1 I O 4(3 − k ) fL1
∆Q I O (1 − k )T 1 − k VO
∆vO = = =
C12 j C12 j fC12 j R
∆vO / 2 1− k
ε= = (3.92)
VO 2 RfC12 j
3.6.2 Re-Lift Multiple-Enhanced Circuit

This circuit is derived from the re-lift circuit of the main series by adding
the DEC multiple (j) times in each stage circuit. Its circuit diagram and
switch-on and switch-off equivalent circuits are shown in Figure 3.14. The
voltage across capacitor C12j is
j+2−k
VC12 j = Vin (3.93)
1− k
The output voltage across capacitor C22j is
j+2−k 2
VO = VC 22 j = ( ) Vin (3.94)
1− k
VO j+2−k 2
G= =( ) (3.95)
Vin 1− k
Analogously,

Vin 3−k
∆iL1 = kT I L1 = I
L1 (1 − k )2 O
V1 2IO
∆iL2 = kT I L2 =
L2 1− k
∆iL1 / 2 k(1 − k )2 TVin k(1 − k ) 4 R

ξ1 = = = (3.96)
I L1 2(3 − k )L1 I O 2(2 − k )( 3 − k ) fL1
2
∆iL 2 / 2 k(1 − k )TV1 k(1 − k )2 R

ξ2 = = = (3.97)
I L2 4L2 I O 4(3 − k ) fL2
∆Q I O (1 − k )T 1 − k VO
∆vO = = =
∆vO / 2 1− k
ε= = (3.98)
VO 2 RfC22 j
3.6.3 Triple-Lift Multiple-Enhanced Circuit

This circuit is derived from the triple-lift circuit of the main series by adding
the DEC multiple (j) times in each stage circuit. Its circuit and switch-on and
-off equivalent circuits are shown in Figure 3.15. The voltage across capacitor
C12j is
j+2−k
VC12 j = Vin (3.99)
1− k
The voltage across capacitor C22j is
j+2−k 2
VC 22 j = ( ) Vin (3.100)
1− k
Same analysis,
j+2−k j+2−k 3
VO = VC 22 j = ( ) Vin (3.101)
1− k 1− k
VO j+2−k 3
G= =( ) (3.102)
Vin 1− k
Analogously,
Vin (2 − k )( 3 − k )
L1 (1 − k ) 3
V1 3−k
∆iL2 = kT I L2 = I
L2 (1 − k )2 O
V2 2IO
∆iL3 = kT I L3 =
L3 1− k
Considering
Vin 1 − k 2 VO 1− k 2
=( ) =( ) R
∆iL1 / 2 k(1 − k )3 TVin

ξ1 = =
I L1 2(2 − k )(3 − k )L1IO
(3.103)
k(1 − k )3 T (1 − k )3 k(1 − k )6 R
= VO =
2(2 − k )(3 − k )L1IO (2 − k ) ( 3 − k )
2
2(2 − k )3 ( 3 − k )2 fL1
∆iL 2 / 2 k(1 − k )2 TV1

ξ2 = =
IL2 2(3 − k )L2 IO
(3.104)
k(1 − k )2 T (1 − k )2 k(1 − k )4 R
= VO =
2(3 − k )L2 IO (2 − k )(3 − k ) 2(2 − k )(3 − k ) fL2
2

∆iL 3 / 2 k(1 − k )TV2 k(1 − k )T 1 − k k(1 − k )2 R

ξ3 = = = VO = (3.105)
I L3 4 L3 I O 4 L3 I O 3 − k 4(3 − k ) fL3
∆Q I O (1 − k )T 1 − k VO
∆vO = = =
∆vO / 2 1− k
ε= = (3.106)
VO 2 RfC32 j
3.6.4 Higher Order Lift Multiple-Enhanced Circuit

Higher order lift multiple-enhanced circuits can be derived from the corre-
sponding circuit of the main series converters by adding the DEC multiple
(j) times in each stage circuit. For the nth order lift additional circuit, the final
output voltage is
j+2−k n
VO = ( ) Vin
1− k
VO j+2−k n
G= =( ) (3.107)
Vin 1− k

…n) is
∆iLi / 2 k(1 − k )2( n−i +1) R

ξi = = h ( n− i )
(3.108)
I Li 2[2(2 − k )] (2 − k )2( n−i )+1 (3 − k )2 u( n−i −1) fLi
where
0 x>0
1 x≤0

and
1 x≥0
0 x<0
The variation ratio of output voltage vO is
∆vO / 2 1− k
ε= = (3.109)
VO 2 RfCn 2 j
3.7 Summary of Positive Output Super-Lift Luo-Converters

All circuits of positive output super-lift Luo-converters can be shown in
Figure 3.16 as the family tree. From the analysis in previous sections, the
common formula to calculate the output voltage is presented:
 2−k n
 ( ) Vin main _ series
1− k
 2 − k n −1 3 − k
( ) ( )V additional _ series
 1− k 1 − k in
 3−k n
VO =  ( ) Vin enhanced _ series (3.110)
 1− k
 4−k n
( ) Vin re - enhanced _ series
 1− k
 j+2−k n
 ( 1 − k ) Vin multiple - enhanced _ series
 2−k n
 ( ) main _ series
1− k
 2 − k n −1 3 − k
( ) ( ) additional _ series
 1− k 1− k
V  3−k n
G= O = ( ) enhanced _ series (3.111)
Vin  1− k
 4−k n
( ) re - enhanced _ series
 1− k
 j+2−k n
 ( 1 − k ) multiple - enhanced _ series

Main Additional Enhanced Reenhanced Multiple-Enhanced

Series Series Series Series Series
Quintuple-Lift Quadruple-Lift Quintuple-Lift Quintuple-Lift Quintuple-Lift Multiple-

Circuit Additional Circuit Enhanced Circuit Reenhanced Circuit Enhanced Circuit
Quintuple-Lift Quadruple-Lift Quintuple-Lift Quadruple-Lift Quadruple-Lift Multiple-

Triple-Lift Triple-Lift Triple-Lift Triple-Lift Triple-Lift Multiple-

Relift Additional Relift Additional Relift Relift Multiple-

Relift Circuit
Circuit Circuit Reenhanced Circuit Enhanced Circuit
Elementary Additional/Enhanced Elementary Elementary Multiple-

Circuit Reenhanced Circuit Enhanced Circuit
Elementary Positive Output Super-Lift Luo-Converter
FIGURE 3.16
The family of positive output super-lift Luo-converters.
In order to show the advantages of super-lift Luo-converters, their voltage

transfer gains can be compared to that of a buck converter,
VO
G= =k
Vin
forward converter,
VO
G= = kN N is the transformer turns ratio
Vin
Cúk-converter,
VO k
G= =
Vin 1 − k
fly-back converter,

TABLE 3.1
Voltage Transfer Gains of Converters in the Condition k = 0.2
Stage No. (n) 1 2 3 4 5 n
Buck converter 0.2
Forward converter 0.2 N (N is the transformer turns ratio)
Cúk-converter 0.25
Fly-back converter 0.25 N (N is the transformer turns ratio)
Boost converter 1.25
Positive output Luo-converters 1.25 2.5 3.75 5 6.25 1.25n
Positive output super-lift 2.25 5.06 11.39 25.63 57.67 2.25n
Luo-converters — main series
Positive output super-lift 3.5 7.88 17.72 39.87 89.7 3.5*2.25(n-1)
Luo-converters — additional series
Positive output super-lift 3.5 12.25 42.88 150 525 3.5n
Luo-converters — enhanced series
Positive output super-lift 4.75 22.56 107.2 509 2418 4.75n
Luo-converters — re-enhanced series
Positive output super-lift 7.25 52.56 381 2762 20,030 7.25n
Luo-converters — multiple (j = 4)-
enhanced series
VO k
G= = N N is the transformer turn ratio
Vin 1 − k
boost converter,
VO 1
G= =
Vin 1 − k
and positive output Luo-converters.
VO n
G= = (3.112)
Vin 1 − k
If we assume that the conduction duty k is 0.2, the output voltage transfer
gains are listed in Table 3.1.
If the conduction duty k is 0.5, the output voltage transfer gains are listed
in Table 3.2.
If the conduction duty k is 0.8, the output voltage transfer gains are listed
in Table 3.3.

TABLE 3.2
Stage No. (n) 1 2 3 4 5 n
Buck converter 0.5
Cúk-converter 1
Fly-back converter N (N is the transformer turns ratio)
Boost converter 2
Positive output Luo-converters 2 4 6 8 10 2n
Positive output super-lift 3 9 27 81 243 3n
Positive output super-lift 5 15 45 135 405 5*3(n-1)
Positive output super-lift 7 49 343 2401 16,807 7n
Positive output super-lift 11 121 1331 14,641 16*104 11n
enhanced series
TABLE 3.3
Stage No. (n) 1 2 3 4 5 n
Buck converter 0.8
Cúk-converter 4
Fly-back converter 4 N (N is the transformer turns ratio)
Boost converter 5
Positive output Luo-converters 5 10 15 20 25 5n
Positive output super-lift 11 66 396 2376 14,256 11*6(n-1)
Positive output super-lift 26 676 17,576 46*104 12*106 26n
enhanced series

1.0A
(9.988m, 618m)
0.5A (9.988m, 218m)

(9.988m, 111m)
+ + +
+
0A
I(L1) I(L2) + I(L3)
1.0KV
(9.988m, 659)
0.5KV (9.988m, 194)

(9.988m, 66)
SEL>>
0V
9.980ms 9.984ms 9.988ms 9.992ms 9.996ms 10.000ms
V(R:2) V(D2:2) V(D5:2)
Time
FIGURE 3.17
The simulation results of triple-lift circuit at condition k = 0.5 and f = 100 kHz.
3.8 Simulation Results

To verify the design and calculation results, the PSpice simulation package
was applied to these converters. Choosing Vin = 20 V, L1 = L2 = L3 = 10 mH,
all C1 to C8 = 2 µF, and R = 30 kΩ, and using k = 0.5 and f = 100 kHz.
3.8.1 Simulation Results of a Triple-Lift Circuit

The voltage values V1, V2 and VO of a triple-lift circuit are 66 V, 194 V, and
659 V respectively and inductor current waveforms are iL1 (its average value
IL1 = 618 mA), iL2, and iL3. The simulation results are shown in Figure 3.17.
The voltage values are matched to the calculated results.
3.8.2 Simulation Results of a Triple-Lift Additional Circuit

The voltage values V1, V2, V3, and VO of the triple-lift additional circuit are
57 V, 165 V, 538 V, and 910 V respectively and current waveforms are iL1 (its
average value IL1 = 1.8 A), iL2, and iL3. The simulation results are shown in
Figure 3.18. The voltage values are matched to the calculated results.

2.0A
(19.988m, 1.8)
(19.988m, 623m)
1.0A (19.988m, 248m)
0A
I(L1) I(L2) I(L3)
1.0KV
(19.988m, 910)
(19.988m, 538)
0.5KV
(19.988m, 165)
(19.988m, 57)
SEL>>
0V
19.980ms 19.984ms 19.988ms 19.992ms 19.996ms 20.000ms
V(D8:2) V(R:2) V(D2:2) V(D5:2)
Time
FIGURE 3.18
Simulation results of triple-lift additional circuit at condition k = 0.5 and f = 100 kHz.
3.9 Experimental Results

A test rig was constructed to verify the design and calculation results, and
compare with PSpice simulation results. The testing conditions were the
same: Vin = 20 V, L1 = L2 = L3 = 10 mH, all C1 to C8 = 2 µF and R = 30 kΩ,
and using k = 0.5 and f = 100 kHz. The component of the switch is a MOSFET
device IRF950 with the rates 950 V/5 A/2 MHz. The values of the output
voltage and first inductor current are measured in the following converters.
3.9.1 Experimental Results of a Triple-Lift Circuit

After careful measurement, the current value of IL1 = 0.62 A (shown in
channel 1 with 1 A/Div) and voltage value of VO = 660 V (shown in channel
2 with 200 V/Div). The experimental results (current and voltage values)
are shown in Figure 3.19, that are identically matched to the calculated and
simulation results, which are IL1 = 0.618 A and VO = 659 V shown in
Figure 3.17.
3.9.2 Experimental Results of a Triple-Lift Additional Circuit

The experimental results of the current value of IL1 = 1.8 A (shown in channel
1 with 1 A/Div) and voltage value of VO = 910 V (shown in channel 2 with

FIGURE 3.19
The experimental results of triple-lift circuit at condition k = 0.5 and f = 100 kHz.
TABLE 3.4
Comparison of Simulation and Experimental Results of a Triple-Lift Circuit
Stage No. (n) IL1 (A) Iin (A) Vin (V) Pin (W) VO (V) PO (W) η (%)
Simulation results 0.618 0.927 20 18.54 659 14.47 78
Experimental results 0.62 0.93 20 18.6 660 14.52 78
TABLE 3.5
Comparison of Simulation and Experimental Results
of a Triple-Lift Additional Circuit
Stage No. (n) IL1 (A) Iin (A) Vin (V) Pin (W) VO (V) PO (W) η (%)
Simulation results 1.8 2.7 20 54 910 27.6 51
Experimental results 1.8 2.7 20 54 910 27.6 51
200 V/Div) are shown in Figure 3.20 that are identically matched to the
calculated and simulation results, which are IL1 = 1.8 A and VO = 910 V shown
in Figure 3.18.
3.9.3 Efficiency Comparison of Simulation and Experimental Results

These circuits enhanced the voltage transfer gain successfully, but efficiency,
particularly, the efficiencies of the tested circuits is 51 to 78%, which is good
for high voltage output equipment. Comparison of the simulation and exper-
imental results, which are listed in the Tables 3.4 and 3.5, demonstrates that
all results are well identified each other.
FIGURE 3.20
Experimental results of triple-lift additional circuit at condition k = 0.5 and f = 100 kHz.
Usually, there is high inrush current during the initial power-on. There-
fore, the voltage across capacitors is quickly changed to certain values. The
transient process is very quick in only few milliseconds.
Bibliography
Kassakian, J.G., Wolf, H-C., Miller, J.M., and Hurton, C.J., Automotive electrical
systems, circa 2005, IEEE Spectrum, 8, 22, 1996.
Lander, C.W., Power Electronics, McGraw-Hill, London, 1993.
Luo, F.L., Luo-converters, a new series of positive-to-positive DC-DC step-up con-
verters, Power Supply Technologies and Applications, Xi’an, China, 1, 30, 1998.
Luo, F.L., Positive output Luo-converters, the advanced voltage lift technique, Elec-
trical Drives, Tianjin, China, 2, 47, 1999.
Luo, F.L. and Ye, H., Positive output super-lift Luo-converters, in Proceedings of IEEE-
PESC’2002, Cairns, Australia, 2002, p. 425.
Luo, F.L. and Ye, H., Positive output super-lift converters, IEEE Transactions on Power
Electronics, 18, 105, 2003.
Pelley, B.R., Tryristor Phase Controlled Converters and Cycloconverters, John Wiley, New
York, 1971.
Pressman, A.I., Switching Power Supply Design, 2nd ed., McGraw-Hill, New York, 1998.
Rashid, M.H., Power Electronics, 2nd ed., Prentice Hall of India Pvt. Ltd., New Delhi,
1995.
Trzynadlowski, A.M., Introduction to Modern Power Electronics, Wiley Interscience,
New York, 1998.
Ye, H., Luo, F.L., and Ye, Z.Z., Widely adjustable high-efficiency high voltage regu-
lated power supply, Power Supply Technologies and Applications, Xi’an, China, 1,
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fm Page 215 Thursday, August 7, 2003 10:10 PM

In order to concentrate the voltage enlargement, assume the converters

© 2003 by CRC Press LLC

3.2 Main Series

3.2.1 Elementary Circuit

The voltage transfer gain is

iin−off = iL1−off = iC1−off iin−on = iL1−on + iC1−on kTiC1−on = (1 − k )TiC1−off

© 2003 by CRC Press LLC

(a) Circuit diagram

(b) Equivalent circuit during switching-on

(c) Equivalent circuit during switching-off

and average input current

I in = kiin−on + (1 − k )iin−off = I L1 + (1 − k )I L1 = (2 − k )I L1 (3.4)

© 2003 by CRC Press LLC

(a) Circuit diagram

(b) Equivalent circuit during switching-on

(c) Equivalent circuit during switching-off

the variation ratio of current iL1 through inductor L1 is

∆iL1 / 2 k(2 − k )TVin k(1 − k )2 R

Therefore, the variation ratio of output voltage vO is

(a) Circuit diagram

(b) Equivalent circuit during switch-on

(c) Equivalent circuit during switch-off

3.2.2 Re-Lift Circuit

The voltage across capacitor C3 is charged to V1. The current flowing

© 2003 by CRC Press LLC

The voltage transfer gain is

Similarly, the following relations are obtained:

Therefore, the variation ratio of current iL1 through inductor L1 is

∆iL1 / 2 k(2 − k )TVin k(1 − k ) 4 R

The variation ratio of current iL2 through inductor L2 is

∆iL 2 / 2 k(1 − k )TV1 k(1 − k )2 TVO k(1 − k )2 R

and the variation ratio of output voltage vO is

3.2.3 Triple-Lift Circuit

© 2003 by CRC Press LLC

The voltage across capacitor C5 is charged to V2. The current flowing

2−k 2−k 2 2−k 3

The voltage transfer gain is

Therefore, the variation ratio of current iL1 through inductor L1 is

∆iL1 / 2 k(2 − k )TVin k(1 − k )6 R

The variation ratio of current iL2 through inductor L2 is

∆iL 2 / 2 k(1 − k ) 2 TV1 kT (2 − k ) 4 VO k(2 − k ) 4 R

The variation ratio of current iL3 through inductor L3 is

∆iL 3 / 2 k(1 − k )TV2 k(1 − k )2 TVO k(1 − k )2 R

and the variation ratio of output voltage vO is

3.2.4 Higher Order Lift Circuit

The voltage transfer gain is

The variation ratio of current iLi through inductor Li (i = 1, 2, 3, …n) is

∆iLi / 2 k(1 − k )2( n−i +1) R

and the variation ratio of output voltage vO is

3.3 Additional Series

3.3.1 Elementary Additional Circuit

The output voltage is

The voltage transfer gain is

Iin D1 D2 V1 D11 D12

(a) Circuit diagram

(b) Equivalent circuit during switching–on

(c) Equivalent circuit during switching–off

The following relations are derived:

(a) Circuit diagram

(b) Equivalent circuit during switching–on

(c) Equivalent circuit during switching–off