https: /t.me/abcdelectrical KOeATAYX Digits Hectronis and Meroprocsons Number Systems and Boolean Algebra '* Decimal : Radix = 10; Symbols = (0, 1,2, 3, 9) * Binary : Radis 2; Symbols = (0, 1) ‘© Hexadecimal : Radix = 16; Symbols = (0, 1, 2.... © Octal : Radix = 8; Symbols = (0, 1,2, .. a 1 For radix N, following digits are possible (1,2, + N-1) ‘© Toconvert a number from radix ‘x’ to bare 10 or decimal. £9, (136) > (2)yq = 12 +3.x+6x° =(2+3+6) Complimentary Number Representation A-B=A+(-8) =A+ (compliment of +B) Fora base —rsystem ( 1)'4 compliment +s compliment =r" =N Where r = base N= given number feger part of N m= no. of digit in decimal part of NV 9, For (37867)}9 N=37867 ; m=3;n=2; r= 10 4 www.krealryx.com 3 eoGgon 3} wh | J JIdddde {| bddty ee PS*//t .me/abcdelectrical Vd Notes a C exp rasswvery > dees 3 Boolean Algebra ge A Bunche d lowe ; baa togell o Vdd d + Comalimen 0-1 or Cestean | 190 Used bo eotpress all Represented as A> A peseeble douth tee, by. And (RSA Ap members Combcre ¢ " the, Set intoe © ANDifunction ap eneprainan. VETTT ITT 7 00-0 AA=A : 120 AI=A z 10=0 AO=0 9 Lt 11-0 AR=0 aay do -Y 1 * OR Function {auo, eT) | AGAZA Ls ue LISanny, as0Ry — A+O=A yj" tet that 3 Laws of Boolean Algebra Rlagram ¢ Venn, Di agrann aren shaded i peane taee FR OS 1) Commutative Law OR=A+B=B+A 2) Associative Law OR=(A+B)+C=A+(B+C) AND=(AB)C=A(BC) SECU = \e www.kreatryx.com 4 osohttps: //t .me/abedelectrical [Knotes rnd Digital tectronies and Nicroprocesns 3) Consensus Law eel Ato=A , AFI ; = +BC= AB+AC A050, atzA istibutve Law = A(B+C)=AB HAC hae 2 ae ail ae AR=A, KAAZO 5 eA pArABHA Dual : Conver all 17 e130 051 A+ BO'=(AH8)AHQ) ArB)CATC) 5) De=Morgaa's (aw + NOR opeatenizame stubbied AND | Ee ge SAB TAC A+B+C... cr. ABIACHLA +¢) GiB) + NAND operation is same as bubbled OR ee a-@ =A +B) Wao b eC AsBsC... 6) Testor an AtB “AA-B) AOB= CAB CAE) A@B YS (MAB) CH AB )=HPHE) AB+AC=(A+C)(A¥B) Operator precedence 1)Parenthesis 2M Lonny 4)OR . Minterms, Maxterms & Properties “Minterm :Itis a standard product term ie. a product term which contains all variables of a given function either in normal form or compliment form. ‘Maxterm:: tis standard sum term ie, a sum term which contains all the variables of the function either in normal or compliment form. eoeoo www.krealryx.comz@ Ls ny La a me SNetps: //t.me/abedelectrical : [Krores aS eens it evi and Moron € FABO et AEC=m, (0.0.0) Aes es Rac=m, (0,0,1) Re BeC=M, ys AgC=m, (1.1.1) AsB+C=My Tf Properties ey » 1D tk 5M = 1) n=variabe function {2M interns 2" maxterni mi fp H - fel ow It Fi

canonical SOP form 2 = M(5,7)-> canonical POS form Karnaugh Map 3=vatiable K~ may J) Octant -> group of 8 minterms Quad — group of 4 min terms Pair > group of 2 min terms ' allel) 4=variable k~ map All comers of k~ map SH (0,2, 8,10) > Quad af} {tf F=AC+AD+80+8C+ ABC www.kreairyx.com eoGcoDn\ ps: //t.me/abcdelectrical IK kpeaTevx Dit eeonies and fa, Ty @ |x fe @ a Eg. F(A.B,C) = =M(0,1,2,3.4.7) F=A(8+C)(8+C) Implicant : itis the set of alladjacent min terms Udddd da Eg. Pair, quadjoctants Prime implicant’ ts an implicant which is not a subset of another implicant. yl Essential Pl (EPI): Its a prime implicant which contains at least one min terms which isnot covered by other prime implicant. ‘ee0% punine’ ¢ 2 Ise Ee 1)PI,Non PL 2)P1, EPI 3) Pl, EPI 4)PI, EPI 5) PI, EPI 5 =|] | Don't care condition In a digital system, for anén - occurring input, the output can be taken as either one or zero during simplification & itis called don’t care condition. Uuya Eg. X(A.B,C.D) = Ym(0,1) +d(10,11,12,13,14,15) ; = at winter 1, : is ann a aL x ee Sso Ser tesm I 4 s|_ of L x= ABC 2 a z) * x iz 7 www.krealryx.com 8 ooohttps: //t me/abcdelectrical Ila KECATENE, Dita ecwonies apd Micronrogesioe “y COINCASINEE OP Logic Gates a argu | igh won 1) Equivalence Gate = x-NOR Gate U iY ¥ ALBIF 0]0{0 * ofa}a 1fol4 8 iiito F=A@B=AB+AB : © In Ex—OR, output = 1 if input has odd no. of 1's + In Ex=NOR, output = 1; if input has even no, of 1's 3) Inverter ATF] ‘ Be] tek ps a “ ype D> ® www.krealryx.coma ay tps: //t .me/abcdelectrical KK wReaTeyx Digit ewrenien @ Teg a OY Z d = 4) ANDGATE conyuchey == o[>| Ye IS i ye a Is Te FEAB a 5) ORGATE IE Tme Hor ai ATBIE — o[ofol i o}tsi| TPS ifo}a vals FeA+B iz iS iz iS ey Bi Te Fi a ABE x ofolt Wl oft|a F 3 1jol1 5 cb U0) } a tix Dae This gate is equivalent to — Y=) @Oe)+laee) =) 2— v v www. kreairyx.com Bevlsan Expresscon peduchion, jn ano #9 oaeo cwplt galéze noma oom anes give bubble im ekg of AND and thput of oR Stepd: wee not gate fir ach Bubs ond apply A ae \ a Z i . arehttps: //t .me/abcdelectrical KRCATEVE. Digital teewonicr nd Microprocestrs 7) NOR GATE A ar FaA+B, a . F A This gate istequivalent to 4 B CODES :- Ener 8 Code 1) Binary coded decimal code (BCD) a) Each digit of decimal number is represented by binary equivalent. b) Itis 4 bit binary code. ©) eg. (243). Sats, 2 seca” 40010100 0011 (243), = (100101000011), 2) Gray Code :~ a) Only one bit in the code group changes when going from one step to the next, b) For 3-bit 000 > 001 + 011 4010-5 110-+ 111 + 101 + 100 4 B6eb ww weir. my aI AK Toot —7\tol a [Kroes ——— a ee a cx x —8 e q sogeae dada he) sla@ Hh d HEY KPCATAYE, Digit eons and Mlroprocssors 8 Combinational Logic Circuits tc A 1 2 2 1) Half Adder soos c 7 S=A@B 0 C=AB 0 1 1 Half adder = 1 XOR Gate & 1 AND Gate 2) Half Subtractor Bole oo aia vio olo Soop + To implement a half sub tractor 5 NAND or 5 NOR Gates are required. Not | ANOS} OR }. EXOR | RNR To implement a half adder using NAND Gates, 5 NAND Gates are required To implement a half adder using NOR Gates, § NOR Gates are required, wanp | | 2 i M7 Sty Mux | +f { Pega 2 www.krealryx.com 2 eooo00= AB+BG, +AC, é ee te «+ To implarrent TlTadder using NAND & NOR Gates 9 Gates are required, Correlation ber |'s the loved : ge LG te Ft ap eet a a J Bhgeee i xe (eo pRe comtlaring be oe eee as w, funder ef We Aime =t Acoklicees | "a Re) = AX CesUeU om Notes rene ong aterm 3) FullAdder:: Neg Fm /® emo A aye 1G ]5 [Set >. me PEEL poke moh (H) 0 {3 fo fr fo aR : of |r fo fs = Arma Aonin) AZ LAomctA nin) © HEI FS [greg Am SAE Lit ds [dla Yee Aime Arti, pf Lettie y = Coy int Aine Arie m2? 8 flaatd ze Sian 5 Cory OEM Am wove has pie Fraqueces Bec a Cahier Freruinte > upper Side bard og way 5 Lecoax Gide bard Prequaty Silene shoe Eee pata! » susutde: te + A lB b D bi 7 ao Jo |o fo Ge ies ee ae (> STE Te ft Flag hPa = Ragas = ofa ft fo Ja | eM hye |o |e Js \ fio fo tKsA =jay)=kA The RE Foadg= fet Ke Am Soni peaesen, 4 [SW LFS Fe tkeAin by = AB-+-Bb, +, latr 0b I «+ To implement full sub tractor Using NAND’or NOR Gates 9 Gates are required. www.krealryx.com (Be cl) Br! ea PLL wey Norio bond A, (os Combe LY eSénamlnt] aceon (debamd P= Be w= Ae 2 -Fohnton worse ualkage : Se \ RY. a in = MTR R. pac ie % i nl Pam te _ Re A IPL acc of white wotse= 8 Magnitude Comparator For 2 bit Magnitude comparator . Magnitude a AeAAy 1 B=B,8y A ‘Comparator A, Ay By Bp ADB A=B A @ 47 . \ ! = OR 7 (© 2015 Kreatryx. All Rights Reserved. www.kreatryx.com ai> E | Communatron systers Bandwidth ef Speech Soy ZUK iz px l Cela plone ‘Comm-) a =r ox woos Kpzctoal Bensety. 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Sing he Scat Banke) Nedul SU ER LSB A, aoFa erapancg dice aim inaler ote mel Tea poh I 5 reGeneration oF ¢sB peel oscillator | “ [Pra pie) 3 | Saeed 7 SSB 1 [A Ga Wek Bh | fe peal : Eg TM le shart ; pl bext { faaincithe ap prea yaes oy Sy eg Si ah aA CASO EA HRT MA, CP. LSSte) = Rawls ecw, Gt Ee fot tasteka pings vot 7 AAw ete ae et) est i br) SS caf AP aeycoret +e “HA ninA PPaae ye pe gay be AVA Phase EM oR 7 Ree A Ce8 Ot) A I > : Spu= A beso TRE AA ody, aia nee Sfmae n nef L Sie 3 : 2 nal | Hm TE Tee 3 a1 Rap of : Ce : - : [a 24pu ect ae ne lea plexi Tech ued fEDM (ax quatatug Division |= a7ae ee A) Fiat Spackeim 4 Called?cs DELTAJPa00No. ] bate CCUEPE IIE of FM mH) derek, mafhod a. UVaG aay diode 2 Or ~ _Tratna }DELTAJPas2ne [Dato WW) orkung af hefrodyne. i The Braman Caphier (Ee i wre Sa ahem 1 aixew "a ferwd” on Hee desi — fh mo 1S a ee LALA, aauid net. Wtx2c TES ee SE : eee a (oad we mee af Ceequatn CI.) od Oehaiote S. Oud pur Oey: 1 Ee Lgiaitg CP-EI — The “Weéal Saceleter ae - CEE F : steel yond ; n ly Oy than Sepp Ce rx? 5 z(Ce = Tae LE Ai Rer J pa.Coiye Tain Ae sig deOend jatel js 20 ee ) bad to Tretis ichinf paths eo cab ‘backing Fa VoRECh, Fr tno S Seend dete eens loved 4 of output bo Keep Teter auteut Weta p owt in a etverr |ype OL sage - iG Vow Whi rece'yer FSas 3-9 a le OX I [es (2 rea whe ays op pice patents so eh benrcutai in pn ] rar ROUGHTEPS://t .me/abedelectrical [Keres Q KREATEYX Digital Electonics and Microprocessors ae i S{R [Smet 0 fo fa we o fi fa i 1 |o Jo a /1 }Q, = * dd ¢ S21, R=1 and Qy.r'=1is impractical state 3) Clocked SR Flip Flop ddd : © When CIk = 0, the flip lop retains its previous state eeeedddde © When ci = 1 S.[R [Snot o [0 1a, oa o |i Jo — > oto fe chy, ) [ 1h A= = — is state «Characteristics equations ea sF, | af i i> i» i. www.kreatryx.com 16 o0G00 in i > ar a) \ ™BEEPS: //t.me/abcdelectrical 4) 1=KFlip Flop To convert SR fip flop to a Jk flip flop, =p S=jQ ; R=kQ or 1 Cy | Characteristics equation = @ — a= Saeed, *kQ, . y + De-efx 2 CLK ‘ CLK Cm 0 fo aii Characteristics equation www. kreatryx.com v7 eoGcoog \ tps: //t .me/abcdelectrical EA la Kia KDEATAYE Digital Electronics and Mieroprocesirs SLICER 6) T=Flip Flop — rT @ r =< ok 7 a yy K “ T [Qn o [a 1 Q n Pr Asynchronous oF Q ae cue [TS [Snes x om, for frat g o a1 “fo fo Bi i a | ~—* o\p depends on characteristic table of Preset and clear input when enabled set or reset the flip flop irrespective of the state of clock. ‘Types of Triggering 1) Level Triggered FE 2) Edge Triggered FF [ [ 2 a) ve edge triggered 2 » b) —ve edge triggered 2 ~ | t t PD 2 www.krealryx.com 18 oGoo 2 AD: Xhttps: //t.me/abcdelectrical a Kirotes Digital ectronis and Microprocessors * Level triggered FF are called as atch and edge triggered FF are called as Flip Flops eu} in TERE When a FF is in toggle mode, then due to propagation delay of gates involved in_ Construction OF FF, output toggles multiple times instead of once & this is called as Race “around condition, ‘+ “THIS only occurs in level triggered FF. * To avoid this problem, Master — slave configuration is used. ‘Note: Whenever a FF is n'toggle mode, output frequency is half of input frequen Applications of FE 1) Shift Regist. face around Conditi °, P, Po Preset (Parallel enable ‘aput) @ Q batt Bet > PF at —oa, “i Serial Serial. ‘a input output | Ur 3- bit shift Register a Q, Q Qq — parallel output P, P, Po > parallelinput 2) Serial input parallel output (SIPO) IK seriali/p Q, Q, oN ON’ Oo 1 1N0N 0 Parallel output, 0 oNW oO a 1 1 0 1 For n—bit, time taken = mxT —T=clock period wae www.kreatryx.com 19 eoeo00/t.me/abcdelectrical 1 Electronics and Miroprocesi votes oun, 2) Serial input serial output (SISO) ck seialo/p —Q, Q 0 = oN oS 1 1 SN oN 2 0 oN Ww 3 1 IN oN 4 =, = IN 5 s a is For n- bits, time taken = (2n - 1)T, T= clock period J input | output (PIP) 3) Bi output it does not require any clock pulse ‘output (PISO) 4) Parallel input seri Suppose P, Py Py = (101) ck QQ, - IN ON 17 1S" 2 - Serial output For n— bits, (n-1) clock cycles are required. & serial output Parallel input can be fed to register using preset enable and for input to propagate to parallel\ hetps://t .me/abcdelectrical Ila citron COUNTERS Asynchronous Counters * Different f are applied with different clocks. ‘+ No.of stages in a counter are called as modules of a counter. MOD - 5 Counter = § Stages Qas clock ~>_up counter i) “Fve edge trigger > Q as clock > ‘up counter ii) *veedge trigger > @_as clock + down counter 0 Oe _—_* $ = ivy 7 ave edge trigger > Q as clock -» down counter BCD Counter (Decade Counter) + 4Flip flops are required. ie 1— sae yan : ce {| x ‘This counter counts from 0000 ~ 1001 “And as son as count is inéremented to 1010, then CLR input of ffis asserted and all fare reset to 0 and count again becomes 0000, 50 this counter counts from 0 — 9. Ring Counter (Synchronous Counter) ‘The last FF output is connected to first FF input. www.krealryx.com 2 eoGoohttps: //t.me/abcdelectrical ye KOCATEVE ck Q, QQ 0 0 0 0 1.0 014 2 1 0 0 3.0 1 0 40014 An-bit synchronous counter has n ~ status. Johnson Counter (Twisted ing Counter) a ax) ck QQ, Q5 0 0 0.0 1 1 050 21 1-0 3114 4011 5 001 6 0 0 0 ‘An~bit Johnson counter has 2n states: T= (2n) Toy nchronous counter desi for given sequence * Suppose counting sequence is 0-3-1240 * Using positive edge triggered D — FF www.kreatryx.com 23 eoeoLAN Ween me/abedelectrical Kroes igs etn and Mirae ‘State diagram («) 7b ©) et i 0 0 % OG \ Excitation Table Bitte \ \ Present state Next State Di Do Dig 0 \ % Q% % ay ws 0 0 +4 11 14 01 o 4 O41 10 10s 150 0 0 oe0. B, = p=, 0% ELL) cu x a z www.krealryx.com 4 eoGcoonhttps: //t .me/abedelectrical KRCATAYX Digital ctrl and Microprocessor Korores Conversion of different flipflops From SR IK D T Flip Flop Flip Flop Flip Flop Flip Flop ‘SR FF S=JQ s=TQ R=kQ TQ IK FF T=5 ~ T K=R T OFF D=S+RQ D=JO+kQ TeQ TRF TSSQ+RQ T=JQ+KQ : A/D and D/A Converters Digital to Analog Converter (DAC) * Resolution The change in analog voltage corresponding one LSB increment in digital input. V, = reference voltage corresponding to logic 1 N= no. of bits y, ‘analog 1 S%resolutior a * Resolufon of R~2R ladder ype DA v Resolution = —£ —— 2 100% = Resolution Decimal equivalent of binary i/pNice dddd. J. Idddd #//t .me/abcdelectrical wKecateyx iit e 1) Weighted Resister DAC (4 - bit) 1 Me ate \ aM Ret tS Fon ba “( [wrtei a aaa LSB Resistance = (2-1) MSB Resistance 2) R=2Rladder R a) 3=bit Non- inverting R= 2R ladder ( nh Saf ") Vp -[t+£ y=! © aib| ret OUR) 21% Ry =ResolutionxDecimalxgain www.krealryx.com 26 oGoo\ https: //t.me/abcdelectrical KREATRYX Digit Hlectronies and Microprocesors, ‘b) 3=bit R-2R Inverting ladd Knrotes Analog to Digital Converter (ADC) a) Counter Type ADC Vitea, cK Counter Maximum number of clock pulse required for n — bit conversion is Ma Conversion tine = (2-1) ey DAC i) www.krealryx.com 7 oeoo amcena ) Parallel Comparator Type (2 - 1 comparators required © Forn—bit 42° resistors required 2 xnpriorty encoder ‘© This is called as Flash ADC, A YE, axa I iD, | @ Priority . 3 encoder cK 1 clock required Fastest ADC of all ‘© For SAR & Dual slope ADC, refer EMMI K ~ Notes. www.krealryx.com 8 gooodhttps: //t .me/abedelectrical Fa Korotes xeeavave igi Eerie nd Mcroprocsor jc Fa 2D. RIL (Resistor Transistor Logic) (Wired AND Logic) Ve (Basic NOR Gate) AB oo 1 0 1 cut-off», saturation 0 10 saturtion cut-off 0 11 saturation ‘saturation 0 2) DIL (Diode Transistor Logic www.krealryx.com eoeon bebe ldjddee. y dag 4} (RR I ah 9p | th - th (L/S [=p3 Je aN bddddddd i a aoe Lm * 4400p PS: //t.me/abedelectrical B 0 OFF 1 OFF 0 OFF 1 ON © When all input are high then Dy & Dg are reverse biased and D,, and T, becomes ON and utpuit becomes low. Knotes —> NAND Gate Y 1 1 1 0 D,. Become forward biased L (Transistor Transistor Logic) i V. T; (Nand gate) : multi - emitter Transistor Bh Gy Ye SS oaccst ay 1aAccSs1 oaAccs1 1AS SCO : Active 2 Cut - off Saturation www.kreatryx.com ive eo0Go0o