Verdi and Siloti Automatic Tracing of X’s with Verdi’s Temporal

Flow View
1. In nTrace or nWave windows, select a signal that has transitioned

Quick Reference 2.
to an X.
Click Auto Trace toolbar icon .
Alternatively,
Guide • Right-click to invoke Temporal Flow View -> Create
Temporal Flow View.
• In Temporal Flow View, select a port signal, right-click to
invoke Trace Active X.

Table of Contents Choose Cycled Based or Transition Based TFV

• Automatic Tracing of Value with Verdi’s Temporal Flow View 1. For RTL debug, typically select Cycle Based TFV.
• Automatic Tracing of X’s with Verdi’s Temporal Flow View 2. For GATE debug, select Transition Based or Cycle Based with
• Choose Cycled Based or Transition Based TFV Clock Skew.
• Active Tracing of RTL
3. Select Cycle Based (if using RTL or Gate Level Net List with
• Function Debugging
SDF).
• Macro Debugging
• SystemVerilog TestBench (SVTB) – FSDB Logging 4. Try TFV in Cycle Based with Clock Skew. Find the frequency
• SystemVerilog TestBench (SVTB) – Testbench Browser of the fastest clock. Set 1/6th or 1/10th of the clock period in the
• Compile and Dump SystemVerilog Assertion Clock Skew setting for the Behavior Analysis (BA) engine to
• Compute Newly Added SVA in Verdi without Re-running Simu- take the SDF timing delay information in the FSDB into account
lation for Trace Active X. If Clock Skew is not used then the BA
• Analyze the Reason for Assertion Failures engine will not know that if delay data exists in the FSDB and
• Shift Time for Signals treats the design like it is a zero time cycle based design. Not
• Count the Transitions of a Clock or Register ideal for Gate Level simulations with SDF.
• Modify Existing Logical Operation Signals For example, if the FSDB time scale is in ‘ns and clock period is
• Trace Memory Contents without Re-running Simulators 100 ns, then enter 17 or 10 (1/6th or 1/10th of the clock period,
• Compute Memory Contents and Write to an FSDB File respectively) into the Worst Case Clock Skew field.
• Virtually Combine Multiple FSDB Files as a Single FSDB • In nWave, when you do Behavior Analysis or invoke TFV
• Aliasing and Alias Files by choosing a signal then right-click to invoke Temporal
• Toggle Coverage Analysis Flow View -> Create Temporal Flow.
• Compare Two FSDB Mismatches • In Create Temporal Flow View window, in the Default
• Compress Time Region Trace Method section, select the Cycle Based option.
• Collapse Source Code • In Create Temporal Flow View window, select Advanced
• Transaction Evaluator tab -> Clock Skew tab, then set Worst Case Clock Skew
• Advanced Transaction Analysis to 17.
• nAnalyzer - Clock Tree Crossing
5. Cycle Based TFV is good for tracing X multiple clock cycles
• nAnalyzer - Switching Reports
back. It uses a cycle-based model to compute the stable-state
• nAnalyzer - Timing Analysis
value and compare it with FSDB value.
• nECO - Graphical Engineering Change Order Enhancement Tool
-OR-
- Modify Gate Level Netlist - Non-Freeze Silicon ECO
• Accelerate Simulation and Reduce Dumping Size with Siloti 6. Select Transition Based (if using Gate Level Net List with
• Resources SDF).
7. If you encounter a mismatch in the last cycle, while using Cycle
Based TFV, where there is a timing propagation delay in the
Automatic Tracing of Value with Verdi’s combination logic greater than the clock period, use Transition-
Temporal Flow View Based TFV trace to see the transition propagation within the fan-
1. In nTrace or nWave windows, find a signal that you want to in cone. Transition-based tracing does not check mismatches. It
debug. simply follows the most recent transition on the gate inputs and
2. Select the signal. traces further.
3. Click the Auto Trace toolbar icon . • Right-click to invoke Temporal Flow View -> Create
Alternatively, Temporal Flow View.
• Right-click to invoke Temporal Flow View -> Create • In Create Temporal Flow View, in the Default Trace
Temporal Flow View. Method section, click on “Transition Based” option.
• In Temporal Flow View, select a port signal, right-click to
invoke Trace This Value. Active Tracing of RTL
If the value of multiple signals is traced, you may find that some 1. In nWave, select a specific signal that you want to debug.
paths are merged into the same path for a better high level view. 2. Double-click an transition point that you want to debug.
This takes you to the line in source code that is causing the
transition.
3. In nTrace, invoke Source -> Active Annotation.
4. Click on the signal, right-click to invoke Active Trace.
Function Debugging
1. In nTrace, find a signal that is driven by a function, i.e. “add”,
etc.
2. Invoke Source -> Function Annotation.
3. Double-click the function, i.e. “add”.
4. Click on function, i.e. “add” to jump back.
Macro Debugging
1. In nTrace, find a macro, i.e. MACRO1(CLOCK2).
2. Put your mouse cursor on MACRO1. The tip window shows the
definition of MACRO1.
3. Invoke Source -> Expand Macro.
SystemVerilog TestBench (SVTB) – FSDB
Logging
1. The $fsdbLog dumping command can be used to log messages
into the FSDB file. The use of $fsdbLog is not restricted to
SVTB and can be used anywhere in your environment where you
have previously used crude text logging mechanisms to log
interesting information. The flexibility of $fsdbLog allows you
to capture not only messages but also severities, variable states,
etc:
• For VCS, use the VCS 2006.06-SP1-18 or above versions
with the vcsd2006.06 dumper.
• For NCSim, use IUS6.2 with the ius6.2_vhpi dumper.
• For ModelSim, use ModelSim 6.3f with the modelsim_
fli6.3 dumper.
SystemVerilog TestBench (SVTB) – Testbench
Browser
NOTE: SVTB Testbench Browser is still considered general beta.
1. To load a VMM based SVTB environment, specify VMM
option:
• % vericom –sv -f run.f -ntb_opts vmm
• % verdi –sv –f run.f –ntb_opts vmm
Specify VMM library path explicitly:
• % vericom –sv -f run.f +incdir+/home/user/vmm_lib
• % verdi –sv -f run.f +incdir+/home/user/vmm_lib
2. Set the environment variable VERDI_SVTB_BETA to 1 to
enable Testbench Browser function.
• In nWave, invoke File -> Open to load an FSDB that
contains SVTB logging message streams (dumped by the
$fsdbLog command).
• In nTrace, invoke Tools -> Testbench Browser to open the
Testbench Browser window which provides a software
oriented view for the design and testbench. All declared
modules, classes, interfaces, and programs are sorted and
displayed in a tree view for easy browsing.
• In nWave, click Get Signals icon to add the logged message
streams under the msg_root scope to nWave window.
Inspect the logged message in nWave window. Or use the
middle mouse button to select a message record in
waveform pane to drag and drop in the source code pane of
the Testbench Browser window to find the source code
which produces the message.
Compile and Dump SystemVerilog Assertion
1. Compiling:
• If all design files are SystemVerilog compliant, specify the -sv or
-sverilog option in Verdi.
• % verdi -f run.f -sv
• If there is a mixture of Verilog and SystemVerilog design files,
then compile with:
• % verdi -f run.f +systemverilogext+.sv+.SV
+verilog2001ext+.v2k
• Or if Verilog files use .v use: +verilog2001ext+.v+.V
• Or use all the vericom command lines for the Verdi work lib:
• % vericom -f run_verilog_files.f
• % vericom -2001 -f run_v2k_files.f
• % vericom -sv -f run_sv_file.f
• % verdi -lib work -top <testbench>
NOTE: With above +ext+ examples, files with extension name (.sv
or .SV) will automatically be recognized as SystemVerilog.
Files with extension name (.v2k) will automatically be
recognized as Verilog-2001. Files with extension name (.v)
will automatically be recognized as Verilog-95.
2. Dumping:
• $fsdbDumpSVA; command is required to dump SVA. Only
asserts will be dumped, Verdi will calculate properties automati-
cally when analyzing.
• For VCS, set LD_LIBRARY_PATH to the Novas dumper, the
VCS version will be selected automatically. For example:
% setenv LD_LIBRARY_PATH ${NOVAS_INST_DIR}/
share/PLI/VCS/${PLATFORM}
• Include the -debug_pp option to enable the basic post
processing debug capability.
• Include the -sverilog option to enable SystemVerilog
features.
• Use the -P option to specify the Novas PLI table file. For
example:
% vcs -line -debug_pp \
-P ${NOVAS_INST_DIR}/share/PLI/VCS/
${PLATFORM}/novas.tab \
${NOVAS_INST_DIR}/share/PLI/VCS/
${PLATFORM}/pli.a \
-f run.f -sverilog
• For IUS, set LD_LIBRARY_PATH to the Novas dumper, the IUS
version will be selected automatically. For example:
% setenv LD_LIBRARY_PATH ${NOVAS_INST_DIR}/
share/PLI/IUS/${PLATFORM}
• Include the -sv option to enable SystemVerilog features for
ncvlog.
• Include the -access +R option to add read access to attempt
for NCSim. For example:
% ncvlog -sv -f run.f
% ncelab top -access +R
% ncsim top
• For Modelsim, set LD_LIBRARY_PATH to the Novas dumper,
the Modelsim version will be selected automatically. For
example:
% setenv LD_LIBRARY_PATH ${NOVAS_INST_DIR}/
share/PLI/MODELSIM/${PLATFORM}
 • Include the -sva and -assertdebug in vsim command line.
• Use the -pli option to specify the Novas PLI table file. For
example:
% vlog -f run.f
% vsim -sva -assertdebug -pli
${NOVAS_INST_DIR}/share/PLI/MODELSIM/
${PLATFORM}/novas_fli.so top
Compute Newly Added SVA in Verdi without Re-
running Simulation
1. Load design and signal level FSDB into Verdi.
2. In nTrace, invoke Tools -> Property Tools.
1. In the Property Tools window or Assertion Hierarchy
View pane, click the Get Properties icon . Apply button at the bottom.
2. In the Total Assertions section of the Get Properties form,
click the scope/instance that has your SVA code.
•When you see your assertion in the next column that you
want to evaluate, double-click it.
3. Click the OK button.
•You can see the chosen assertion in the hierarchy tree of the
Property Tools window.
4. Click the Evaluate icon . Rising Edge options, then click the Apply button at the bottom.
5. Click the assertion that you want to evaluate in the hierarchy
tree of the Property Tools window.
6. Click the RUN button at the bottom right of the Property
Tools window.
7. Double-click a row in the FSDB Statistics tab, in the
Results Mode window.
•A Property Details area will appear below the FSDB
Statistics tab.
Analyze the Reason for Assertion Failures
1. Click the assertion property that you want to analyze/debug.
2. Then double-click the assertion property or click the Analyze
Property button . Trace Memory Contents without Re-running
Now an Analyzer tab appears at the bottom of the Property Tools
window.
3. Scroll down the Analyzer pane to view property and sequences
for the specific SV Assertion that you want to debug.
4. Notice the time information above and the data information
below the variable signals in the sequences.
5. Click the Expand button . automatically locate the last write.
This will focus in on the logical failures in the sequence.
6. In nWave, select the SV Assertion that you want to debug and
invoke Waveform -> Expand/Shrink Property Signal.
7. View the expanded assert at top for the specific SV assertion that
you want to debug.
8. To automatically add the evaluated/analyzed SVA property to the
nWave window, invoke View -> Options from the Property Tools
window.
• From the Analyzer tab of the Assertion Options form,
enable the Add Evaluated Signals to nWave
Automatically option.
Shift Time for Signals
1. To shift the complete FSDB file:
• In nWave, invoke Waveform -> Waveform Time -> Shift
File Time.
2. To shift just one signal’s time:
• In nWave, invoke Waveform -> Waveform Time -> Shift
Individual Signal Time.
3. Enter the time (+ or -) to shift the FSDB file or signal by, for
example: 500.
Count the Transitions of a Clock or Register
1. To turn on the Grid Count in nWave:
• In nWave, invoke View -> Grid Options.
• In the Grid Options form, enable the Grid on, Rising Edge,
and Grid Count with Start Number options and click the
• Left-click in the nWave window to move the start count on
the signal that you want to count.
2. To Jump to the 100th rising edge, for example:
• Go back to the Grid Options form and click on the Lock
Grid Count and Jump Cursor to Grid Number and click
the Apply button at the bottom.
3. From the same Grid Options form, disable the Grid on and
Modify Existing Logical Operation Signals
1. In nWave, left-click a signal that you’d like to create a copy/
modify.
2. In nWave, invoke Signal -> Logical Operation, and then select
an existing logical operation signal in the Logical Operation
form.
3. Modify the content in the Expression field, for example, if you
have selected an 8 bit register, perform a logical right two bit
shift operation like this: “top/reg1[7:0]” >> 2
4. Click the Create/Modify button.
Simulators
1. From TFV, invoke Tools -> Show Memory Contents.
-OR-
From nTrace, right-click to invoke Debug Memory -> Show
Memory Contents.
2. In nMemory window, invoke Time -> Sync Cursor Time to
Compute Memory Contents and Write to an
FSDB File
1. Find location for memory array. In nTrace source code pane,
right-click to invoke Debug Memory -> Dump Memory
Waveform to FSDB.
• In Dump Memory Waveform to FSDB form, be sure to set
start time and end time and enter name for Dump FSDB
File similar as “my_memory_dump.fsdb”,
• Then click Start Dumping button.
2. In nWave, invoke File -> Edit Virtual File.
• In Virtual File Editor form, set Virtual File Name similar
as "original_plus_memory_data.vf";
• Then select the original FSDB file and the new
"my_memory_dump.fdsb" file and click the Add button.
 • Then click the OK button. • Select Full, Partial or Any Change in Toggle Criterion
3. Find the location for the memory array. In nTrace source code section.
pane, right-click to invoke Debug Memory -> Show Memory • Then click Apply button.
Contents. • Click the Report button to see the toggle report.
• Then in Get Memory Variable form, select Dumped by 3. In the Toggle Coverage Report form, select Toggled or Not
Simulator tab, find your memory array name in right side Toggled in the List by section.
of form. Select it and then click OK button. 4. To save report, click the Save button and save the result as
4. Finally, in nMemory window, click the search arrow buttons to "something.rpt".
find changes of last write in memory array. These changes will
show in red.
Compare Two FSDB Mismatches
1. Open two nWave windows with different FSDB files. Ideally
Virtually Combine Multiple FSDB Files as a pass vs. fail FSDB files on same test or RTL vs. Gate simulation
Single FSDB on locked in signal names.
1. Open a new nWave window. • In the first nWave window, invoke File -> Open, select an
• In nTrace, click nWave icon on menu bar FSDB file and click the Add button, then click OK button.
-OR- • In the second nWave window, invoke File -> Open, select a
• Invoke Tools -> New Waveform from pull-down menu. different FSDB file and click the Add button, then click OK
2. In nWave, invoke File -> Edit Virtual File. button.
• In the Virtual File Editor form, enter a name for your virtual 2. Put the same signals to the two nWave windows. You can drag
file in the Virtual File Name section, similar as and drop signals from one nWave window to another.
"total_virtual_file.vf". 3. Synchronize the nWave window cursors.
• Select an FSDB file and click the Add button. Add more • In the first nWave, invoke Windows -> Sync Waveform
files in the same way, and then click the OK button. View.
3. If you already have many other FSDB files opened in the current • In the second nWave, invoke Windows -> Sync Waveform
nWave window, you have to set the new virtual file as active: View.
• In nWave, invoke File -> Set Active. 4. Compare any parts of the signals, e.g. compare all signals in each
• In the Active File form, select the virtual file that you just group for both nWave windows.
created and click the OK button. • In nWave, invoke Tools -> Waveform Compare
-> Compare Two Groups.
Aliasing and Alias Files • In Compare Two Groups form, click Groups in Different
Windows.
1. Use the -autoalias option on Verdi command line for automatic
mnemonic recognition for ‘defines and parameters. • Select the first group name from the first Group Name
selection field. And select the second group name from the
• % verdi -f run.f -autoalias
second Group Name selection field.
2. Use aliasextract to extract an alias file from a compiled library.
• The Comparison Result form shows your comparison
The default is extracted.alias.
results for the signals in each group.
• % vericom –f run.f –lib work
• To save report, click Save button to save the report as a .txt
• % aliasextract -lib work file.
3. Use the -aliasFile option on Verdi command line to load an alias 5. Search by mismatches:
file.
• In the first nWave window, make sure Search By option is
• % verdi -top system -aliasFile extracted.alias set to Mismatches (/), then click on the blue horizontal
4. To add an alias file from nWave: arrows next to the Search By option.
• In nWave, click a bus signal in the hierarchy pane.
• Invoke Waveform -> Signal Value Radix -> Add Alias Compress Time Region
from File. 1. In nWave, invoke View -> Compress Time Range.
• Then select the .alias file, and click OK button. • In the Compress Time Range form, enter the value in the
• The .alias file contains lines that look as following: From Time and To Time fields.
ADDA 6'h0d -OR-
ADDB 6'h0e • Go to nWave window, left-click a starting time and right-
click an ending time, then go back to Compress Time Range
Toggle Coverage Analysis form and click Cursor/Marker button.
1. Bring in as many FSDB files as you like: • Click the Insert button.
• In nWave, invoke File -> Open. 2. Compress time in the nWave window.
• Select an FSDB file and click the Add button (select more if • You can add more compressed time ranges by repeating
needed). Then click OK button. previous steps.
2. In nWave, invoke Tools -> Toggle Coverage Report. • You can also remove compressed time ranges by clicking a
• In the Toggle Coverage form, your FSDB files are shown in specific compressed time range in the main section in the
the Target File(s) section. Compress Time Range form and click the Delete button.
 • When done, click the Close button.
Collapse Source Code
1. In nTrace\, enable Automatic Source Code Folding option in
Tools -> Preferences -> Source Code page -> Miscellaneous
page.
2. In the source code of the nTrace window, you see process and
while blocks with a [-] and [+] next to the line number. Click on
the minus [-] icon to collapse code.
3. If you want to expand all the collapsed code, invoke View ->
Source Code Folder -> Expand All in Scope in nTrace.
4. To collapse all the code in a specific module, invoke View ->
Source Code Folder -> Collect All in Scope in nTrace.
Transaction Evaluator
1. Transactions can come from multiple sources:
• Some languages, i.e. SystemC, e, SVTB and Vera, have a
notion of transactions and abstract transaction-level data can
be directly dumped into the FSDB database.
• Transaction IP such as SpiraTech can dump transaction-
level data using APIs since they are transaction-aware.
• End-users can bolt in our API into their own proprietary
tools or models to dump the data in transaction format.
2. Describe the sequence of events that make up transactions in
SVA and use the Transaction Evaluator engine to create the
transaction data. Reasons for using SVA:
• It is a standard language which many users are becoming
increasingly familiar with. The ramp-up time for adoption is
hence much shorter.
• Assertion languages have facilities to specify temporal
sequences of events.
• Some of the SVA code that is written for its original
purpose, i.e. assertion checking, can be re-used for
transaction extraction.
• SVA has local variables which can map to transaction
attributes. SVA’s local variables give it an advantage in this
regard over other assertion languages.
3. When the waveform view is too cluttered with signals, define the
transaction using SVA. A suffix of _nTX is recommended for the
assertion name.
4. In nTrace, invoke Tools -> Transaction -> Transaction
Evaluator.
5. In the Transaction Evaluator form, select a transaction to drag
and drop into nTrace.
6. In nTrace, double-click the property referenced in the assert
statement to trace to the underlying sequence.
NOTE: The sequence describes a sequence of signal events that can
be used to capture transaction-level data for the ‘single
write’ action with the Transaction Evaluator engine.
7. In Transaction Evaluator form, click Evaluate button to create a
new FSDB with transaction data.
8. In nWave, open Get Signals form to select the transaction
streams, e.g. NEW_ASSERT_nTX under the scope where you
put your transaction code and add to waveform. Select one of the
transactions of NEW_ASSERT_nTX in waveform area, and then
click-right on Properties to open Transaction Property form to
change each of its attribute’s value radix to “Hexadecimal”.
Single write and read transactions will be displayed in the
waveform.
9. In nWave, compare read and write transactions to bus signals.
Advanced Transaction Analysis
1. In nWave, invoke Tools -> Transaction -> Analysis Window to
open the Transaction Analyzer window.
2. Add a few transaction streams into the Transaction Analyzer
window by clicking the Get Signals button. Then double-
clicking on transactions in the Get Signals form.
3. Click on column heading to sort.
4. Click on Statistic Window icon, then click on Full Range
button and click OK.
5. In Statistic Window, invoke Window -> Duplicate Window as
-> Pie Chart.
nAnalyzer - Clock Tree Crossing
NOTE: This Topic is still considered general beta.
1. In nTrace, invoke Tools -> New Schematics -> Clock Tree.
2. Click the Import SDC Format button to open the Load SDC
form.
3. Select a SDC (Synopsys Design Constraint) file and then click
OK to extract clock trees for the target clock sources.
4. In nTrace, invoke Tools -> Clock Analyzer -> Extract Clock
Information.
nAnalyzer - Switching Reports
NOTE: nAnalyzer is an optional Verdi module.
1. In nTrace, invoke Tools -> Switching Analysis -> New Query.
• In Switching Analysis form, working scope should be a
scope that you want to focus on, or just use the top scope for
everything, e.g. tb_CPUsystem.i_CPUsystem.i_CPU;
• Enable Include Instances under the Hierarchy.
• Enable Switching Activity Report for the report type.
• Click OK.
2. In the Switching Analysis Report window,
• In the Filters tab, enter in a module name to search for, i.e.,
enter: *alu* in the Module text field.
• In the Sorting Scheme tab, select the Sort By option as
Name and also enable the Ascend option. Left-click the
Transition Count column to sort the results by the number
of transitions.
3. In the Switching Analysis Report window, click the New Query
button to open the Switching Analysis form.
• In the Switching Analysis form, you can change the working
scope to another level, i.e.,
tb_CPUsystem.i_CPUsystem.i_CPU.i_ALUB.i_alu;
• Enable the Peak Activity Report option in the Report
Type section.
 • Click OK.
NOTE: The new Switching Analysis Report window has different
Time stamps with Transition Count and also notice the
“Time Period” at the top of the window should have some
range, e.g. “0 ~ 15000 x ns”.
• To find the location for the highest peak activity for an
instance of time, double-click on the row in the Switching
Analysis Report window that has the time that you want to
see. This will open a new Switching Analysis Report
window but the Time Period will be one snapshot in time,
i.e. “3000 ~ 3000 x ns”. This will give you all the locations
in that time snapshot and their Transition Counts.
nAnalyzer - Timing Analysis
NOTE: nAnalyzer is an optional Verdi module.
1. In nTrace, invoke File -> SDF -> Load SDF Files ->
<your_sdf_file>.sdf
2. In nTrace, invoke Source -> Find String; enter the name of a
register where you want to start. Select Match Case and In All
Files options; double-click on desired result in the message pane
at the bottom of the nTrace window.
3. In nTrace, click nSchema icon.
4. In nSchema, invoke Trace -> Two Points.
5. In nTrace, drag and drop starting point output pin into From
field of Trace Two Points form.
6. In nTrace, invoke Source -> Find String; enter some name of a
register where you want to end; Select Match Case and In All
Files options; Double-click on desired result in the message pane
at the bottom of the nTrace window.
7. In nTrace, drag and drop ending point output pin into To field of
Trace Two Points form.
8. In Trace Two Points form, click the Trace button.
• In View Trace Result Schematic window, invoke Schematic
-> SDF Annotation.
• In View Trace Result Schematic window, invoke Schematic
-> Delay Type and Schematic -> Delay Scale.
• In View Trace Result Schematic window, invoke Trace ->
Shortest/Longest Path and select Longest.
• In nSchema window, right-click on cell to invoke Show
Cell Delay.
nECO
- Graphical Engineering Change Order
Enhancement Tool
- Modify Gate Level Netlist
- Non-Freeze Silicon ECO
NOTE: nECO is an optional Verdi module.
NOTE: Frozen Silicon, spare cells need to be specified.
1. In nTrace, invoke File -> Import Path Data File to open a
Timing Report form.
2. In Timing Report form,
• After Enable Sorting, select Descending or Ascending.
• Then select a path with the worst slack
• Click File Viewer in Show On section, then click Show
button at bottom
-OR-
• click on nSchema in Show On section, then click Show
button at bottom.
3. In nSchema, invoke Schematic -> Auto Fit Found Object(s).
Drag longest slack path on delay to nSchema
4. Fix the delay. In nSchema, find the cell output pin that may have
the highest slack, and right-click for Trace Connectivity.
• Assume the combinational logic on the load is too much,
then, right-mouse-click and drag over all necessary and
Shift click all Connected logic.
5. In nSchema, invoke Tools -> New Schematic -> ECO Window
for Selected.
6. In ECO Window, for example, to share a load of eight cells:
• Shift click on bottom four B inputs, then click Disconnect
Pin from Net button, at top of window.
• Find the cell that has too much load on it, right-click on cell
to invoke Copy Instance, and then right-click to invoke
Paste Instance.
• Click on output of new cell to carry load and previous
disconnected pins, and then click on Make Connection
button at top of Window.
• Connect all inputs of old loaded cell to inputs of new copy
that will help share the load.
• Click the Keep Placement button at top of window to turn
it off and on to reroute placement.
• In nECO, invoke File -> Commit Change.
7. In nTrace, change to the scope where the change was made by
double-clicking, then search for the word Novas to see changes
8. In nTrace, invoke File -> ECO -> Save ECO Netlist can also
save eco script.
• To save ECO Netlist form, turn on Affected Files Only,
then click OK.
9. In nTrace, invoke File -> ECO -> ECO Report.
• In ECO Report form, append eco0/eco.log to the Full File
Name text field, then click OK.
• % cd eco0; % emacs eco.log
Accelerate Simulation and Reduce Dumping Size
with Siloti
1. Run a Siloti command as following:
• % esa –f run.f –hier_eslist es.list –bas cmp_top.iop
• -bas <scope> = Perform Behavior Analysis on the specified
scope immediately after loading design. If the specified
scope does not exist, Behavior Analysis will not be
performed.
• –hier_eslist = Specify the output file name for hierarchical
format only; recommended for simulation to get better
performance.
2. We have analyzed the design with Behavior Analysis to generate
a minimal but sufficient set of signals to be dumped during
simulation to provide 100% visibility during debug.
3. Be sure to add in the Novas FSDB dumping commands into your
testbench:
• $fsdbDumpfile("esd.fsdb");
• $fsdbDumpvarsES("es.list");
4. Then run your simulation again.
5. The result of this simulation is in the ‘esd.fsdb’ file. You could
have named it anything.
6. Load design and essential signal FSDB file into Verdi:
• % verdi –f run.f –ssf esd.fsdb –ba –de –sigexp –ba_mode
WSBA
• –ba = Perform Behavior Analysis immediately after loading
design.
• –de = Perform Data Expansion setup (auto time window
mode) automatically after loading the design.
• –sigexp = Enable signal expansion by default. All signals in
the design are displayed in the Get Signals form whether
they are dumped to the FSDB file during simulation or they
can be expanded.
• –ba_mode WSBA = Run Behavior Analysis in non-
incremental mode. Specify WSBA to do scope base
Behavior Analysis for all top scopes. There are two modes
for this argument:
WSBA: Perform non-incremental Behavior Analysis in
working scope mode.
MBBA: Perform incremental Behavior Analysis in module-
based mode.
7. Enable Active Annotation by invoking Source -> Active
Annotation in nTrace to view data expansion results. Note that
the value calculated by the Data Expansion engine will be
marked as purple.
8. Drag local signals to nWave. Drag an instance in the Verdi
session.
9. Create a Temporal Flow View from this transition to view full
capabilities of Verdi debug.

Resources
• Verdi User's Guide & Tutorial: $NOVAS_HOME/doc/
VerdiTut.pdf
• Siloti User's Guide & Tutorial: $NOVAS_HOME/doc/
SilotiTut.pdf
• nECO User's Guide & Tutorial: $NOVAS_HOME/doc/
nECO.pdf
• nAnalyzer User's Guide & Tutorial: $NOVAS_HOME/doc/
nAnalyzer.pdf
• nCompare User's Manual: $NOVAS_HOME/doc/
nCompare.pdf
• Demo cases: $NOVAS_HOME/demo
• Verdi and Siloti Command Reference Manual:
$NOVAS_HOME/doc/novas.pdf
• Application Notes, FAQ, Newsletter, Release Notes: http://
support.springsoft.com