VLSI MAJOR PROJECTS LIST

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1 Short Bit-Width Twos Complement Multipliers

2 VLSI Implementation of OLS encoders

3 BOOTH ENCODER MULTIPLIER

4
5 Realization of basic gates using MUX in CMOS design

6 Design of Digit-Serial FIR Filters: Algorithms,

Architectures and a CAD Tool

7 Implementation of OFDM System using IFFT and FFT

8 Multi operand Redundant Adders on FPGAs

9 An Efficient Field Programmable Gate Array

Implementation of Double Precision Floating
Point Multiplier using VHDL

10 Computing Two-Pattern Test Cubes for Transition Path

Delay Faults

11 Fpga Based High Speed Parallel Cyclic Redundancy Check

12 20-GHz 8 ​× ​8-bit Parallel Carry-Save

Pipelined RSFQ Multiplier

13 HIGH SPEED CARRY SAVE MULTIPLIER BASED LINEAR

CONVOLUTION USING VEDIC MATHAMATICS

14
Modulo 2​n​-2 Arithmetic Units
 VLSI MAJOR PROJECTS LIST

15 FPGA Implementation of 2-D DCT Architecture for JPEG

Image Compression

16 VLSI implementation of Fast Addition using

Quaternary Signed Digit Number System

17
Performance Evaluation of Complex Multiplier Using
Advance Algorithm

18 A Novel VLSI DHT Algorithm for a Highly

Modular and Parallel Architecture
19 Design of High Speed Vedic Square by
using Vedic Multiplication Techniques
20 A low power single phase clock distribution using VLSI
technology

21 Area-Efficient Parallel FIR Digital Filter Structures for

Symmetric Convolutions Based on Fast FIR Algorithm

22 A Verilog Model of Universal Scalable Binary Sequence

Detector

23 Design and Simulation of 32-Point FFT Using Radix-2

Algorithm for FPGA
Implementation

24 HARDWARE MODELING OF BINARY CODED DECIMAL

ADDER IN FIELD PROGRAMMABLE GATE ARRAY

25 A Novel Approach for Parallel CRC generation for high

speed application

26 High-Performance High-Valency Ling Adders

27 Design and Implementation of High-Performance

 VLSI MAJOR PROJECTS LIST
High-Valency Ling Adders

28 PERIOD EXTENSION AND RANDOMNESS ENHANCEMENT

USING HIGH-THROUGHPUT RESEEDING-MIXING PRNG

29 Design and Implementation of Two Variable

Multiplier Using KCM and Vedic Mathematics

30 SINGLE CYCLE ACCESS STRUCTURE FOR LOGIC TEST

31 ON MODULO 2​n​ + 1 ADDER DESIGN

32 A LOW-POWER SINGLE-PHASE CLOCK MULTIBAND

FLEXIBLE DIVIDER

33 Platform-Independent Customizable UART Soft-Core

34 An efficient FPGA implementation of the Advanced

Encryption Standard algorithm

35 Design and Implement of FFT Processor for OFDMA

System Using FPGA
36 Reliable and Cost Effective Anti-collision Technique
For RFID UHF Tag

37 Design of FIR Filter Design Based on Faithfully Rounded

Truncated MCM

38 Implementation of JPEG2000 using DWT

39 FPGA implementation of multi operand redundant

adders

40 Multi bit Flip-Flop design for Area efficiency

 VLSI MAJOR PROJECTS LIST

41 MDC FFT/IFFT Processor With Variable Length

42 Built-In Generation of Functional Broadside Tests Using a

Fixed Hardware Structure

43 Constant and high speed adder design using QSD number

system

44 Digit-Serial FIR Filters: Algorithms,

Architectures and a CAD Tool

45 A Common Boolean Logic(CBL) implementation for

modified CSLA

46 High speed vedic multiplier using barrel shifter

47 A new approach to design fault coverage circuit with

efficient hardware utilization for testing applications

48 Design of Parallel Carry-Save Pipelined RSFQ Multiplier

49 Single phase clock distribution using VLSI technology for

A low power

50 Design and implementation of efficient Quaternary

Signed Digit Multiplier

51 High Speed FPGA Implementation of FIR Filter for DSP

Applications

52 High speed Modified Booth Encoder multiplier for signed

and unsigned numbers
 VLSI MAJOR PROJECTS LIST

53 Design and Simulation of 32-Point FFT Using Radix-2

Algorithm for FPGA Implementation

54 Implementation of an Efficient Multiplier based on Vedic

Mathematics Using EDA Tool

55 A Floating-Point Fused Dot-Product Unit

56 Implementation of Power Efficient Vedic Multiplier

57 LUT Optimization for Memory-Based Computation

58 Area Efficient Parallel Fir Digital Filter Structures For

Symmetric Convolutions Based On Fast Fir Algorithm

59 Measurement and Evaluation of Power Analysis

Attacks on Asynchronous S-Box

60 High Speed Booth Encoded Multiplier By

Minimising The Computation Time

61 Design Of Area Optimized Aes 128 Algorithm

Using Mixcolumn Transformation

62 VLSI design Of a Digital Clock Using GALS Technique

63 Efficient Weighted Pattern Generation Technique With

Low Hardware Overhead

64 SCA-FF and SCAh-FF design for single cycle access test

65 Design and Implementation of a High Performance
Multiplier using HDL

66 A VLSI Implementation of Modulo 2​n​-1 Multiplier By

Using Radix-8 Modified Booth Algorithm
 VLSI MAJOR PROJECTS LIST

67 Platform-Independent Customizable UART Soft-Core

68 A Parallel Multiplier - Accumulator Based On Radix – 4

Modified Booth Algorithms by Using Spurious Power
Suppression Technique

69 Using Self-Immunity Technique 64-bit Register File

Immunity Improvement

70 A Novel Nanometric Parity Preserving Reversible Vedic

Multiplier

71 Techniques for Compensating Memory Errors in

JPEG2000

72 High Speed 3d DWT VlSI Architecture for Image

Processing Using Lifting Based Wavelet Transform

73 Low-Cost FIR Filter Designs Based on Faithfully Rounded

Truncated Multiple Constant
Multiplication/Accumulation

74 Pulse Triggered Flip-Flop Design for low power

75 MDC FFT/IFFT Processor With Variable Length for

MIMO-OFDM Systems

76 Faster and Low Power Twin Precision Multiplier

77 A Novel 2​n​ – 2​k​–1 Modulo Adder for

Residue Number System
78 Design and Analysis of 8-bit Low Power Parallel Prefix
VLSI Adder

79 Concurrent Error Detection for Orthogonal Latin Squares

 VLSI MAJOR PROJECTS LIST
Encoders and Syndrome Computation

80 FPGA Implementation of Booth’s and Baugh- Wooley

Multiplier Using Verilog

81 Low-Power Pulse-Triggered Flip-Flop Design

Based on a Signal Feed-Through Scheme

82 Implementation of Area Efficient 16bit Adder

83 Implementation of Area Efficient 16bit Adder

84 Built-In Generation of Functional Broadside Tests Using a

Fixed Hardware Structure

85 Reliable and Higher Throughput Anti-Collision Technique

for RFID UHF Tag

86 Achieving Reduced Area By Multi-Bit Flip Flop Design

87 IMPLEMENTATION OF BUS BRIDGE

BETWEEN AHB AND OCP
88 Design and Implementation of 32 Bit Unsigned Multiplier
Using CLAA and CSLA