usn | zr} 1]o}e|v fs |i |e 10EC129 M.Tech. Degree Examination, January 2011 SoC Design Time: 3 hrs. Max. Marks:100 : Note: Answer any FIVE full questions. i 1 a Define the term SoC. Explain the various factors that are driving the industry to develop i SoC. (0 Maris) ‘What is design productivity gap? What is its effect on time-to-market (TM)? Suggest some ways to bridge the productivity gap. (10 Marks) $2 2 a. Bring out the differences between RISC and CISC processors. (10 Marks) 1 . Based on architecture, classify the processors. Which architecture is more ideal for SoC? is Why? (0 Marks) ¢ ‘i 3 ‘What is cache coherency? Explain MESI protocol for cache coherency. (12 Marks) ' } Design the memory hierarchy for the below given data. t= 10.04 ys, hi = 0.98, ho = 0.9. se Memory level | Access time | Capacity | CosvK Byte i Cache t= 25 ns =$125 ; i Main menu | t= unknown 2=$02 EE Secondary menu | = 4 ms c3=$ 0.0002 5 hi Find t, and ss, if the total access time is 10.04 pis, and total cost is $15,000. (08 Maris) EJ 4 © Whit the need for hardware accelerators in SoC? What are the tradeoffs in implementing 3 these functionalities in software? ‘do Marks) 28 ‘What is DMA? With a neat interface diagram, explain the working of a DMA controller. ti (10 Marks) Bg 5a. Whatare the various data transfer modes? Discuss their advantages and disadvantages. fF (10 Marks) i i Describe the different switching techniques used in NOC. (0 Marks) BS 6 a. Whatare the different data converters used in SoC? Explain any one ADC, used in SoC. (10 Marks) | . What is the need for power management circuits in SoC? What are the different sources of power dissipation? (0 Marks) 5 = + a. Withanest flow chart, explain the high-level verification for an SoC device. (Maria) 3 What are the fundamental issues in hardware-software codesign? (10 Marks) z 8 Write short notes on: a. Moore's law (06 Marks) E DRAM (O7Marts) ESL design flow. (07Marks) *