LIBRARY IEEE;

USE IEEE.STD LOGIC_1164.ALL;

ENTITY CONVERTIDOR IS
PORT(
A: IN STD_LOGIC_VECTOR(1 TO 4);
F: OUT STD_LOGIC_VECTOR(1 TO 4));

ATTRIBUTE PIN NUMBERS OF CONVERTIDOR: ENTITY IS

"A(1):1 A(2):2 A(3):3 A(4):4 ";
& "F(1):17 F(2):18 F(3):19 F(4):20 ";

END CONVERTIDOR;

ARCHITECTURE CONVERTIDOR1 OF CONVERTIDOR IS

Begin
PROCESS(A)
BEGIN
CASE A IS
WHEN "0000" => F<="0000";
WHEN "0001" => F<="0111";
WHEN "0010" => F<="0110";
WHEN "0011" => F<="0101";
WHEN "0100" => F<="0100";
WHEN "0101" => F<="1011";
WHEN "0110" => F<="1010";
WHEN "0111" => F<="1001";
WHEN "1000" => F<="1000";
WHEN OTHERS => F<="1111";
END CASE;
END PROCESS;
END CONVERTIDOR1;