Back End of Line Nanorelays for Ultra-low Power

Monolithic Integrated NEMS-CMOS Circuits

Thesis by
Jesus Javier Lechuga Aranda

In Partial Fulfillment of the Requirements

For the Degree of

Masters of Science

King Abdullah University of Science and Technology, Thuwal,

Kingdom of Saudi Arabia

©May, 2016

Jesus Javier Lechuga Aranda

All Rights Reserved

 2
The thesis of Jesus Javier Lechuga Aranda is approved by the examination committee

Committee Chairperson: Prof. Hossein Fariborzi

Committee Member: Prof. Khaled Nabil Salama
Committee Member: Prof. Mohammad Younis
 3

ABSTRACT

Back End of Line Nanorelays for Ultra-low Power Monolithic

Integrated NEMS-CMOS Circuits

Jesus Javier Lechuga Aranda

Since the introduction of Complementary-Metal-Oxide-Semiconductor (CMOS)
technology, the chip industry has enjoyed many benefits of transistor feature size
scaling, including higher speed and device density and improved energy efficiency.
However, in the recent years, the IC designers have encountered a few roadblocks,
namely reaching the physical limits of scaling and also increased device leakage which
has resulted in a slow-down of supply voltage and power density scaling. Therefore,
there has been an extensive hunt for alternative circuit architectures and switching
devices that can alleviate or eliminate the current crisis in the semiconductor industry.
The Nano-Electro-Mechanical (NEM) relay is a promising alternative switch that
o↵ers zero leakage and abrupt turn-on behaviour. Even though these devices are
intrinsically slower than CMOS transistors, new circuit design techniques tailored for
the electromechanical properties of such devices can be leveraged to design medium-
performance, ultra-low power integrated circuits. In this thesis, we deal with a new
generation of such devices that is built in the back end of line (BEOL) CMOS process
and is an ideal option for full integration with current CMOS transistor technology.
Simulation and verification at the circuit and system level is a critical step in
the design flow of microelectronic circuits, and this is especially important for new
technologies that lack the standard design infrastructure and well-known verification
 4
platforms. Although most of the physical and electrical properties of NEM structures
can be simulated using standard electronic automation software, there is no report of
a reliable behavioural model for NEMS switches that enable large circuit simulations.
In this work, we present an optimised model of a BEOL nanorelay that encompasses
all the electromechanical characteristics of the device and is robust and lightweight
enough for VLSI applications that require simulation of thousands of devices. To
verify the performance of the proposed model, complex logic circuits built exclusively
with relays, and also, hybrid CMOS-NEM circuits are simulated and verified. Finally,
these novel topologies are reviewed and discussed as low-power alternatives to current
CMOS topologies.
 5

ACKNOWLEDGEMENTS

I would like to express my sincere gratitude to my advisor Prof. Hossein Fariborzi

for the continuous support during my research and thesis work. I would like to thank
Prof. Khaled Salama for the opportunity he gave two years ago to join KAUST and
Prof. Mohammad Younis for being part of my thesis defense committee and for their
time. To all my colleagues and friends, I express my sincere gratitude. Distance
cannot stop my family and their support; they are the reason for who I am. And for
the girl I love there are no words to thank you. You have been my support all this
time.
 6

TABLE OF CONTENTS

Title Page 1

Examination Committee Approval 2

Abstract 3

Acknowledgements 5

List of Abbreviations 8

List of Figures 9

List of Tables 11

1 Introduction 12
1.1 Back-end of line nano electro-mechanical relay . . . . . . . . . . . . . 15
1.2 Hybrid NEMS-CMOS Circuits . . . . . . . . . . . . . . . . . . . . . . 21
1.3 Thesis Objetive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.4 Thesis Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2 Back-End-of-Line Nano Relay 24

2.1 The Electromechanical Switches . . . . . . . . . . . . . . . . . . . . . 24
2.2 Basic Electromechanical Model of Nanorelay . . . . . . . . . . . . . . 28

3 Optimised Modelling of BEOL Relay for VLSI Applications 34

3.1 The Motivation for a Reliable Compact Verilog-A Model . . . . . . . 34
3.2 The Relay Physical Model . . . . . . . . . . . . . . . . . . . . . . . . 36
3.3 Model Simulation and Comparison . . . . . . . . . . . . . . . . . . . 48

4 All-Relay and Hybrid NEMS-CMOS Circuit Level Simulation 53

4.1 Circuit Design With Relays . . . . . . . . . . . . . . . . . . . . . . . 53
4.2 Optimised NEMS Logic Design Paradigm . . . . . . . . . . . . . . . . 54
 7
4.3 Logic Circuit Simulations . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.4 Hybrid Power Gating With BEOL Relays . . . . . . . . . . . . . . . 63
4.4.1 Energy-Efficiency With Power Gating . . . . . . . . . . . . . . 64
4.5 Hybrid SRAM Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
4.5.1 6T CMOS SRAM vs 4T-2R Hybrid SRAM cell . . . . . . . . 69

5 Concluding Remarks 74
5.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
5.2 Future Research Work . . . . . . . . . . . . . . . . . . . . . . . . . . 76

References 78

Appendices 84
 8

LIST OF ABBREVIATIONS

BEOL Back End of Line.

CMOS Complementary Metal Oxide Semiconductor.

FEM Finite Element Method.

MEMS Micro Electro Mechanical System.

NEMS Nano Electro Mechanical System.

VLSI Very Large Scale Integrated.

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LIST OF FIGURES

1.1 Power Trend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

1.2 Limits of Parallelism . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.3 Minimum energy per operation . . . . . . . . . . . . . . . . . . . . . 15
1.4 Electrical response of a electro-mechanical switch . . . . . . . . . . . 16
1.5 Simplest electrostatic switch design . . . . . . . . . . . . . . . . . . . 17
1.6 BEOL Six Terminal Relay . . . . . . . . . . . . . . . . . . . . . . . . 21

2.1 Intel 14 nm BEOl stack with air gap technology . . . . . . . . . . . . 24

2.2 Serpentine BEOL Six Terminal Relay . . . . . . . . . . . . . . . . . . 25
2.3 Pull-in voltage prediction for scaling BEOL relays . . . . . . . . . . . 27
2.4 Proposed Six Terminal BEOL relay . . . . . . . . . . . . . . . . . . . 28
2.5 Implementation of Six and four terminal BEOL vertical relays . . . . 29
2.6 Parallel plate capacitor model . . . . . . . . . . . . . . . . . . . . . . 30
2.7 Hysteresis behaviour of the NEM relay . . . . . . . . . . . . . . . . . 31
2.8 Pull-in Voltage representation for the BEOL Relay . . . . . . . . . . 33

3.1 MEMS/NEMS design Flow . . . . . . . . . . . . . . . . . . . . . . . 36

3.2 6T BEOL relay to be described as a Verilog-A behavioural model . . 38
3.3 Parametrised model for Verilog-A implementation . . . . . . . . . . . 39
3.4 Structure approximation for Verilo-A implementation . . . . . . . . . 39
3.5 Force contribution by every electrode and approximated force for the
Verilog-A implementation . . . . . . . . . . . . . . . . . . . . . . . . 42
3.6 Stop force Verilog-A implementation . . . . . . . . . . . . . . . . . . 43
3.7 Smooth force calculation Verilog-A code implementation . . . . . . . 44
3.8 State space representation of the dynamics of the beam in Verilog-A . 45
3.9 Variable resistance between source and drain for Verilog-A model . . 46
3.10 Simple circuit for Verilog-A . . . . . . . . . . . . . . . . . . . . . . . 47
3.11 Algorithm used for the Verilog-A code implementation . . . . . . . . 48
3.12 Comparison of the transient response of the BEOL relay in MEMS+
and the Verilog-A model . . . . . . . . . . . . . . . . . . . . . . . . . 49
 10
3.13 Comparison of the transient response of the BEOL relay in MEMS+
and the Verilog-A model . . . . . . . . . . . . . . . . . . . . . . . . . 50

4.1 Comparison between CMOS and NEMS circuit topology . . . . . . . 55

4.2 1-Bit Full-Adder built with 6T BEOL relays . . . . . . . . . . . . . . 57
4.3 2-Bit Adder block diagram . . . . . . . . . . . . . . . . . . . . . . . . 58
4.4 16-Bit Adder built with 6T BEOL relays . . . . . . . . . . . . . . . . 58
4.5 Waveforms graph for a 2-bit Adder . . . . . . . . . . . . . . . . . . . 59
4.6 Waveforms graph for a 2-bit Adder . . . . . . . . . . . . . . . . . . . 59
4.7 Waveform simulation for a 7:3 compressor . . . . . . . . . . . . . . . 60
4.8 Input vector waveforms for a 16-bit Adder . . . . . . . . . . . . . . . 60
4.9 Output vector waveforms for a 16-bit Adder . . . . . . . . . . . . . . 61
4.10 6 Bit Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
4.11 6 Bit Multiplier output vecetors . . . . . . . . . . . . . . . . . . . . . 62
4.12 CMOS vs Relay implementation of Power Gating . . . . . . . . . . . 64
4.13 CMOS vs Relay implementation of Power Gating with circuit elements 65
4.14 6T CMOS SRAM and 4T-2N hybrid SRAM . . . . . . . . . . . . . . 70
4.15 Butterfly plot for the CMOS and Hybrid SRAM cells . . . . . . . . . 71
4.16 Optimised Signal to noise margin of the Hybrid SRAM cell . . . . . . 72
4.17 Layout for 4T-2R hybrid SRAM cell . . . . . . . . . . . . . . . . . . 72
4.18 Simulation of WRITE and READ operations of a Hybrid CMOS-NEM
SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
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LIST OF TABLES

2.1 Projected minimum half-pitch () [1] . . . . . . . . . . . . . . . . . . 26

3.1 Comparison of the DC and Transient time simulations of MEMS+ and

Verilog-a models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.2 Mechanical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.3 Accuracy of proposed model . . . . . . . . . . . . . . . . . . . . . . . 51

4.1 Input vectors for 6 Bit mulitplier . . . . . . . . . . . . . . . . . . . . 63

4.2 CMOS technology parameters for the standard PTM [2] . . . . . . . 66
 12

Chapter 1

Introduction

Moore’s law prediction for the increment of transistors in an integrated circuit proved
to be accurate for many decades. By doubling the number of transistors in a sin-
gle chip every two years, the semiconductor industry has been able to improve the
performance and efficiency of Complementary-Metal-Oxide-Semiconductors (CMOS)
integrated circuits. Nevertheless, recently there has been a deceleration of Moores
law. Newer, smaller technology nodes, especially below 65 nm, show an increased
power density. Reasons like the inherent challenges of MOS devices such subthresh-
old leakage and the existing limits of supply and threshold voltages are the cause of
this augmentation in power consumption. There are billions of transistors in modern
electronics, all of them leak; ergo, the reason why modern devices are getting more
power-hungry and batteries do not endure the energy requirements. Low-power inte-
grated circuits is, therefore, a major need in modern electronics devices. For example,
technology gadgets are getting smaller every year, their power increases with every
new generation, but there is a problem with power consumption; batteries run out
very fast and processing units scorch when maximum performance is required.
For instance, the trend for the static and dynamic power dissipation of modern
consumer portable devices is to increase every year, meanwhile the industry require-
ment for low-power electronics demands that the power stay constant. In a few years,
circuits designers will have the energy budget to activate only a fraction of the tran-
 13

Figure 1.1: SOC Consumer Portable Power Trend [1].

sistors in a integrated circuit if they were to stay within the low-power specifications
dictated by the industry. The trend describing the projection of power increment by
the International Technology Roadmap for Semiconductors is shown in Figure 1.1
[1]. It can be seen that, ideally, the power should stay constant throughout the past
of time, but scaling the transistors is leading to more power consumption.
Proposed system architectures such as parallel processing alleviate some of the
problems of CMOS circuits and systems. The main principle of parallelism is that if
a CMOS circuit runs slower it will permit the reduction of the energy per operation
of functional blocks. However there is a well-defined minimum energy per operation
for each functional block in a integrated circuit[3] (Figure 1.3). Once we reach the
minimum energy per operation, slowing down each block further does not bring more
energy savings, thus more parallelism becomes inefficient as depicted in Figure 1.2.
As a result, an extensive hunt for beyond CMOS devices has been going on in the
past decade.
In the past years a lot of interest has been shown in micro and nano electro-
 14

Figure 1.2: The limits of parallelism [3]

mechanical relays (MEMS/NEMS) as an alternative for CMOS transistors and com-

plement to CMOS integrated circuits. These devices are simple electrostatic-actuated
switches, with zero current leakage and abrupt turn-on behaviour that are inspired
in an older technology, the main building blocks of the first reported computers; the
electro-mechanic magnetic relay. Konrad Zuses Z3 is one of the first programmable
computers, built with 2000 electro-mechanical relays, the machine could execute fixed
sequences of floating point arithmetical operations [5]. Even though it demonstrated
the capabilities of relay-based computing, the Z3 and its main component, the mag-
netic relay, did not stand the test of time since it was rapidly outperformed by com-
puters built with vacuum tubes and transistors [6]. Compared to its new competitors,
the relay was bulky, slow, power hungry and its miniaturization involved technical
challenges hard to solve with the technology available at that time. Nonetheless the
fabrication techniques have evolved a lot since then, allowing chip makers to shrink
billion of transistors in a single chip and to fabricate moveable mechanical struc-
tures in silicon wafers, hence making possible the construction of micro and nano
electromechanical relays. Although these new miniature switches inherit some of the
disadvantages shown by older relays like slow response and mechanical wear, the
 15

Figure 1.3: Minimum energy per operation [4]

MEMS/NEMS can be engineered to exhibit a reduced energy per operation, even

comparable to modern CMOS transistors; and more important, they do not leak
current when they are o↵. These assets make the MEMS/NEMS relays ideal for
ultra-low power applications [7]. The challenge now is to understand their behaviour
in the micro and nano scale regime, further to analyze its integration into modern
very-large-scale integrated circuits (VLSI).

1.1 Back-end of line nano electro-mechanical relay

MEMS and NEMS relays are electrostatic-actuated structures that have the qualities
of a near-ideal switch. The fundamental behaviour of relay switches is simple; after
applying a voltage di↵erence between two terminals, a physical electrical circuit can
be opened and closed. Three terminal devices are the simplest MEM relays that can
be used in logic circuits. They are built by manufacturing one fixed electrode known
as gate and arranging a parallel moveable structure source separated by an air cavity,
the physical separation gap that is formed when the relay is in the o↵-state prevents
any current to leak, showing an o↵-state currents as small as 1pA in some of the
proposed designs [8]. The typical electrical response of a electro-mechanical switch is
 16
shown in Figure 1.4.

Figure 1.4: Electrical response of a electro-mechanical switch

The basic actuation of the switch is simple, when a voltage is applied, the moveable
structure is moved towards the fixed electrode drain closing the electrical circuit and
allowing conduction, the voltage required for this action is called pull-in voltage (Vpi ).
When the voltage is removed the source is returned to the original position, breaking
the conduction. The simplest electro-mechanical switch built is shown in Figure 1.5.
The first micro-electro-mechanical relay was demonstrated by Petersen [5] . It
was described as a device between a traditional transistor and an electromechanical
relay with a high o↵-to on-state impedance ratio and all-metal conduction paths,
suitable for alternate current switching arrays. Inspired by this first device, various
types of relays have been developed in the following years exploring di↵erent designs,
materials and actuation mechanisms like thermal, piezoelectric-e↵ect or magnetic.
To qualify as a candidate for low-power computing, the device should possess a
high integration density, fast switching speed and low operational voltage. Thermal
and magnetic actuators are slow and big, even if they are implemented using the cur-
rent fabrication techniques [3] . Hence they fail to achieve the first two characteristics,
making them unacceptable for digital computing. On the other hand piezoelectric
switches can accomplish a good switching speed and operational voltages of around
0.5V , some of the lowest operational voltages reported till date. Their device foot-
 17

Figure 1.5: Simplest electrostatic switch design

print is large (around 57m2 ) and their scalability is poor, excluding their candidature
as a switch for VLSI applications [9].
Reported electrostatic actuated switches are di↵erent in design, materials and
number of terminals, being three terminals the least for a practical logic switch. The
first nanorelay for logic application was built using top-down fabrication techniques by
suspending a cantilever beam on top of a gate and drain electrode. The as-fabricated
contact gap was 40 nm and the structure was immersed in oil trying to reduce the
pull-in voltage, reporting actuation voltages of 4 V to 8 V in oil [10]. Four terminals
and six terminals out-of-plane actuation relays have been reported by the research
group at UC Berkeley. These logic relay are composed of a moveable polycrystalline
silicon-germanium thin plate suspended over a fixed electrode, a conductive strip of
 18
metal is attached to the moveable plate to allow conduction. The design proved to
have a stable contact resistance during more than 106 cycles and a low operational
voltage down to 1V [11].
Recently, research groups in Europe have demonstrated 3T and 4T curved can-
tilever relays coated with amorphous carbon (a-C). This design is intended to reduce
mechanical strain, wear,contact resistance and to lower the hysteresis [12]. The prin-
cipal characteristics of this relay are a pull-in voltage of 7V , a contact resistance of
15k and the possibility to further reduce the pull-in voltage with body bias voltage.
The device foot print area was reported as 15m2 .
Silicon carbide (SiC) relays have been demonstrated as potential logic switches
for harsh environments, like outer-space and military applications . With a footprint
of 1m2 and separation gap of 100 nm the relay reported actuation voltages from 11
V to 15 V with and endurance of around 14,000 cycles at an elevated temperature of
500 C. Logic implementation of simple gates were also demonstrated using this relay
[13].
The National University of Singapore have demonstrated a nanorelays with torsion
bars engineered to work in non-volatile memory circuit. The footprint for this device
is around 9m2 with a fabricated gap between 80 nm and 100 nm. The operational
voltages for this relay were reported as 5.5V . The the durability of the device showed
to be poor by failing after only few switching cycles [14].
Laterally actuated relays have also been reported by Sandia National Laboratories,
with fabricated gaps between 20 nm and 70 nm. A pull-in voltage was demonstrated
to be 4 V or higher with an endurance of more than 106 cycles. The fabrication was
challenged by poor manufacturing yield [15]. Recently, other laterally actuated relays
with as-fabricated gaps as small as 5 nm have been demonstrated and fabricated by
[ccc] showing the possibility to obtain even smaller gaps needed to reduce actuation
voltages below 1 V [16].
 19
The electro-mechanical relays reported during the last years have proved the can-
didacy of nanorelays as an alternative switching device, but there is still some im-
provement needed to achieve a suitable switch for low-power electronics. Most of the
discussed designs have an outsized device footprint compared to CMOS transistors,
high switching voltages, poor fabrication yield and bad endurance; not mentioning
the elaborated fabrication techniques used to achieve their integration in the standard
CMOS process.
NEMS switches need to overcome many challenges before being considered as
practical devices for low-power logic circuits. Some of the characteristics that we
want to have in a NEM relay are:

• High manufacturing yield with enough support to achieve high volume produc-
tion in a CMOS-compatible process

• Low pull-in voltages that assure low switching power

• Reiterate behaviour with constant OFF/ON resistance over the life-cycle of the
switch

• Fast and reliable switching mechanism with an endurance around 3x101 4 switch-
ing cycles. To assure a life expectancy comparable to a CMOS transistor.

• Reduced number of extra steps as well as minimum introduction of external

materials to standard CMOS process.

To achieve these characteristics, the constant participation of various disciplines

like mechanical engineering, material science and integration engineering is required.
Integration with current CMOS process is still poor for most of the proposed de-
signs since they involve post-processing steps, even being CMOS-compatible. Hence,
fabrication of these proposals as a complement or replacement for complementary
 20
oxide transistors is expensive and very elaborated. Thesis investigates a fully CMOS-
compatible vertical nano relay design as the best relay alternative for implementation
in current VLSI circuits. This nano relay switch is a device constructed with the metal
interconnects available in the back-end-of-line (BEOL) process first introduced in [17]
as seen in Fig. 1.6. Such implementation guarantees a compact, natural solution for
the monolithic integration of CMOS and NEMS with no extra process steps, making
the BEOL-relay a significant improvement in CMOS-integration and fabrication over
the others designs. The design can take advantage of the multiple metals layers and
air gap technology in the back-end process to assemble a moveable beam and fixed
electrodes, the continuous wire and gap scaling assures a small device footprint and
high integration density. The pull-in voltage, mechanical delay and adhesion forces
can be tuned by selecting the BEOL stack material, number of metals used and sepa-
ration gaps. With the versatility of design parameters, the proposed relay can achieve
optimised behaviours for di↵erent applications.
 21

Figure 1.6: Close up of a BEOL relay with a CMOS transistor (FEOL). Metal 1 acts
as a mechanical anchor, metals 2-4 form the beam and actuation layers, metals 5
contain the channel, source and drain. Between Metal 4 and 5 exists a Intra-Metal-
Dielectric. Adapted from [17]

1.2 Hybrid NEMS-CMOS Circuits

NEMS relays have outstanding switching properties that can be employed to produce
ultra-low power integrated circuits. But we can not simply replace NEMS relays with
transistors; new circuit topologies have to be created to reach the objective of ultra-
low power electronics. The primary goal is to design new system architectures that
comply with the industry requirements of ultra-low power budget plus the ability
to follow the scaling trend predicted for the CMOS transistors. As we reviewed in
previous sections, relays can behave as an electrical switch using only a fraction of the
operational power of their equivalent CMOS counterparts. Hence, only-relay circuits
can be elaborated and optimised to produce logic blocks to replace CMOS-based
 22
equivalents. The main two drawbacks of nanorelays: their switching time and large
device footprint, have to be taken as optimisation variables to design reliable only-
relay circuits. In simple words, we want a circuits with small delay with fewer devices
that can compete with CMOS-based designs.
Another solution that shows promising advantages over CMOS and NEMS relay-
based circuits is the hybrid NEMS-CMOS architecture [18] [19]. Hybrid NEMS-
CMOS circuits aim to solve the potential disadvantages of the other reported schemes.
By taking advantage of the speed and analog operation capability of CMOS transistors
and the zero current leakage of nanorelays novel circuits designs can be created to be
implemented in VLSI applications. Circuit techniques and architectures like power
gating, hybrid NEM-CMOS memories are some of the potential solutions for low-
power electronics [20] [21].
Circuit simulation is a mandatory step for the exploration and evaluation of this
new circuit topology. There have not been reports of reliable models that can be
simulated in VLSI. Thus, a reliable device with all the electromechanical properties
of the nanorelay model is needed for simulation or large complex circuits.

1.3 Thesis Objetive

The main challenge of this work has been to make the model simple and robust
enough for large circuit simulations, while making sure that it covers all the major
electrical and mechanical properties of the device and can give a good approximation
of the behaviour of the device in a mixed-signal environment. The absence of such
a model in the past years has made simulation and verification of NEM relay based
circuits virtually impossible. A second aim is to explore di↵erent circuit architectures
of hybrid NEM-CMOS that can achieve low-power operation and test them using the
available mixed-signal environment simulation software.
 23
1.4 Thesis Outline

The rest of this thesis is organized as follows:

Chapter 2 discusses the electromechanical relays as a potential switching alterna-
tive. A simplified analysis of the physics and e↵ects governing a conventional electro-
static switch is presented. The section examines the concerns and challenges in the
construction and fabrication of these devices with the current fabrication technology.
Chapter 3 elaborates in the modeling and implementation of a behavioral model
intended for circuit simulation. It explains the practical approximations and algo-
rithm implementation for the hardware description language code. With the e↵ort to
provide circuit designers a reliable working, the chapter concludes with the description
of the simplification of a Verilog-a model for VSLI simulations.
Chapter 4 presents a review of available circuit-design techniques for relays. Show-
ing simple and complex logic implementations of widely used logic blocks and the
novel hybrid designs. The section discusses the current trends in delay optimisa-
tion techniques for all-relay-based and hybrid relay-CMOS circuits. With the goal to
present the advantages of the combination of both technologies.
Chapter 5 concludes with a summary of the completed work, the trend of NEMS-
CMOS circuit topologies and the future work needed to elaborate simplified models
of NEMS relays for VLSI circuit simulations.
 24

Chapter 2

Back-End-of-Line Nano Relay

2.1 The Electromechanical Switches

Implementing vertical relays in the back-end of line process is the best option for
the monolithic integration of electrostatic switches and CMOS transistors [17]. As
discussed in the previous chapter, most of the other relay designs comprise fabrication
and integration challenges that the BEOL relay do not. This relay is constructed
directly on the BEOL stack of current CMOS foundry processes. The wires and vias
in the stack supplements with the air-gap technology [22] to assemble a moveable
beam and electrode plates (Fig. 2.1). In this way, we assure that none or minimal
extra steps are needed for the integration of this technology which, at the end, makes
the construction of these devices a natural step in a standard foundry process [17].

Figure 2.1: a) Intel 14 nm BEOL stack. (b) Air gap technology

 25
Xu et al. proposed the first vertical BEOL relay. This structure comprises a
”serpentine” model constructed in the first five metals in a back-end-of-line stack.
Where the first metal acts as the mechanical anchor and access the gate electrode.
Metals two to four make the moveable beam and actuation plates. Metal five allocates
the contact channel and the source and drain connections. Between metal four and
five, an intra-metal dielectric is placed to isolate the channel from the rest of the
moveable beam. Two electrodes composed of metal two to four are fixed parallel to
the movable wires. The size of the relay and overall arrangement of the BEOL relay
is shown in Fig. 2.2 , where  is the minimum feature size dictated by the half-pitch
(HP) of the used technology node.

Figure 2.2: (a) Close up of a BEOL relay (Opacity of body and contact plates is
lowered to show the structure of the beam). (b) Side view of the relay showing the
intra-metal dielectric. (c) Top view of the relay showing fabrication dimensions and
the smallest feature size  . Figure adapted from [17].

The projected minimum half-pitch reduction over time is a prediction made by

the International Technology Roadmap for Semiconductors (ITRS). The prediction
states that as manufacturing technology advances, the lithography resolution of the
 26

Table 2.1: Projected minimum half-pitch () [1]

Year 2015 2017 2019 2021 2023 2025
Half pitch,  (nm) 25.3 20.1 15.9 12.6 10 7.09

CMOS process will be able to manufacture smaller features every two years allowing
the NEM relays to scale. This minimum feature reduction is a great ally to even
further reduce pull-in voltages and to increase integration density. Table 2.1 displays
the scaling prediction for .
This proposed relay can achieve lower pull-in voltages as the  decreases, this is
achieved by the small actuation gap of the structure (Fig 2.3). Xu et al. guarantee
pull-in voltages less than 1V for relays with a footprint less than 0.1 µm2 . The
”serpentine” architecture of this relay may jeopardize its mechanical stability. The
movement or the beam relies on the bending and torsion of the first via. Consequently,
all the stress is concentrated on this node, increasing the risk of failure. The contact
between the channel and source and drain connections does not occur at the same
time nor with the same contact area. Vibrations between the channel and the electric
connections during the contact might lead to welding of the structure, increased
resistance or incomplete contact.
The low spring constant provided by the single via connected to the first metal
(anchor) compromises the performance of the relay. Low-actuation voltages can be
achieved by lowering the structural sti↵ness of relay structures. However, in [23]
was demonstrated that, contrary to popular belief, the spring constant of nanorelays
should be relatively large to obtain a superior energy-delay performance.
 27

Figure 2.3: Pull-in voltage prediction for scaling relays.

In this thesis we propose a similar design to the one introduced in [17]. Instead of
using the ”serpentine” movable beam, a ladder-type beam is formed with the BEOL
wires and vias. The ladder exercises two vias distributed evenly along the length of
the wires, this to add support and even moment distribution throughout the wires.
This structure forces the beam to have only one degree of freedom, removing the
torsion stress from the via and leaving only the bending strain. Such arrangement
tries to make the relay bear more switching cycles due to the lowered rotation fatigue
on the via and to increase the energy-delay performance [23]. Figure 2.4 shows the
NEM relay with new proposed configuration, all dimensions are a function of the
smallest feature size  , described by the minimum technology node half-pitch [17].
Four terminal (4T) and six terminal (6T) relays can be arranged by adding or
removing an pair or source (S) and drain (D) connections and a body (B) plate as
seen in Figure 2.5. The selection between 4T and 6T relays is totally dependent on the
required characteristics of the design and circuit topology. In [24] was demonstrated
that by the count of total relays in a logic circuit could be lowered by choosing 6T
over 4T relays.
Di↵erent switching behaviours can be obtained by tweaking the design of the relay
and the di↵erent design parameters. The design flow of nanorelays starts by selecting
 28

Figure 2.4: Proposed Six Terminal (6T) BEOL relay.  is the minimum feature size
of the used technology node

the pull-in voltage and adhesion force required for a particular behaviour. Followed
by an area optimisation method to achieve the highest integration density for low
operational energy and the necessary device parameters. The design variables are
the number of metal layers used, the length of the wires (which dictate the over-
all actuation area). The BEOL stack material, typically aluminium (AL) or copper
(CU) modifies the mechanical properties of the stack and therefore its overall me-
chanical response. The description of the physical contribution of these variables and
optimisation method is explained later in the chapter.

2.2 Basic Electromechanical Model of Nanorelay

The relay can be represented as a mass-spring-damper system where the force is

exerted by a variable parallel plate capacitor, a graphical representation of the system
is shown in Fig. 2.8. To analyze the dynamics of such system we can recall Newton’s
second law of motion. The second order system representing this law describes the
 29

Figure 2.5: Implementation of Six and four terminal BEOL vertical relays. By
adding/removing a couple of drain and source electrodes and a body electrode 4T
and 6T relays can be fashioned in the same manner.

acceleration of an object as a result of an acting force and is defined by the equation:

mÿ + b ẏ + ky = Felec (y) (2.1)

Where y describes, the displacement of the wire plate by the influence of an

electrostatic force Felec (y), b and k represent the damping coefficient and the e↵ective
spring constant respectively. The active inertial mass of the moving mass is denoted
by m. The acting Felec (y) is the result of a voltage (Vgb applied between the gate and
body electrodes, denoted by:

"o Aov Vgb2

Felec = (2.2)
2(go y)2

where "o is the permittivity of air, (go y) represents the displacement of the plate
about the initial gap. Vgb2 is the applied voltage and Aov is the acting overlap area.
 30

Figure 2.6: Representation of the parallel plate capacitor model

For the BEOL relay, the practical Aov is defined by the force contribution of each
wire-plate charged with a voltage i.e. each di↵erent metal contributes in a di↵erent
manner to the overall area (see Chapter 3.X). The restoring force on the system is
dictated by the spring force:

Fspring = ky = k(go y) (2.3)

Where k is the spring constant and can be obtained by beam theory analysis
[25] . The correspondent spring constant for any system is formulated taking into
consideration the overall shape of the flexure parts of the design. For a BEOL relay,
the spring constant is obtained by analysing the mechanical node that exhibits most
of the compression and tension strains [26] in this case, the metalic via. The spring
constant is described by the cross-section profile of the via and is obtained by:

EI
kround = (2.4)
l4

⇡r4
I= (2.5)
4

Where E is the Young modulus that is dependent of material of the interconnects.

 31
I is the second moment of inertia for a cantilever with a round profile, r is the radius
and l is the beam e↵ective length where the force exerts the bending moment [26].
For the BEOL relay l and r can be described as a function of the smallest feature .

Figure 2.7: Hysteresis behaviour of the NEM relay. We can see that we have a
Vpi = 3.65 and a Vpo = 2.67. The abrupt displacement happens at 2g3o

An important parameter for NEM relays is the pull-in voltage (Vpi ), which dictates
a sharp displacement from the initial position to the turn-on state, this happens at
a fraction of the initial separation gap go . As we can see in Fig. 2.7 the relays shows
2go
an abrupt change in the displacement at 3
, the voltage at which this happens is the
Vpi . The pull-in voltage can be represented by:

s
8kgo3
Vpi = (2.6)
27"o Aov

The voltage to turn o↵ the relay is usually less than the Vpi . To release the
structure, the spring force has to overcome the Felec and the adhesion force Fadhesion .
 32
The adhesion force in MEMS and NEMS is described by the attraction forces between
neighbouring particles. Described by the Casimir and Van der Waals forces, dominant
forces in the nanometric regime. For separation gaps in the order of ten on nanometers
Van der Waals force represent the primary contribution adhesion force in NEMS, while
Casimir forces take e↵ect in larger separation gaps [27] [26]. The Van der Waals forces
per unit area can be modelled as:

H
Fvdw = (2.7)
6(go y)3
19
Where H is the Hamaker constant, for Al is found to be 3.6x10 [28]. Like the
Felec , the adhesion force becomes more dominant as the plates reduce their separation
distance [29]. The Fvdw can reach magnitudes that can surpass the restoring strength
and stick the plates together. This phenomenon can be engineered to obtain di↵erent
behaviours in the relay that can be used to fabricate devices with di↵erent properties,
memories as an example [30]. In such way the turn-o↵ voltage occurs when the
restoring force is greater than Fadhesion and Felec . The release voltage can be expressed
by:

s
2(kgd Fadhesion )(go gd )2
Vrelease = (2.8)
"o Aov

For go gd being the distance di↵erence between the initial and the contact gap.
The di↵erence separating the Vrelease and the Vpi creates a hysteresis behaviour, shown
in Fig. 2.7.
 33

Figure 2.8: Pull-in Voltage representation for the BEOL Relay.

 34

Chapter 3

Optimised Modelling of BEOL

Relay for VLSI Applications

In this chapter we describe the process followed for the construction of a compact
behavioural model for the BEOL vertical relay. The process carried to describe the
dynamics of the electrostatic switch is similar to the ones found on the literature
presented. This model is constructed by simplifying the physical properties and
smoothing the equations trying to avoid complex assignments. The Verilog-A model
is coded following the design guidelines provided by CADENCE [31]. By avoiding
extra state space variables and complex contributions, the nodal analysis made by the
CADENCE simulator ”SPECTRE” can be simplified to few and simple equations that
yield fast simulation times and yet accurate description of the dynamics and electrical
behaviour of the vertical relay.

3.1 The Motivation for a Reliable Compact Verilog-

A Model

The design flow for NEMS relay devices usually follows a systematized path as seen
in Fig. 3.1 Starting with the dynamics analysis of the mechanical model and its elec-
 35
trical response. Followed by device-level FEM and SPICE simulations and finishing
with a prototype fabrication and characterization. There is a need of an extra step
for creating a reliable compact model for VLSI simulation. Simple circuit simulations
are frequently included in device proposals reports using complex physical models
to analyze the behaviour of the devices in a mixed-signal environment. Descrip-
tive behavioural models are built using the device-derived physical equations and
SPICE models and plugged into a standard Electronic Design Automation (EDA)
software in the form of a descriptive code. The compiled behavioural models top
in detail and accuracy but often su↵er from long simulation times and convergence
problems. Hence complex circuits simulations is hardly achieved with these mod-
els. FEM-MEMS specialized software like Intellisuite and Coventor MEMS+ have
introduced new functions to their software packages for their integration with com-
mercial EDA software. MEMS models built in the FEM-software environment can
be exported to a SPICE simulator to verify the integrated circuit design and be able
to predict yield sensitivity to manufacturing variations [32]. This integration allows
fast and accurate simulation of the devices in a mixed-signal environment. Never-
theless, this functionality is not intended for large and complex circuits and requires
constant communication between the commercial software and the circuit simulator,
constraining in this way the interchangeability of the models. Reduce-order-models
(ROM) can also be obtained by these software, providing a simple Verilog-a model
calculated around an operational point of selected no-contact MEMS structures [32].
The obtained files can be used for circuit simulation and achieve faster simulations
times. However, NEMS switches, di↵erently from resonators and other no-contact
structures, cannot be reduced around and operation point since the contact inter-
actions leads to nonlinearities and convergence issues [33]. Simulations derived by
FEM analysis are very accurate and fast but the constant need of specialised soft-
ware reduces the availability and interchangeability of device models. Even though
 36
analysing single devices in a circuit simulator environment can give the designer a
very good approximation about the behaviour of the electro-mechanical device in a
mixed-signal environment, the need for complex circuit analysis along with typical
CMOS transistors is a growing concern and cannot be accomplished by the present
models.

Figure 3.1: MEMS/NEMS design Flow and the insertion of a new step for the creation
of a compact model for VLSI applications.

3.2 The Relay Physical Model

Behavioural Verilog-A models have been elaborated for di↵erent in plane NEM switches
structures in [34] and [35]. These behavioural models are accurate descriptions of the
switches and can simulate moderately complex circuits. Nevertheless, they su↵er
from convergence issues when the number of relays are increased . An improved
algorithm for the same model in [34] can be found in [36] allowing to increase the
number of relays per circuit of 22 NEM devices to 192 with less than 6% margin error
and no issues during the simulation. The task to build a reliable model for VLSI
implementation is an ongoing e↵ort and needed step to add in the NEMS design
flow. Simplicity and good accuracy is needed to accomplish fast simulations with
 37
no convergence issues. The BEOL relay treated in this thesis is a vertical structure
with a complex structure. No studies have been carried on this type of structures
before. Since the approach for building models of horizontal relays follows the same
flow for RF MEMS and other MEMS switches the modelling and approximations
for the Verilog-A model for the BEOL are the same for horizontal devices with the
appropriate modifications. This chapter continues with the discussion of the relay
physical equations and their implementation in the Verilog-A language along with
the simulation and comparison with the Coventor MEMS+ software implementation.
Inversely to typical NEMS devices, the movement of the BEOL vertical relay is on
the x-y plane and not in the z-x or z-y plane like other proposed systems [Figure
3]. Nevertheless, the static and dynamic analysis is carried in similar manner due to
the negligible orientation e↵ects. E↵ects like Van Der Waals forces and contact force
are approximated using reported models from di↵erent MEMS structures. Due to
the nano-scale gaps and device construction, the film squeeze damping is neglected.
It should be noted that the model for VLSI integration, as stated before, does not
have to be as accurate as the FEM-derived simulation. The lumped model should
provide enough physical representation of the relay pull-in voltage, mechanical delay
and energy consumption to be used for complex circuit simulation and provide a good
accuracy and fast simulation time.
The BEOL structure is shown in Figure 3.2.The relay is built using the wires and
vias of standard CMOS process. The fist metal is used as the mechanical anchor and
electrical input port noted as gate (g). Metal 2 to 3 compromises the moveable beam
and the actuation electrodes noted as body (b). In metal 5 the channel shuttle and the
source (sr) and drain (dr) ports can be found. The minimal gap achievable is denoted
by  which is the minimum feature size and is dictated by the minimum half-pitch
technology node as reviewed in Chapter 1. The via between metal 4 and metal 5 is
formed y an intra-metal dielectric (IMD) which isolates the channel from the gate [5].
 38
The material for the structure is technology dependent, for this analysis aluminium
(Al) is used. The Verilog-A model is parametrised model, so all the measurements
are declared in the code as a function of the minimum size feature  as seen in Fig 3.3

Figure 3.2: 6T BEOL relay to be described as a Verilog-A behavioural model.

For the Verilog-A implementation and to avoid complex moment calculations in-
volved in the original structure, the device can be approximated to a one-dimensional
one-side fixed cantilever beam with as distributed total mass. Thus the model can
be approximated to two round cantilevers with rigid massless bars connecting the
structure. Figure 3.4 shows the original structure with the electrode plates and the
approximated structure, where the electrode plates have been replaced by massless
beams.
The gap between the contact and beam is the minimum feature size and the total
expected displacement from the beam (gd ). Hence, the structure is coded to restrict
the movement of the beam within the range of gd < y < gd . From beam theory, the
maximum deflection (ym ) and slope ( ) of a uniform density beam is given by:

F l3
ym = (3.1)
3EI
 39

Figure 3.3: 6T BEOL relay parametrised model for Verilog-A implementation

Figure 3.4: 6T BEOL relay structure approximation for Verilog-A implementation

F L2
= (3.2)
2EI

Where F is the uniaxial applied force, l is the distance to where the force is applied,
E is the young modulus and I is second moment of inertia. From these equations
we can see that the spring constant (k) for the beam is the ratio of displacement to
force:

3EI
k= (3.3)
l3
 40
The second moment of inertia (moment of area) is a geometry-dependent param-
eter and it is defined by the transversal cross-section profile. For our structure we
have a round cantilever (via) profile, from statics we can find that the moment of
inertia and the spring constant is [25]

⇡4 3E ⇡ 4
Icircle = kef f = 3 ⇤ (3.4)
4 l 4

3E ⇡r4
kef f = ⇤ (3.5)
l3 4

The e↵ective spring constant for the BEOL beam can be found by adding the
spring constant from the two round-profile cantilever beams formed by the first via
layer and seen in Figure 3.3 [29]. The spring constant was also compared to simula-
tions in COMSOL and MEMS+. The di↵erence between the calculated and simulated
spring constant was of 4%. The total mass of the structure is integrated along the
length and distributed throughout the two cantilever beams that are connected by
vias in the metals 2,3 and 4. From beam theory we can find that the e↵ective mass
of a cantilever beam is given by:

k
mef f = (3.6)
(f0 2⇡)2

where f0 is the first natural frequency of the structure as extracted from MEMS+
and COMSOL simulations. For a 21nm feature size relay it was found to be 743M Hz.
Thus, all the mass of the cantilever is distributed along two round cantilevers of total
mass = mef f that are connected by massless unit wires. So the system is considered
only as bending cantilevers, the wires area that form the electrodes is only used for
capacitance and force calculations.
We can model the relay as a damped mass-spring system, which is actuated by
a non-linear electrostatic force Fe (y, V ) that is dependent on the voltage and beam
 41
displacement and a contact force Fc (y) dependent on the material penetration and
physical-chemical e↵ects. The motion of the beam is forced to be one dimensional to
simplified the calculations and avoid extra matrices in the simulations. The Newtons
law of motion for the free mass is expressed by:

mÿ + b ẏ + ky = Felec (y, V ) + Fc (y) (3.7)

When the capacitors formed between the wires on the beam and the body elec-
trodes are charged the electrostatic force Fe (y, V ) is exerted on the beam. The elec-
trostatic force Fe (y, V ) is the gradient of the potential energy that is stored in the
capacitor. The electrostatic force can be expressed with the first order simplification
[29] given by:

@(CV 2 (t)) "o AV 2

Felec (y, V ) = = ĝ (3.8)
2@go 2go2

Where "o is the vacuum permittivity, A is the overlap area of the electrode, go
is the initial separation gap and is the directional vector where the force is exerted
ĝ. From the system geometry we can see that three di↵erent electrostatic forces are
actuating on the beam, each one for each electrode. The Felec (y, V ) behaves in a non-
linear manner with respect to the separation gap. The first order simplification of
the electrostatic force is enough for this analysis and later with simulations is proven
to provide a good approximation of the dynamics of the system. Furthermore, the
e↵ective force for moment bending in the beam is di↵erent for each electrode, being
the top electrode the one wielding most of the bending force on the beam due to
the di↵erence in displacement and applied moment. Thus the overall e↵ective force
acting on the beam is described in this analysis by only one e↵ective force denoted
by Fe0 . As we can see in 3.5 the three forces exerted by the di↵erent wire electrodes
represent di↵erent contribution, being the top electrode the electrode with the most
 42
yielded force and the resultant e↵ective force (red arrow in the right structure). This
force is dependent on the one dimensional separation distance from the anchor, it
can be obtained by considering all the force contributions and translating them to a
distance l0 . The first metal can be excluded in the analysis since the force contributed
to the total bending of the structure is minimal, the second and third body metals
are the one providing the most force to the beam. The e↵ective force contribution
was taken by approximating the di↵erent runs in the MEMS+ software and analysing
every node in the brick elements declared by Coventor software and calculating the
e↵ective force at l before and after the pull-in.

Figure 3.5: Force contribution by every electrode and approximated force for the
Verilog-A implementation

The contact force is also a nonlinear contribution that changes according to the
beam velocity and material. There has been di↵erent approaches to model the con-
tact forces, some of them are derived for MEMS relay switches [4] and RF MEMS
ohmic switches [37]. The modelling of these e↵ects describe the interaction of a move-
able structure and an electrode on physical hard contact. When the moveable beam
reaches the maximum allowed deflection constrained by go an plane solid structure is
declared to stop the motion. At the point where both surfaces are in contact an ad-
hesive force is introduced [29]. The adhesion force can be explained by Van der Waals
forces and the Hamaker theory [28]. This forces depend on the material Hamaker con-
stant and Van der Waals screening constant zs [38]. For the aluminum the Hamaker
 43
constant acquired in [28] is used. The screening distance for this analysis is taken as
3Å, which is the one used for solids in [37]. The governing equations describing the
contact force and the adhesion forces are:

8
>
>
<Fadhesion if go > y
Fstop = (3.9)
>
>
:⇤(Fe0 (y, V ) + Fadhesion if y go

where ⇤ is a smooth turn on function in the form of:

2
⇤= atan(eft (go y)
) (3.10)
⇡

Where ◆ is the ratio as the function turns on, to avoid discontinuities it was found
that values between 100 < ft < 1000 gave good results in the code. Other turn on
functions have been proposed in other works [34] but the functions were declared as
a limited exponential that caused discontinue forces when the position of the beam
reached the end of the displacement. This stop force guarantees that the beam does
not displace more than the declared range without causing irregularities. The code
implementation for the smooth stop force in the Verilog-A code is declared for each
pair of source and drain with a normalised force as seen in Figure 3.6. For debugging
purposes, every converged iteration in the Verilog-A code can be monitored in the
resulting log file in the simulation by including the $strobe function.

Figure 3.6: Stop force Verilog-A implementation

The adhesion force is dependant on the material and the penetration of the con-
tacting metals, for the Verilog-A code, the model for adhesion force per area has been
 44
adapted from [4] and is expressed by:

H ys
Fadhesion = ⇤ (3.11)
6(go y)3 ys y

To help with the DC convergence of the Verilog-a model the Fstop , Fe0 and Fadhesion
are coded by restricting the displacement to avoid singularities using turn-on and
smoothing functions [4] [36] in the form of go ⇤ tanh(1/g0 ). Figure ref The system
describing the dynamics of the reduced model for the relay is depicted in the Verilog-A
code in the following state space representation:

Figure 3.7: Smooth force calculation Verilog-A code implementation

2 3 2 32 3 2 3
6 ẏ 7 6 0 1 7 6 y1 7 6 0 7 0
4 5 = 4 q 54 5+4 5 (Fe + Fstop ) (3.12)
kef f kef f mef f 1
ÿ mef f Qm
y2 m

This state representation is coded to reduce state space variables in the node
assignment done by the SPECTE simulator. The first order approximation for the
quality factor Qm can be found for a uniformly distributed beam, for the BEOL
structure a internal Qm is defined for simulations taking values for critically damped
structures [34]. As the Verilog-A code is a implementation of a behavioural model
in circuit based simulator, all the contributions (force, current, voltage) are assigned
to node or branches for the solver to calculate all the contributions and to resolve
taking into consideration Kirchho↵ and Ohm laws for nodes and branches. There is no
di↵erence between the mechanical and the electrical contributions, therefore we have
to take care when assigning mechanical contributions to a node since the di↵erence
in the regime of units might blow up the simulator tolerances. The tolerances for the
 45
mechanical contributions can be later changes inside the disciplines.vams file, this can
be also be useful for declaring private-owned tolerances and Natures. In Figure 3.8 we
can see the implementation of the state space representation of the system in Verilog-
A code. This part of the code can be read as: Assign the (Pos(velocity)) contribution
when ddt(Pos(z,anchor))=(Pos(velocity)). This type of node contribution assures
that there is no another contribution to the node from other source [39].

Figure 3.8: State space representation of the dynamics of the beam in Verilog-A

This model also includes the contact resistance calculation. The contact resistance
(Rcon ) in MEMS and NEMS has been studied for di↵erent materials. The amount of
resistance depends directly on e↵ective area areaef f that is highly dependent on the
number of asperities and material quality. The number of asperities and hence the
areaef f making contact increases with the applied force since the material mechanical
properties change with the stress caused by the force. For the code we choose a simple
descriptive model dependent on the material hardness and the applied force. The
equation describing the Rcon is [40]:

s
F
Rcon = (3.13)
⇠⇤⇡⇤H

Where F is the force applied to the contact that is found to be approximate to the
Felec . ⇠ is dependent on the mechanical deformations properties of the metals making
contact. For elastic ⇠ = 0.5 and for plastic ⇠ = 0.1 [40]. A dynamic calculation of this
parameter can be included on the Verilog-A code, but for simplification a fixed value
of ⇠ = 0.1 is chosen. The change of Rcon does not vary a lot with the di↵erent values
of ⇠, therefore is not necessary to waste computational power and state variables
in this calculation. H is the material hardness in GP a and can be found for bulk
 46
aluminium. Further insight into atomic deposited aluminium might be required to a
more accurate approximation of the hardness of the contacts. The entire model can
be described as a variable resistance or a couple of resistances connected between the
source and drain terminals of the 4T and 6T relays respectively. The ON-resistance
is described by the resistance imposed by the air gap. The OFF-resistance is the
superposition of the channel resistance which is given by the wire resistance by:

length
Rchannel = ⇢ (3.14)
22

Where ⇢ is the resistivity of the material, in this case AL. The length is the chosen
extension of the wire. The area is calculated as a function of the technology node
feature . A graphical representation on how the resistance between the source and
drain terminals change according to the position of the beam is shown in Fig. 3.9.

Figure 3.9: a) The resistance between S0 and D0 is the resistance of the air b) Now
the beam connects S0 and D0 changing the resistance of the other pair to Rair .

Having declared all the formulas to calculate the dynamics of the system it is
required to declared the inputs and outputs of the electric circuit that is going to be
placed in the EDA. For this step we have to take into consideration the Verilog-A
coding best practices [39]. First we declared all the electrodes as inputs/outputs.
To make the relay bidirectional we declare source and drains and inouts, the gate
and bodies are declared as inputs. It is recommended that the system is declared in
branches and no single nodes. So we declared the nodes for the structure with their
 47
inherent capacitances. The major branches are gate-body0, gate-body1, source0-
drain0 and source1-drain1. This simple representation of the circuit is shown in
Figure 3.10. Note that the circuit implementation include more capacitances and
high resistance contributions. Some of the variable capacitances and resistances in
the model can be taken as constant, for this analysis these were taken as variable.

Figure 3.10: Simple circuit for Verilog-A

The algorithm selected to solve the system is adapted from the one found in [36].
Making the required changes and parametrising for the reduced BEOL relay model
the algorithm implemented in the Verilog-A code is shown in Fig. 3.11.
This algorithm allows to calculate the constants in a first setup step, that is not
repeated again during the simulation, saving time and computing power. The calcu-
lation of the forces at y = 0 allows the simulator to start by placing the beam in the
starting positions evading faulty starts and irregularities. Some of the capacitances
in the model are declared as constant since their change is not significant.
 48

Figure 3.11: Table describing the algorithm used in the Verilog-A code implementa-
tion

3.3 Model Simulation and Comparison

A model built using the minimum feature size  of 21nm is simulated in Cadence
using the SPECTRE circuit simulator. DC and Transient are possible with this
model. The best fitted algorithm provided by SPECTRE for transient simulations
was found to be GEAR2. The model response is compared to the one obtained by the
FEM software Coventor MEMS+. Both models are placed in the same test bench in
CADENCE. Fig. 3.12 shows the DC respose from MEMS+ and the Verilog-A code.
It can be seen that the response is quite accurate. The reported Vpi for the MEMS+
 49
model is found to be 3.65V and 3.6 for the Verilog-A model.
A transient analysis (Fig. 3.12) ,with a input voltage signal of 3.7, is carried out to
obtain the mechanical delay ⌧mech of both models. It can be seen that for the MEMS+
models the ⌧mech is found to be 21.65ns and for the Verilog-A model 20.34ns, showing
that the elaborated model has only around 7% of margin error in DC and transient
analysis. The MEMS+ model shows a di↵erent turn-on behaviour than the Verilog-a
model, this is due to the inherit capacitances declared in the MEMS+ environment
for plate-contact model between the channel and the source and drain electrodes
that cannot be excluded in the analysis. However, since the channel is consider as
an electrical floating node due to the intra-metal-dielectric. Such capacitance is not
declared on the Verilog-A model, obtaining in this way a more descriptive behaviour
of the turn-on function. The pull-in time comparison between this work and MEMS+
is found on Fig. 3.12

Figure 3.12: Comparison of the transient response of the BEOL relay in MEMS+
and the Verilog-A model. The reported times for the ⌧mech is found to be 21.65ns for
MEMS+ and 20.34ns for the Verilog-A model.

To verify the Vpi and the Vrelease of the Verilog-A model we took as a base the
dynamic behaviour of MEMS+. A voltage sweep for 0V to 4V and back, was applied
 50
to the gate of both a MEMS+ model and the Verilog-A model. In Figure 3.13 we
can see the movement of the beam and when the pull-in and release happen. Going
beyond the e↵ective force that exerts in the beam has been extracted from both
software and plotted against the applied voltage. We can see that even there is a
di↵erence between the movement and the exerted force, this is minimum and does
not a↵ect the important parameters of the dynamic and electrical behaviour of the
relay.

Figure 3.13: Comparison of the transient response of the BEOL relay in MEMS+ and
the Verilog-A model. The reported Vpi for the models are 3.62 and 3.69 for MEMS+
and this work respectively.

Another e↵ect that has not been taken into consideration neither for MEMS+ nor
Verilog-A models is the electron tunnelling e↵ect. Such e↵ect can be taken into con-
sideration in future model improvements. Models for tunnelling have been reported
for di↵erent architectures but they require a lot of computational power. Thus for
a Verilog-A implementation the best option is to obtain a empirical model based on
experimental work and simplified exiting methods with the derived data.
The mechanical constant and values calculated and use in this work are shown
in Table 3.2. The f0 has been extracted from MEMS+ and COMSOL, the values
extracted from this softwares have been used to implement the Verilog-A model.
 51

Table 3.1: Comparison of the DC and Transient time simulations of MEMS+ and
Verilog-a models
Simulation times
Analysis MEMS+ This Work
DC 2.5 s 1.5 s
Transient (for a 10 uS stop time) 95 s 6s

Table 3.2: Mechanical values

Parameter k spring constant f0 (MHz) E↵ective mass
COMSOL 0.2857 740.5 1.32e-18
MEMS+ 0.298 741.5 1.29e-18

The simulation time for the Verilog-A model has proved to be faster than the one
for the MEMS+. Table 3.1 shows the simulation times for DC and transient analysis
for both models, showing the advantage of the Verilog-A model. Table 3.3 shows
the performance and precision of the relay model in this work and the simulations
extracted from MEMS+.

Table 3.3: Accuracy of proposed model

Parameter Pull-in Voltage (V) Release Voltage (V) Pull-in time (nS)
MEMS+ 3.62 2.89 21.65
This Work 3.69 2.96 20.34
% error 2% 3% 6%

The error is not accumulable for the Verilog-A model, only it has to be taken into
consideration the electrical delays due to the declared capacitances and that we have
not yet included the length and complete parasitics attached to the source and drain
electrodes.
The model as seen in Table 3.3 is quite accurate and can be improved if the
extracted data from MEMS+ or COMSOL is included as a technology constant inside
the code. It is good to point out that this model works only for the BEOL relay
previous declared, if one would like to perform a similar model it would require to
run MEMS+ or COMSOL simulations to extract the constants for the mechanical
behaviour and to declared of the electrical characteristics of the new model.
 52
In the next chapter di↵erent complex logic circuits are simulated, demonstrat-
ing the advantage to have a fast compact model that can achieve fast and accurate
approximations of the real behaviour of the NEMS relay.
 53

Chapter 4

All-Relay and Hybrid

NEMS-CMOS Circuit Level
Simulation

In this chapter di↵erent all-relay circuits topologies are simulated to verify the Verilog-
A model elaborated in the previous chapter. This to prove the reliability of the
compact physical model for complex-logic simulation. In addition to simulations,
hybrid CMOS-NEMS circuits are compared to typical CMOS implementations and
analysed as potential candidates for ultra-low-power applications.

4.1 Circuit Design With Relays

Relay-based logic circuits are constructed following design guidelines di↵erent from
the established well known CMOS circuit-design techniques. The reason lies in the
basic di↵erences between transistors and relays circuits architectures. The first is
governed by the quadratic Elmore delay, which is calculated by the number of devices
stacked in series. Thus optimised CMOS circuits avoid long stacks of devices and
try to achieve a distributed electrical e↵ort using simple logic gates along the many
number of stages in the circuit [24]. Due to to the di↵erence between the mechanical
 54
and electrical time constant in NEMS relays, being the mechanical time constant
orders of magnitude larger than the latter, relay-based architectures are designed try-
ing to reduce the mechanical switching delay by comprising single-stage actuation of
complex logic gates, i.e. we want to have a circuit when all the mechanical switching
movements occur at the same time, guaranteeing a single mechanical delay. For each
gate-driven stage in a relay based circuit, the total delay increases, thus minimising
gate actuations in this type of architecture yields the best energy-delay product. Re-
placing CMOS transistors with NEMS relays in an optimised logic CMOS circuits will
not yield the same energy-delay product, new optimisation techniques are required
to achieve comparable performances for the same logic operation.

4.2 Optimised NEMS Logic Design Paradigm

Figure 4.1 shows the implementation of a 4-input AND logic gate with CMOS and
relays. The di↵erence between the two architectures can be clearly seen in the in the
number of gate delays for each design. For the CMOS implementation there exists
4 gate-delays, which for CMOS based circuit optimises the energy-delay product. If
we were to replace every transistor with a NEM relay, the total mechanical delay of
the circuit 4 mechanical delays, much larger than the CMOS implementation. For
the relay-optimised architecture (Figure 2-b) the total delay of the gate is of only one
mechanical delay. It can also be observed that the number of devices used for the
relay implementation is less than the one with transistors, thus reducing the number
of relays and hence total area of relay-circuits can be achieved by using this pass-
transistor logic style. Another design technique discussed in [24] is the preferential
use of a pass-gate logic style over a static-gate style. This approach promises faster
logic gates with half the number of devices used in the static-gate style.
Simple (AND, XOR, NAND, etc.) and complex (32 bit- Multiplier) have been
 55

Figure 4.1: Comparison between CMOS and NEMS circuit topology. Adapted from
[24].

demonstrated using only relay devices in [6] and [24] respectively. These designs are
optimized to reduce the number of NEM relays to lower the fabrication area, achieve
a fast operation and lower the power consumption. For instance, a 16-bit multiplier
built using the 4T and 6T relays demonstrated in [41] was benchmarked against 16-
bit CMOS multipliers built in 90nm and 45nm technology. The results showed that
the relay-based multipliers show an average of 10x improved energy-efficiency above
CMOS architectures for operational speeds of sub-10 million operations per-second
(MOPS) [24].
Even though the possibility of the low-power advantages of only-relay circuits
have been demonstrated, the benefits of these designs can be eclipsed by their overall
 56
large employed area compared to their CMOS counterparts, not to mention the elab-
orated fabrication and integration techniques to accomplish this structures [9]. For
instance, most of the relay structures discussed in the past chapters are reported as
CMOS-compatible designs in terms of fabrication temperatures and materials, but
the complex forms needed for their optimised behaviour increase the total fabrication
costs of the final circuit [12] [42].

4.3 Logic Circuit Simulations

In this section we verify the reliability of the elaborated Verilog-A model by simulating
di↵erent complex logic circuits. Full-Adders (FA) with only 1 mechanical delay can
be elaborated with 6T relay switches as demonstrated in [34]. Figure 4.2 shows the
circuit topology of a Full-Adder built with only relays. By cascading two FA a 2-
bit Adder can be constructed. This circuit is good start to test the performance of
the fabricated Verilog-A model. The transient simulation obtained in CADENCE
is plotted in Figures 4.5 and 4.6. It can be seen that the model has an accurate
response and there is no problems with the cascading of models. Transit times are
recorded as expected and there is no fault values. In [24] a 7:3 all-mechanic digital
compressor is introduced. The authors describe that the simulation of such circuit
was not possible due to convergence problems found in their model, for that reason
they presented experimental measurements. In Figure 4.7 the simulation results of
the 7:3 compressor is shown. The circuit simulated fast ( 6.5 seconds) without any
convergence problem. This simulation proves the possibility for large complex circuit
simulations.
FAs simulation can give us a good a idea of how well the Verilog-A model behaves
in transient and DC analysis in a mixed-signal environment such as the SPECTRE
simulator. On [36], the author discusses that a good indicator for benchmarking
 57
compact models is a comparison of simulation time vs cascaded N-bit Adders. Since
there is no antecedent for a vertical BEOL compact model, the proposed Verilog-A
model is tested in larger N-bit multipliers. Figure 4.4shows the schematic for a 16-bit
Adder. The simulation time for this model was as little as 1.25min. The input and
output vector waveforms for this simulations can be seen in Figure 4.8 and Figure 4.9.
The simulation times for the 16-bit Adders were very good, going beyond 32-bit Adder
were simulated without problems in around 2.5 min. The proposed Verilog-A model
outperforms other elaborated models allowing the test of big Adders, showing fast
simulation times without convergence issues.

Figure 4.2: 1-Bit Full-Adder built with 8 6T BEOL relays

 58

Figure 4.3: 2-Bit Adder block diagram[17].

Figure 4.4: 16-Bit Adder built with 64 6T BEOL relays

 59

Figure 4.5: Waveforms graph for a 2-bit Adder

Figure 4.6: Waveforms graph for a 2-bit Adder

 60

Figure 4.7: This plots shows the simulation results for a 7:3 compressor introduced
in [24]

Figure 4.8: Input vector waveforms for a 16-bit Adder.

 61

Figure 4.9: Output vector waveforms for a 16-bit Adder.

The biggest circuit simulated making use of the BEOL Verilog-A model introduced
in this work is a 6-Bit multiplier adapted from [8]. Multipliers are one of the most
complex and expensive arithmetic operations in digital integrated circuits. Di↵erent
multipliers topologies have been proposed trying to overcome the power requirements
for current technology demands. All-relay multipliers are a good option for ultra-
low power applications. For this topologies the circuit designers tries to reduce the
mechanical delays as much as possible. The simulated multiplier shows only 4 me-
chanical delays for its optimised design. For this work the Partial product generation
matrix was done using an AND network. N:3 compressors are used for partial prod-
uct accumulation and FA and HA are used for small partial product accumulation.
The simulated multiplier makes use of 712 relays (combining 4T and 6T). It is good
to point out that there has not been any reported simulation for such big circuits
 62
before. The schematic for this 6-Bit relay is shown in Figure 4.9. The resulted vector
waveforms are shown in 4.11
The simulation of VLSI circuits is mandatory for the design and verification of
new ideas and products. NEMS are a promising alternative for new circuit topologies
thus having a reliable model for large circuit simulations is necessary.

Figure 4.10: 6 Bit Multiplier. Adapted from [8]

Figure 4.11: 6 Bit Multiplier. output vectors

 63

Table 4.1: Input vectors for 6 Bit mulitplier

A[5-0] B[5-0] Product
1111111 000000 000000000000
101010 001101 001000100010
1010001 000000 000000000000
101110 100110 011011100010
0000010 000000 000000000000
0101010 101010 011011100100
100000 010000 001000000000
1010100 000000 000000000000
0000001 000001 000000000001
1010100 000000 000000000000
0000010 000010 000000000100

The input vector for the multiplier are shown in Table 4.1.

4.4 Hybrid Power Gating With BEOL Relays

Nowadays, is a widely known fact in the research community that transistors leak
current when they are o↵, with smaller technology nodes being the most a↵ected.
Power-gating is a conventional industry-standard technique to mitigate the leaking
of electronics when there is no processing occurring, like standby and sleep times.
This method is very popular among mobile, wireless and sensing applications, where
idle times are long [43]. The popularity of this method falls on the simplicity of its
basic implementation, which does not require any change in the logic circuit nor the
power-gate operation. CMOS transistors have been used efficiently in the last years in
power-gating circuits, but due to theirs increased o↵-state leakage the practical power
consumption reduction is becoming less with smaller nodes. Another e↵ect caused
by CMOS power-gates is the voltage drop created across the gate circuit that lessens
the e↵ective voltage supply to the circuit, reducing the performance of the circuit
by reducing its speed. Figure 4.12 shows the implementation of CMOS and Relay
power gating. There can be found a trade-o↵ in CMOS power gates between area and
 64
speed. Thus, circuit designers must size the transistors to optimize their operation for
di↵erent applications. The near infinite resistance of NEMS relays provided by the air
gap in their o↵-state practically eliminates the leakage of these devices. Furthermore,
the on-resistance of relays is relatively smaller than their CMOS counterparts and they
can be arranged in parallel to further reduce their resistance and increase the e↵ective
supply voltage. Thus, nanorelays are promising alternative for power-gating. This
section revises the possibilities for power gating using hybrid NEMS-CMOS circuits.

Figure 4.12: a) CMOS implementation of power-gating: The leakage is reduced but

not eliminated, there exists a reduced supply voltage. b) Relay implementation of
power-gating: The relay shows zero-leakage so the current is completely o↵ during
idle times, relays can be arranged in parallel to reduce the e↵ective resistance and
increase the supply voltage

4.4.1 Energy-Efficiency With Power Gating

The total consumed energy in a logic circuit is described by the active, switching and
idle energy. The implementation of power gates for CMOS and NEM-CMOS with
the inherit capacitances is shown in Fig. 4.13 [44]. The zero leakage in NEM relays
significantly reduce the last term, thus for this analysis it is considered negligible.
The energy in a logic circuit can be expressed as a function of the idle (Tof f ) and
 65
active time (Ton ). We can express the energy per power-gate switching cycle for the
NEM relay (ER ) and the MOSFET transistor (ET M ) as [44]:

Figure 4.13: a) CMOS implementation of power-gating b) Relay implementation of

power-gating. is the ratio of supply capacitance and CMOS capacitance. and ✏
are the ratios of drain and gate capacitances for the CMOS Transistors (CT M ) and
NEM relay (CR ).

ER = Eactive + Eswitch
(4.1)
= Ion Ton Vsup + ( UR CR + CL )VDD Vsup + UR CR VR ef f )

ET M = Eactive + Eswitch + Eleak

2
= (Ion Ton UT M Iof f Tof f )Vsup + (UT M CT M + CL )VDD Vsup + UT M CT M VIO

(4.2)

Where Vsup represents the external supply voltage for the desired IR product
inherent in the power gate, it can be described as:

VDD + ION RON,R

Vsup = (4.3)
MR
 66
Where Ron,R is the ON-resistance of a single power-gate NEM relay switch. MR is
the multiplicity factor that is described as the total e↵ective width for the MOSFET
transistors on the power gate and the number of NEM relay swiches in parallel. CT M
is the gate capacitance for the MOSFET. VIO is the e↵ective voltage driving the gate
capacitance and VR ef f is the e↵ective gate voltage for the relay that can be described
by:

VR2 ef f = Vpi (Vpi Vpo ) (4.4)

As we discussed before, to obtain a better performance in the gated logic circuit,

is recommended to have a sufficient high efficient supply voltage. To achieve this, the
multiplicity factor MR can be optimised in the following manner for MOSFET and
NEM relays:

s
dET M kRON,T M TON
= MR Opt = ION 2 2
(4.5)
dMR Iof f TOF F VDD + CT M VIO + CT M VDD

s
dER kRON,R TON
= MR Opt = ION 2 2
(4.6)
dMR CR VREF F + ✏CT M VDD

ION P
Where k = ION
assuming that ↵f TON >> .

Table 4.2: CMOS technology parameters for the standard PTM [2]
Technology node (nm) VN OM (V) CT M (fF/m) RON (/m) IOF F (nA/m)
12 0.65 0.6 135 500
16 0.7 0.7 140 310
22 0.9 0.9 145 120
32 0.9 0.9 150 52
45 1 1.5 165 270

To perform an analysis of the performance between the CMOS and NEMS power
gating techniques, we can analyze the normalised amount of the lost energy kin to
the ON-state energy of an ideal power gating [44].
 67

s
kRON,T M (PLEAK,T M TOF F + EG,T M )
ET M ⇡ 2 2
(1 + +
TON VDD 2↵f TON
s (4.7)
2 2
kRON,T M IOF F TOF F
)+
4TON (PLEAK,T M TOF F + EG,T M ) 2↵f TON
s
kRON,R EG,T M
ER ⇡ 2 2
(1 + )+ (4.8)
TON VDD 2↵f TON 2↵f TON
2 2
For ER = (ER EON )/EON , EG,T M = CT M (VIO + VDD ), EG,R = CR (VR2EF F +
2
✏VDD ). Using the predictive technology parameters shown in 4.2 and the parameters
for the proposed 4T BEOL NEM relay with a half pitch  of 21nm we can obtain the
energy ratio for the CMOS and NEM power gate techniques as it was demonstrated in
[44]. Simulations in small circuit cells using the Verilog-A model showed the possibility
for the construction of bigger and more complex logic circuits for power gating, small
simulations were carried to test the multiplicity e↵ect on the supply voltage. We
can find with (4.9) that the minimum TOF F required for the NEM power gating to
obtain savings over their CMOS counterparts ( 21nm technology node prediction
parameters) is around 8µs.

RON,R CR · EG,R EG,T M

TOF F,min ⇡ ( 1) (4.9)
RON,T M CT M · EG,T M PLEAK,T M

A more in-depth analysis on power gating with NEMS can be found in [44], [45],
[43] and [35]. Power gating is one of the most discussed hybrid NEM-CMOS tech-
niques that show promising solutions. Some of the advantages to mention about the
NEMS power gates over the CMOS implementations it is the fact that the multi-
plicity factor UM for MOSFETS implies that the e↵ective width of the power gate
increases to reduce the supply voltage drop. This overall larger width area comes
with more leakage due to the extra transistors. In the other hand, NEMS relays can
be connected in parallel to decrease the e↵ective resistance and no penalty in leakage
 68
is gained with this technique. Some of the penalties for the NEM relay implemen-
tations are: the overall area needed for placing all the parallel relays required to
increase the e↵ective supply voltage, the mechanical delay that restricts the clocking
frequency and the changing ON-resistance of the NEM relays [40]. Power gating is an
interesting technique where the NEM relays demonstrate the advantage of having a
near-zero current leakage for the overall power consumption of logic circuits. For long
idle times, NEM relays are a great alternative for power gating, due to the OFF-state
power consumption and the high integration density that can be achieved with the
vertical BEOL relays.

4.5 Hybrid SRAM Cells

Memories are important subsystems in most of the integrated circuits and one of
the most challenging design tasks for low-power applications. CMOS scaling has
allowed the fitting of more SRAM memory cells in smaller areas, but it has also
jeopardized the stability and power consumption for smaller technology nodes. Stable
writing and read operations are becoming harder to achieve with small cell sizes and
low supply voltages. Di↵erent techniques try to alleviate the problems of the new
memory cells like a) adding more transistors in the cells and the peripheral circuits,
b) using di↵erent supply voltages for read and write operations, c) the use of high
and low threshold voltage transistors. The proposed solutions manage to solve some
of the problems in memory cells, but they do no not achieve to eliminate the leaking
current for hold operations when some of the transistors in the cells are in the o↵-
state. Leaking current in CMOS memory cells is a grave concern, not only due to
the o↵-state power consumptions but for the increased read access latency caused
by leakage current. Using low leakage devices has been an explored as a promising
technique to improve the performance of memory cells. Therefore, NEMS relays can
 69
be employed as potential low-leakage devices for improved SRAM memory cells with
low power consumption [46]. In this section, a hybrid NEMS-CMOS SRAM memory
is discussed, the obtained plots are simulated in SPECTRE using the elaborated
Verilog-A model and SPICE models by Predictive Technology MODELS (PTM) [2].

4.5.1 6T CMOS SRAM vs 4T-2R Hybrid SRAM cell

Hybrid SRAM cells have been proposed in [47] and [48]. Dadgour et. al. suggested
to replace the pull-up and pull-down network transistors in a SRAM cell for NEM
switches. This configuration achieved almost 8x lower leakage with a slighter increased
reading latency and Signal to Noise Margin (SNM). The design was compromised by
the high ON-resistance of the NEMFET used for the simulations. Chong et. al.
proposed to replace the pull-down network NMOS transistors with 3T NEM relays.
The simulations of the design proved that the static power consumption could be
significantly decreased by using the novel configuration. Also, the SNM of the cell
was to shown to increase due to the hysteresis present in the NEM relays.
In this thesis, we treat with a design similar to the one in found in [47]. By
replacing the pull-down NMOS transistors with 4T BEOL NEMS relays a SRAM
with low power consumption and stable read/write operations can be accomplished,
all this trying no to compromise the read and write latency in a significant manner.
Figure 4.14 shows a standard CMOS 6T SRAM and a hybrid CMOS-NEM 4T-2R
SRAM.
 70

Figure 4.14: a) CMOS 6T SRAM b) CMOS+NEMS 4T-2N SRAM ( NMOS transis-

tors are substituted by NEMS relays with body bias (Vb)

Replacing the Pull-Up NMOS transistors in the SRAM is possible, but it will
compromise the latency and SNM of the cell [47]. Furthermore, the contribution for
power reduction is not as significant as the one obtained by replacing the pull-down
transistors. For SRAM cells, the literature demonstrates that NMOS transistors show
gate leakage usually greater than their PMOS counterparts [49] and that in some cases
can surpass the drain to source leakage [50]. Thus, the major contribution of current
leakage can be attributed to the NMOS transistors. With the proposed design a static
power reduction of around 80% can be achieved [49].
Read operation for the SRAM cell does not compromise the speed, tests involving
similar architectures have shown that the read latency for CMOS-NEM SRAM cells
is analogous to the CMOS cells [50]. The butterfly plot for the READ operation of
a standard of a 6T SRAM using the low-power applications (LTP) 20nm technology
models is shown in Fig. 4.15 along with the hybrid implementation of the same SRAM
using PMOS and 4T terminal relays with a minimum half-pitch  of 21 nm and cell
area of 82 . It can be observed that both the CMOS and hybrid implementation
show a similar SNM, being the hybrid slightly larger (0.38V for CMOS vs 0.41V for
the hybrid), this due to the hysteresis and sharp subthreshold slope present in the
 71
BEOL relay [50]. The SNM of the hybrid memory cells can be further improved by
taking advantage of the body biasing and hysteresis of the 4T relays. By supplying
a di↵erent body voltage (Vb ) to the NEM relays one can obtain a low and high
Vpull in for each switch in the pull-down network. This technique allows to change
and optimise the READ SNM of the hybrid SRAM cell. This demonstrates the
prominent advantage that is to have a fourth terminal for body biasing, not only for
delay-energy optimisation but also for circuit design. Figure 4.16 depicts the butterfly
plot obtained by optimising the SNM (780mV ) of the memory cell by applying a
di↵erent Vb for each NEM relay.

Figure 4.15: The plot shows the the butterfly plot for the CMOS and Hybrid SRAM
cells, it can be seen that the SNM for the Hybrid implementation is slighter larger

The WRITE operation for the hybrid SRAM is the only operation that involves
a mechanical delay (⌧mech ), if and only if a READ operation is followed after it. To
take advantage of this techniques, the access NMOS transistors should be sized to
minimise the writing speed. Even though the WRITE operation comprises a ⌧mech ,
the writing of the cell for a 6T CMOS and a 4T-2R hybrid topology can be comparable
[47].
 72

Figure 4.16: The SNM of a Hybrid SRAM cell can be optimised by applying di↵erent
V b to each di↵erent NEM relay to obtain di↵erent Vpull in

Figure 4.17: The layout implementation for a hybrid SRAM cell for a 20 nm node
technology. It can be observed that the NEM relays can be constructed on top of the
silicon area for the cell to increase the integration density.

The cell area for the hybrid CMOS-NEM SRAM does not presents any drawbacks
since the NEM relays can be constructed on top of the PMOS transistors on the BEOL
metals as seen in Fig. 4.17, thus high integration density can be accomplished and
further increased by layout engineering.
The hybrid SRAM cell inherits the challenges of the NEM switches, the variability
of the resistance across the multiple switching cycles might change the behaviour for
the WRITE and READ operations. Furthermore the writing latency might be a
drawback since it depends on the ⌧mech . Even by scaling the slow response of for
 73
WRITE might be not suitable for some applications where rapid writing is desirable.
The WRITE and READ simulation results for the Hybrid CMOS-NEMS SRAM is
shown in Figure 4.18.

Figure 4.18: Simulation of WRITE and READ operations of a Hybrid CMOS-NEM

SRAM
 74

Chapter 5

Concluding Remarks

5.1 Summary

Chip fabrications have managed to build smaller transistors with increased perfor-
mance, but lately, this has come with a power consumption penalty. CMOS transis-
tors leak current when they are o↵, causing an increased power consumption in idles
times. Such leakage increases as the technology scale down, compromising the power
performance of future electronic devices. In this work, we have explored the NEM
relays as a promising alternative switching device that can improve the power con-
sumption in current and future VLSI applications. We focused especially in a BEOL
vertical NEM relay. This device o↵ers the best compatibility for its integration in
standard CMOS process without many complicated steps of post-fabrication steps.
The vertical relay constructed using vias and wires in the interconnect stacks makes
use of air gaps to achieve a zero leakage current and abrupt turn-on behaviour. These
properties make the BEOL relay an attractive building block for complex all-relay
and hybrid CMOS-NEM logic circuits. Compared to others proposed designs of liter-
ature, the BEOL relay o↵ers fewer constraints for its integration With the predictive
technology node scaling this device allows its high integration density and scaling.
A significant contribution in this thesis in the elaboration of a compact physical,
behavioural model for the BEOL NEM relay. This work introduces the first reliable
 75
model that can be used for VLSI. The computation time outperforms commercial
software like MEMS+. There have not been reported models for this relay that
could manage large circuit simulations. Some of the published models for MEMS
relays can handle simple circuit simulations, but they fail to converge and to simulate
fast when they are placed in complex logic circuits. The elaboration of the model
is described and its accuracy compared to a extracted model from the commercial
FEM software MEMS+. Simulation times and physical behaviour is examined. The
proposed Verilog-A model proved to be an accurate description of the mechanical and
electrical behaviour of the BEOL relay.
A 16-bit adder and 7:3 compressor built only with NEM relays was simulated
in SPECTRE using the proposed Verilog-A model. Analysis on how these circuit
topologies o↵er advantages over their CMOS counterpart is presented and discussed.
The guidelines for all-relay circuit design are also reviewed. The simulation of these
circuit architectures serves as a prove of the reliability of the Verilog-A model in a
complex logic analysis.
Hybrid CMOS-NEMS architectures such power-gating and a SRAM cell are dis-
cussed as novel topologies that can significantly reduce the power consumption of
future integrated circuits. Power gating making use of BEOL relays with 21nm half-
pitch is analysed as a reliable power gate device. The SRAM hybrid cells make use of
four CMOS transistors, and two NEM relays to substitute the well known 6T SRAM
cell. The novel structure can reduce the power consumption of the SRAM cell for the
HOLD times without area nor READ latency penalties.
NEM relays are promising structures that can eliminate the current leakage in
electronics and hence the overall power consumption. Their integration with standard
CMOS process has been reviewed but there has not been an actual implementation of
hybrid-CMOS circuits. The main drawbacks of these devices are their slow mechanical
delay and the mechanical wear of the devices. Contact oxidation is a well-known
 76
problem in MEMS and NEMS contact switches. Furthermore, fabricated MEMS
devices have demonstrated a short productive lifetime, since the devices have the
tendency to break after some switching cycles. Hence, the practical implementation
of the NEM relays in modern electronics devices requires improvement not only in the
device design but also in fabrication techniques and material science. With mature
technologies, we will be able to fabricate reliable NEM switches without much hassle.

5.2 Future Research Work

There are many di↵erent and exciting paths to follow after this work. The fabri-
cation of this device with standard CMOS tools can be a nice way to test di↵erent
properties of the device that can not be analysed with software. Reliability is a very
important parameter to extract from a relay-life device. With this information, we
will be able to predict the lifetime of each relay and to redesign circuits accordingly
to this information. Optimisation of the device can be accomplished by analysing the
performance of di↵erent structures, materials and fabrication techniques. Also, the
dynamics of the fabricated device can be compared to the simulation results to have
a better understanding of the third order e↵ects a↵ecting the behaviour of the relay
in a di↵erent non-ideal environment.
Contact resistance is an important parameter for NEM relays since it describes
the voltage drop across the terminals, and it is a important parameter for circuit
design. The investigation of the resistance by material characterization is a major
step in improving the device model. Another consideration for improvement of the
relay model is to include device variations, yield and corner analysis.
Another major trajectory to follow is the exploration, design and fabrication of
hybrid CMOS-NEM circuits. These topologies are critical and can find application in
many popular modern handheld devices where active times are short and the device
 77
is mostly idle, and power losses due to current leakage constitute a big portion of the
consumed power.
At last, but not least, the sustained improvement of the compact model is a
compulsory task. By fabricating, testing and extracting experimental data from the
di↵erent characterization analyses we can improve the compact model of the relay
by revising the model formulations. The creation of a standard NEM libraries for
commercial EDA software that contains small functional cells with their layout to-
pography can enable a faster design flow process for hybrid CMOS-NEM circuits.
Constant improvement of the compact model is a crucial task. By fabricating,
testing and extracting experimental data the model can be improved according to
the operational characteristics of the device. The creation of standard NEM libraries
for commercial EDA software that contains small functional cells with their layout
can enable a faster design flow process for hybrid CMOS-NEM circuits.
 78

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 84

APPENDICES

A Verilog-A Code

/* Verilog-A of a 4T BEOL relay for logic implementation*/

‘include "disciplines.vams"
‘include "constants.vams"

module BEOL_4T(s1,d1,g,b1);
inout s1, b1, d1, g;
electrical s1, d1, g, b1;
ground gnd;
branch (d,s) ch1;
branch (g,b1) B1;
kinematic y, velocity, y2, anchor;

// Structure, mechanical and electrical constants

parameter real gap_0=31.5e-9 from (0:inf); // For Force = Feature size
[m]
parameter real gap_d=21e-9 from (0:inf); // For contact = Feature size
[m]
parameter real l=224.4e-9 from (0:inf); // l=2.31e-7 from (0:inf); //
beam length at effective force = 5.5*2F [m]
parameter real F=21e-9 from (0:inf); // Feature size [thickness] [m]
parameter real wp=468e-9 from (0:inf); // plates width 22*F[m]
parameter real wp_e=10e-9 from (0:inf); // electrodes width [m]
// Electrical parameters
parameter real R_con=1.0 from [0:inf); // constant resistance for the
contacts [Ohm]
parameter real R_chan=1e3 from [0:inf); // channel resistance [Ohm]
parameter real Rair=1e15 from [0:inf); // air resistance
 85
// Beam (aluminum)
parameter real rho=2.7e3 from (0:inf); // The density for [aluminum]
[kg/m^3]
parameter real E=70e9 from (0:inf); // The Aluminium young’s modulus

real A, b,q_gb1, q_gb2, F_c, F_e,F2_e, F_s, F_con, F2_con, Ik_1, m,

R_cha, R_cha2, zNor,F_conN, F1_stop;

//analog behaviour//

analog begin

@ ( initial_step ) begin
A=2*F*w; // Area calculation
m= 0.23*5e-18;//2*0.23*5e-18; // effective mass
I_z=‘M_PI*pow(10.5e-9,4)/4; // second moment of inertia for round
cantilever [*r/4]
k_1= 6*E*I_z/pow(l,3); // effective spring constant
Q= 0.7; // quality factor

// Forces at y=0
F_ele=‘P_EPS0*A*pow(V(g,b1),2)/2*1/pow(gap_0,2); // effective
electrostatic force at y=0
F_spring=k_1*g_d*tanh(Pos(y,anchor)/g_d); // spring force at y=0

end

//** Forces calculations **//

//-----Van der waals and contact forces---//

F_contact=(3.6e-19*w_e*2*F)/(6*‘M_PI*pow(gap_d-
gap_d*tanh(Pos(y,anchor)/gap_d),3));

//-----Electrostatic forces---//

F_elec=‘P_EPS0*A*pow(V(B1),2)/2*1/pow(gap_0-
gap_0*tanh(Pos(y,anchor)/gap_0),2);
// smooth effective electrostatic forces

//----Normalized caclulations for contact forces---//

zNor=Pos(y,Bd1)/(gap_d);
F_con=(2/(‘M_PI))*atan(limexp(1000*(zNor-1)));
 86
if(F_con<1e-12) F_conN=0;
else F_conN=F_con;
F1_stop=1.45*F_e*F_conN;

//----Spring & damping Force----------//

F_spring=k_1*gap_d*tanh(Pos(y,anchor)/gap_d); // smooth spring

forces
b=k_1/(0.9*2*‘M_PI*f_m_0); // damping coefficient

//---State-space description for the model approximation----//

Pos(anchor) <+ 0.0;
Pos(velocity):ddt(Pos(y,anchor))==Pos(velocity);
Pos(z,anchor):ddt(Pos(velocity))==1/m*(--1.0*F_spring
+F_elec-F1_stop+2*F_contact)+ b*Pos(velocity);
Pos(y2,anchor)<+ -1*Pos(y,anchor);

//** Electrical Equations **//

//---Source & Drain 1---//

vcap1 = transition(V(B1));
q_gb1=‘P_EPS0*A*vcap1/(gap_0-gap_0*tanh(Pos(z,anchor)/gap_0));
I(B1) <+ ddt(q_gb1);
I(g,gnd) <+ V(g,gnd)/1e17;

//--Conditions for conduction--//

if (Pos(z,anchor)<0.9*gap_d) begin
R_cha=2*R_c+R_ch+Rair;
// I(ch1)<+ V(ch1)/R_cha1;
end
else begin

R_cha=(2*R_c+R_ch);
end
end
endmodule

end
endmodule
 87

B Papers Submitted and Under

Preparation

• Jesus Javier Lechuga Aranda “Compact behavioural model of a BEOL nanorelay

for VLSI simulations”, Under preparation for IEEE A-SSCC, June. 2016.