UNIT-3

8255 programmable peripheral interface

The 8255 is a widely used, programmable, parallel I/O device.
• It can be programmed to transfer data under various conditions, from simple I/O to interrupt
I/O.
• It is flexible, versatile and economical and complex.
The 8255 has 24 I/O pins that can be grouped primarily into two 8 bit parallel ports: A and B,
with the remaining 8 bits a port C. The 8 bits of port C can be used as individual bits or be
grouped in two 4-bit ports: CUPPER (CU) and CLOWER (CL), as shown in the figure 1.1. The
functions of these ports are defined by writing a control word in the control register.

Figure 1.2 shows all the functions of 8255; classified according to two modes: the Bit Set/Reset
(BSR) mode and I/O mode.

The BSR mode is used to set or reset the bits in port C.

The I/O mode is further divided into three modes: Mode 0, Mode 1 and Mode 2. In Mode 0, all
ports function as simple I/O ports. Mode 1 is a hand shake mode whereby Ports A and/or B use
bits from port C as handshake signals. In Mode 2 Port A can be set up for bidirectional data
transfer using handshaking signals from Port C, and Port B can be set up either in Mode 0 or
Mode 1.

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Block Diagram of the 8255

CONTROL LOGIC

(Read): This control signal enables the Read operation. When the signal is low, the MPU
reads data fro a selected I/O Port of the 8255.

(Write): This control signal enables the write operation. When the signal goes low,
MPU writes into a selected I/O Port or control register.

RESET: (Reset): This is an active high signal; it clears the control register and sets all ports in
the input mode.

, A0 and A1: Theses are device select signals. Chip Select is connected to a decoded
address, and A0 and A1 are generally connected to MPU address lines A0 and A1 respectively

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CONTROL WORD
Figure 1.5 shows a register called the control register. The contents of this register called control
word. This register can be accessed to write a control word when A0 and A1 are at logic 1. This
control register is not accessible for a read operation.
Bit D7 of the control register specifies either I/O function or the Bit Set/Reset function. If bit
D7=1, bits D6-D0 determines I/O functions in various modes. If bit D7=0, Port C operates in the
Bit Set/Reset (BSR) mode. The BSR control word does not affect the functions of Port A and
Port B.

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To communicate with peripherals through the 8255, three steps are necessary:
1. Determine the address of ports A, B and C and of the control register according to the chip
select logic and address lines A0 andA1.
2. Write the control word in the control register.
3. Write I/O instructions to communicate with peripherals through Ports A, B and C.

Operating Modes

Mode 0: Simple Input or Output

In this mode, ports A, B are used as two simple 8-bit I/O ports and port C as two 4-bit ports.
Each port can be programmed to function as simply an input port or an output port. The
input/output features in Mode 0 are as follows.
1. Outputs are latched.
2. Inputs are not latched.
3. Ports don’t have handshake or interrupt capability.

Mode 1: Input or Output with Handshake

In this mode, handshake signals are exchanged between the MPU and peripherals prior
to data transfer. The features of the mode include the following:
1. Two ports (A and B) function as 8-bit I/O ports. They can be configured as either as
input or output ports.
2. Each port uses three lines from ort C as handshake signals. The remaining two lines of
Port C can be used for simple I/O operations.
3. Input and Output data are latched.
4. Interrupt logic is supported.

Mode 2: Bidirectional Data Transfer

This mode is used primarily in applications such as data transfer between two computers.
In this mode, Port A can be configured as the bidirectional port and Port B either in Mode
0 or Mode 1. Port A uses five signals from Port C as handshake signals for data transfer.

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 The remaining three signals from port C can be used either as simple I/O or as handshake
for port B.

BSR (Bit Set/Reset) Mode

The BSR mode is concerned only with the eight bits of port C, which can be set or reset by
writing an appropriate control word in the control register. A control word with bit D7 =0 is
recognized as a BSR control word, and it does not alter any previously transmitted control word
with bit D7=1; thus the I/O operations of ports A and B are not affected by a BSR control word.
In BSR mode, individual bits of port C can be used for applications such as an on/off switch.
Ports A and B are not affected by the BSR Mode.

BSR CONTROL WORD

This control word, when written in the control register, sets or resets one bit at a time,

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8251 Programmable Communication Interface

 8251A is a USART (Universal Synchronous Asynchronous Receiver Transmitter) for

serial data communication.

 Programmable peripheral designed for synchronous /asynchronous serial data

communication, packaged in a 28-pin DIP.

 Receives parallel data from the CPU & transmits serial data after conversion.

 Also receives serial data from the outside & transmits parallel data to the CPU after
conversion.

# Pin diagram

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Block diagram of the 8251 USART

Sections of 8251A

 Data Bus buffer

 Read/Write Control Logic

 Modem Control

 Transmitter

• Receiver

1. Data Bus Buffer

D0-D7 : 8-bit data bus used to read or write status, command word or data from or to
the 8251A

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 2. Read/Write Control logic
Includes a control logic, six input signals & three buffer registers: Data register,
control register & status register.
Control logic : Interfaces the chip with MPU, determines the functions of the chip
according to the control word in the control register & monitors the data flow.
Input signals
 CS – Chip Select : When signal goes low, the 8251A is selected by the MPU for
communication.
 C/D – Control/Data : When signal is high, the control or status register is addressed;
when it is low, data buffer is addressed. (Control register & status register are
differentiated by WR and RD signals)
 WR : When signal is low, the MPU either writes in the control register or sends output to
the data buffer.
 RD : When signal goes low, the MPU either reads a status from the status register or
accepts data from data buffer.
 RESET : A high on this signal reset 8252A & forces it into the idle mode.
 CLK : Clock input, usually connected to the system clock for communication with the
microprocessor.
Status register
• Checks the ready status of the peripheral.
• Status word in the status register provides the information concerning register status and
transmission errors.
Data register
 Used as an input and output port when the C/D is low

CS C/D WR RD Operation

0 0 1 0 MPU reads data from data buffer

0 0 0 1 MPU writes data from data buffer
0 1 0 1 MPU writes a word to control register
0 1 1 0 MPU reads a word from status register
1 × × × Chip is not selected for any operation

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3. Modem Control:
DSR - Data Set Ready : Checks if the Data Set is ready when communicating with a modem.
DTR - Data Terminal Ready : Indicates that the device is ready to accept data when the 8251 is
communicating with a modem.
CTS - Clear to Send : If its low, the 8251A is enabled to transmit the serial data provided the
enable bit in the command byte is set to ‘1’.
RTS - Request to Send Data : Low signal indicates the modem that the receiver is ready to
receive a data byte from the modem.

4. Transmitter section
Accepts parallel data from MPU & converts them into serial data.
Has two registers:
a. Buffer register : To hold eight bits
Output register : To convert eight bits into a stream of serial bits.
 The MPU writes a byte in the buffer register.
 Whenever the output register is empty; the contents of buffer register are transferred to
output register.
 Transmitter section consists of three output & one input signals
 TxD - Transmitted Data Output : Output signal to transmit the data to peripherals
 TxC - Transmitter Clock Input : Input signal, controls the rate of transmission.
 TxRDY - Transmitter Ready : Output signal, indicates the buffer register is empty
and the USART is ready to accept the next data byte.
TxE - Transmitter Empty : Output signal to indicate the output register is empty and
the USART is ready to accept the next data byte.
5. Receiver Section
Accepts serial data on the RxD pin and converts them to parallel data.
Has two registers :
a. Receiver input register
b. Buffer register

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 When RxD goes low, the control logic assumes it is a start bit, waits for half bit time, and
samples the line again. If the line is still low, the input register accepts the following data,
and loads it into buffer register at the rate determined by the receiver clock.
 RxRDY - Receiver Ready Output: Output signal, goes high when the USART has a
character in the buffer register & is ready to transfer it to the MPU.
 RxD - Receive Data Input : Bits are received serially on this line & converted into a
parallel byte in the receiver input register.
 RxC - Receiver Clock Input : Clock signal that controls the rate at which bits are received
by the USART.

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 Programmable. Interval timer (Intel 8253 and 8254)
 Compatible with All Intel and Most other Microprocessors and Handles Inputs from DC
to 10 MHz
 8 MHz 8254 and 10 MHz 8254-2
 The Intel 8254 is a counter/timer device designed to solve the common timing control
problems in microcomputer system design.
 It provides three independent 16-bit counters, each capable of handling clock inputs up
to 10 MHz
 Binary or BCD counting
 Single a +5V Supply and Standard Temperature Range
 Six Programmable Counter Modes and All modes are software programmable. The 8254
is a superset of the 8253.
 The 8254 uses HMOS technology and comes in a 24-pin plastic or CERDIP package.
 Used for controlling real-time events such as real-time clock, events counter, and motor
speed and direction control.

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 Counters:
 Three Counters – C1,C2 & C3
 Each 16 Bit Identical Presettable
 Down Counter Operates In BCD /Hex
 Controlled By Loading Count To Command Word Register
 “On The Fly” Reading

Control Logic:
 CS – Logic 0 – Enables 8254
 RD – Logic 0 – Tells Microprocessor Reads Count From 8254
 WR – Logic 0 – Tells Microprocessor Writes Count/ Command Into 8254
 A1,a0 – Address Input Pins To Select Modes And Counters

Data Buffers:
 8 Bit Bidirectional D0-d7 Connected To Data Bus Of Microprocessor
 In  Reads Data From Peripheral
 Out  Writes Data To Peripheral
Control Word Register:
 Accepts 8 Bit Control Word Written By Microprocessor
 Can Only Be Written ( Not Read)
 Control Word Chooses One Of The Six Modes Of Operation

CS RD WR A1 A0 OPERATION

0 1 0 0 0 Write Counter 0

0 1 0 0 1 Write Counter 1

0 1 0 1 0 Write Counter 2

0 1 0 1 1 Write Control Word

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0 0 1 0 0 Read Counter 0

0 0 1 0 1 Read Counter 1

0 0 1 1 0 Read Counter 2

0 0 1 1 1 No Operation ( Tristated )

0 1 1 X X No Operation ( Tristated )

1 X X X X 8254 Not Selected

Control Word Format

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 8254 Modes Of Operation
1. Mode 0 (Interrupt On Terminal Count )
2. Mode 1 (Programmable Monoshot )
3. Mode 2 (Rate Generator )
4. Mode 3 (Square Wave Generator )
5. Mode 4 (Software Triggered Strobe )
6. Mode 5 (Hardware Triggered Strobe )

Mode 0: Interrupt On Terminal Count

 The output becomes a logic 0 when the control word is written remains low even after
count value loaded in counter.
 Writing a count register , when previous counting is in process
first byte when loaded stops the previous count,
second byte when loaded starts new count

Mode 0: Interrupt On Terminal Count

Mode 1: One-shot mode.

 Monostablemultivibrator

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  Gate input is used as trigger input
 Output remains high till the count is loaded after application of trigger, output goes low
and remains low till count becomes zero
 Mode 1: One-shot mode

Mode 2: Rate Generator / Divide by N Counter

 When N is loaded as count  after N pulses  OUT goes low for only one clock
cycle then,
 count N is reloaded  OUT becomes high for N clock pulses
 Gate  logic 0  no counting
 Gate  logic 1  normal counting

Difference between 8253 and 8254

The following table differentiates the features of 8253 and 8254 –

8253
Its operating frequency is 0 - 2.6 MHz
It uses N-MOS technology
Read-Back command is not available
Reads and writes of the same counter cannot be
interleaved.
8254
Its operating frequency is 0 - 10 MHz
It uses H-MOS technology
Read-Back command is available
Reads and writes of the same counter can be
interleaved.

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 Mode 3: SQUARE WAVE RATE GENERATOR
1. When count N loaded is even  output remains HIGH for half the count and LOW
for the rest half of the count
2. When count N loaded is odd  output remains HIGH for (N+1)/2 and low for (N-
1)/2.
3. Repeated operation gives square wave

Mode 4: Software triggered Strobe

 After mode is set output goes high
 When count is loaded counting down starts on reaching terminal count output goes
low for only one clock cycle, and then again output goes HIGH
 The above said low pulse can be used as a strobe for interfacing MP with peripherals

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 Mode 5: Hardware triggered Strobe

 This mode generates a strobe in response to the rising edge at the trigger
 Mode is used to generate a delayed strobe in response to an externally generated signal
 Once mode is programmed and counter loaded, OUT goes HIGH
 Counter starts counting after the rising edge of the trigger (GATE)

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8279 Programmable Keyboard/Display Controller and Interfacing
The Keyboard/Display Controller 8279

Intel’s 8279 is a general purpose Keyboard Display controller that simultaneously drives the
display of a system and interfaces a Keyboard with the CPU.

Both of these functions are performed by the controller in repetitive fashion without involving
the CPU. The Keyboard is interfaced either in the interrupt or the polled mode.

Architecture and Signal Descriptions of 8279

The Keyboard display controller chip 8279 provides
1. A set of four scan lines and eight return lines for interfacing keyboards.
2. A set of eight output lines for interfacing display.

I/O Control and Data Buffer

The I/O control section controls the flow of data to/from the 8279. The data buffer interface the
external bus of the system with internal bus of 8279. the I/O section is enabled only if D is low.

8279 Internal Architecture

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Control and Timing Register and Timing Control
These registers store the keyboard and display modes and other operating conditions
programmed by CPU. The registers are written with Ao=1 and WR =0.

Scan Counter
The Scan Counter has two modes to scan the key matrix and refresh the display.In the Encoded
mode, the counter provides a binary count that is to be externally decoded to provide the scan
lines for keyboard and display (four externally decoded scan lines may drive up to 16 displays).

Return Buffers and Keyboard Debounce and Control

This section scans for a Key closure row-wise. If it is detected, the Keyboard debounce unit
debounces the key entry (i.e. wait for 10 ms). After the debounce period, if the key continues to
be detected.

FIFO/Sensor RAM and Status Logic

In Keyboard or strobed input mode, this block acts as 8-byte first-in-first-out (FIFO) RAM. Each
key code of the pressed key is entered in the order of the entry, and in the meantime, read by the
CPU, till the RAM becomes empty.

In scanned sensor matrix mode, this unit acts as sensor RAM. Each row of the sensor RAM is
loaded with the status of the corresponding row of sensors in the matrix.

Display Address Registers and Display RAM.

The Display address registers hold the addresses of the word currently being written or read by
the CPU to or from the display RAM. The contents of the registers are automatically updated by
8279 to accept the next data entry by CPU.

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RS-232

One of the oldest serial interfaces is generically called RS-232. It was originally established in
1962 as a method of connecting data terminal equipment (DTE) such as electro mechanical
teletypewriters to data communications equipment (DCE). Over the years its use has included
connections to video terminals, computers, and modems. The first personal computers included
an RS-232 called a serial port for connection to a printer or other peripheral device. Today, it is
still widely used in embedded computer development systems, scientific instruments, and all
sorts of industrial control equipment.

The standard defines the pin numbering, meaning of signals and the connectors (9-pin or 25-pin
connector). For a minimal unidirectional communication, only 2 wires are needed (TX/RX and
GND). For a bidirectional connection, at least 3 wires are needed (TX, RX and GND). RS-232
has been available on many computer system and is commonly known as ‘serial port’. Because
of the simplicity of the protocol, many embedded devices have an UARTintegrated. As the
microcontroller typically does not provide the higher voltage levels as defined in the standard, an
additional line driver as the MAX232 is needed to communicate with devices over a larger
distance.

Comparison Table

USB RS-232

Wires 4 2-10

Communication Protocol standard only low level defined

Connector footprint small large

Power yes no

Software stack size large small

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Handshaking built-in only with CTS/RTS wires

Interoperability yes no

Multi-Device connections yes (hub) not defined

IEEE-488 INTERFACE BUS (HP-IB/GP-IB)

The IEEE-488 Interface Bus (HP-IB) or general purpose interface bus (GP-IB) was developed to
provide a means for various instruments and devices to communicate with each other under the
direction of one or more master controllers. The HP-IB was originally intended to support a wide
range of instruments and devices, from the very fast to the very slow

A device may be capable of any other three types of functions: controller, listener, or talker. A
device on the bus may have only one of the three functions active at a given time. A controller
directs which devices will be talkers and listeners. The bus will allow multiple controllers, but
only one may be active at a given time. Each device on the bus should have a unique address in
the range of 0-30. The maximum length of the bus network is limited to 20 meters total
transmission path length.

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