EC-203VHDL Tutorial PDF

VHDL tutorial
EC-203 Digital electronics

Introduction
• Very High Speed Integrated Circuit Hardware
Description Language (VHDL)
• Project in Mid 1908s by US Dept of defence & IEEE
• To develop platform for design and development of
high speed and complex (large no. of gates) Ics
• Other competitors – Verilog (also popular) and ABEL
(no so popular)
• HDL are meant to emulate behavior of digital circuit
real time
• Allows both (concurrent and sequential execution of
statements) along with timing specifications (gate
delays)
2 EC242, Dr. SanjeeV Manhas, E&CE IIT Roorkee
Different levels of abstractions
Design abstraction levels in digital circuits

• Abstraction is hiding of
details: Differentiation
between essential and
nonessential information
• Creation of abstraction levels:
On every abstraction level
only the essential information
is considered, nonessential
information is left out

Different levels of abstractions
Behavioral, Structural,
and Physical levels
VHDL allows one to describe a digital

system at the structural or the behavioral
level

Abstraction Levels in IC Design
• Behavior model : functional description of the module is outlined at

the behavioral level
• RTL: design is divided into combinational logic and storage
elements with storage elements controlled by a system clock
• Logic - design is represented as a netlist with logic gates (AND,
OR, NOT,) and storage elements
• Layout - different cells of target technology are placed on the chip
and the connections are routed

Abstraction levels and VHDL
• Design entry in behavioural and RTL is usually done by text editors

Description of Abstraction Levels

RTL and gate level
Behavioral or Register
transfer level
functional behavior is modeled
with so called combinational
and clocked processes
Structural or Gate level- list

of the gates (components) that
are used in the design

Typical high-density FPGA design flow

Behavioral description
• Behavioral is highest level of
abstraction • Behavioral descriptions can be
• Describes a system in terms of Data flow and Algorithmic
what it does or how it behaves • Dataflow representation describes
how data moves through the
• Specifies relation between input
system
and output signals
• Eg data flow between registers
• Behavioral description is abstract (Register Transfer level or RTL)
• Data flow model uses concurrent
statements executed in parallel as
soon as data arrives at the input
eg XOR gate : S = AB

Eg Car passenger Buzzer:
Warning = Ignition_on AND ( Door_open OR Seatbelt_off)

Structural
• Describes system as Structural representation of a “buzzer”
collection of gates and circuit
components
interconnected to perform
a function
• Similar to schematic of
interconnected logic gates

Basic Structure of a VHDL file
• In VHDL a digital system is an entity

• An entity can contain other entities
• Entity modeled by an entity
declaration and an architecture body
• Entity declaration defines interface to
outside by declaring input and output
signals
• Architecture is description of the entity
and is composed of interconnected
entities, processes and components, all
operating concurrently

VHDL syntax main features
• VHDL uses reserved keywords that cannot be

used as signal names or identifiers
• Keywords along with user-defined identifiers are
case insensitive
• VHDL is strongly typed language i.e. must declare
type of every object that can have a value, such as
signals, constants and variables
• Comments start with --
• Ignores line breaks and extra spaces

Entity declaration
Entity declaration defines the NAME of the entity and lists
the input and output ports
entity NAME_OF_ENTITY is [ generic generic declarations);]

port (signal_names: mode type;
signal_names: mode type;
:
signal_names: mode type); Signal type
end [NAME_OF_ENTITY] ;
Signal direction:
input/output/both etc.
-- comments: example of the buzzer circuit
entity BUZZER is
port (DOOR, IGNITION, SBELT: in std_logic;
WARNING: out std_logic);
end BUZZER;

Entity description
• The NAME_OF_ENTITY is a user-selected identifier
• signal names consists of a comma separated list of one or more user-selected identifiers
that specify external interface signals.
• mode: is one of the reserved words to indicate the signal direction:
1. in – indicates that the signal is an input
2. out – indicates that the signal is an output of the entity whose value can only be
read by other entities that use it.
3. buffer – indicates that the signal is an output of the entity whose value can be read
inside the entity’s architecture
4. inout – the signal can be an input or an output.
• type: a built-in or user-defined signal type. The type defines the set of values an object can
have. Examples of types are bit, bit_vector, Boolean, character, std_logic, and std_ulogic.
1. bit – can have the value 0 and 1
2. bit_vector – is a vector of bit values (e.g. bit_vector (0 to 7)
3. std_logic, std_ulogic, std_logic_vector, std_ulogic_vector: can have 9 values to indicate
the value and strength of a signal. Std_ulogic and std_logic are preferred over the bit
or bit_vector types.
4. boolean – can have the value TRUE and FALSE
5. integer – can have a range of integer values
6. real – can have a range of real values
7. character – any printing character
8. time – to indicate time

Entity declaration examples
generic: optional declarations and determine local constants used for timing and sizing (e.g.
bus widths) the entity. Generic can have a default value. Syntax:
generic (
constant_name: type [:=value] ;
constant_name: type [:=value] ;
:
constant_name: type [:=value] );
entity dff_sr is
port (D,CLK,S,R: in std_logic;
Q,Qnot: out std_logic-);
end dff_sr;
entity mux4_to_1 is
port (I0,I1,I2,I3: in std_logic_vector(7 downto 0);
SEL: in std_logic_vector (1 downto 0);
OUT1: out std_logic-_vector(7 downto 0));
end mux4_to_1;
• The type defines the set of values an object can have

• std_logic type is defined in the std_logic_1164 package of the IEEE library

Architecture body
• Specifies how the circuit operates and how it is implemented
• Entity or circuit can be specified in a variety of ways, such as behavioral,
structural (interconnected components), or a combination of the above
Architecture body
architecture architecture_name of NAME_OF_ENTITY is
-- Declarations
-- components declarations
-- signal declarations
-- constant declarations
-- function declarations
-- procedure declarations
-- type declarations
begin
-- Statements
end architecture_name;

Behavioral model
Behavioral model of Buzzer circuit
Architecture behavioral is associated with
entity, BUZZER
architecture behavioral_Buzz of BUZZER is
begin main body of the architecture starts
WARNING <= (not DOOR and IGNITION) or (not SBELT and IGNITION);
end behavioral;
Boolean expression of the function
“<= ” assignment operator, assign value of expression
on the right to signal on left
-- An example of a two-input XNOR gate (entity + architecture)

entity XNOR2 is
port (A, B: in std_logic;
Z: out std_logic);
end XNOR2;
architecture behavioral_xnor of XNOR2 is

-- signal declaration (of internal signals
• Signal X, Y)
assignment statements in architecture body uses
signal X, Y: std_logic;
begin
operators (eg and, or, not, <= etc..) and are concurrent
X <= A and B; • Concurrent statements: Eg if A changes, signals X and Y
Y <= (not A) and (not B); change values that in turn causes the last statement to update
Z <= X or Y; the output Z
End behavioral_xnor;
• Digital systems are data-driven (data flow) and an
event/change which occurs on one signal will lead to an event
on another signal
• Order in which these statements are given does not matter
• Contrast this to conventional, software programs that execute
18 EC242, Dr. SanjeeV Manhas,
statements inE&CE IIT Roorkeeflow
a sequential
Structural description
Describes the system as set of gates appropriately interconnected
architecture structural of BUZZER is Buzzer entity declaration same earlier
-- Declarations
component AND2
port (in1, in2: in std_logic; declarative part that gives
out1: out std_logic); the components (gates)
end component; that are going to be used
component OR2
port (in1, in2: in std_logic;
out1: out std_logic); Schematic
end component;
component NOT1
port (in1: in std_logic;
out1: out std_logic);
end component;
-- declaration of signals used to interconnect gates
signal DOOR_NOT, SBELT_NOT, B1, B2: std_logic; Concurrent statements
An alternative
begin way to define net list using explicit association between the ports executed in parallel and
-- Component instantiations statements and how they are connected hence order does not
U0: component-name
label: NOT1 port map (DOOR, DOOR_NOT);
port map (port1=>signal1, port2=> signal2,… port3=>signaln);
U1: NOT1 port map (SBELT, SBELT_NOT); Key word port mapmatter
defines how the
U2: AND2 port map (IGNITION, DOOR_NOT, B1); components are connected
U0: NOT1 port map (in1 => DOOR, out1 => DOOR_NOT);
U3: AND2 port map (IGNITION, SBELT_NOT, B2);
U1:
U4: NOT1 portmap
OR2 port map (in1
(B1, B2,=> SBELT, out1 => SBELT_NOT);
WARNING);
U2: AND2 port map (in1 => IGNITION, in2 => DOOR_NOT, out1 => B1);
U3:end
AND2 port map (in1 => IGNITION, in2 => SBELT_NOT, B2);
structural;
U4: OR2 port map (in1 => B1, in2 => B2, out1 => WARNING);
Hierarchical design with structural modeling
- 4-bit adder example
sum = (A B)  C
carry = AB + C(A  B)
Define single full adder
-- Example of a four bit adder

library ieee; • Library and use clause
use ieee.std_logic_1164.all;
-- definition of a full adder
• defined a component for the full adder
entity FULLADDER is
port (a, b, c: in std_logic;
sum, carry: out std_logic);
end FULLADDER;
architecture fulladder_behav of FULLADDER is
begin
sum <= (a xor b) xor c ;
carry <= (a and b) or (c and (a xor b));
end fulladder_behav;

Architecture of full adder
-- 4-bit adder
library ieee;
entity FOURBITADD is
port (a, b: in std_logic_vector(3 downto 0);
Cin : in std_logic;
sum: out std_logic_vector (3 downto 0);
Cout, V: out std_logic);
end FOURBITADD;
• Library and use clause
architecture fouradder_structure of FOURBITADD is • defined a component for
signal c: std_logic_vector (4 downto 0); the full adder
component FULLADDER •Four instantiations of
port(a, b, c: in std_logic;
the full adder to build
end component; the structure of the 4-
begin bit adder
FA0: FULLADDER
port map (a(0), b(0), Cin, sum(0), c(1));
FA1: FULLADDER
port map (a(1), b(1), C(1), sum(1), c(2));
FA2: FULLADDER
port map (a(2), b(2), C(2), sum(2), c(3));
FA3: FULLADDER
port map (a(3), b(3), C(3), sum(3), c(4));
V <= c(3) xor c(4);
Cout <= c(4);
end fouradder_structure;
Lexical Elements
• Identifiers - are user-defined words used to name objects in VHDL models
– May contain only alpha-numeric characters (A to Z, a to z, 0-9) and the underscore (_)
character
– The first character must be a letter and the last one cannot be an underscore.
– An identifier cannot include two consecutive underscores.
– An identifier is case insensitive (ex. And2 and AND2 or and2 refer to the same object)
– An identifier can be of any length.
– Valid identifer: X10, x_10, My_gate1
– Some invalid identifiers are: _X10, my_gate@input, gate-input.
• Keywords (Reserved words): eg entity, architecture, component
• Numbers
– Integer literals: 12 10 256E3, Real literals: 1.2 256.24 3.14E-2,
– Base different from the base “10”, one uses the following convention: base#number# Eg:
Base 2: 2#10010# (representing the decimal number “18”), Base 16: 16#12#
• Characters, Strings and Bit Strings
– character literal : „f‟. „A‟
– string of characters: “hello world”
– bit-string: Binary: B”1100_1001”, b”1001011”, Hexagonal: X”C9”, X”4b”, ctal: O”311”,
o”113”

Data Objects: Signals, Variables and Constants
• Data object created by object declaration and has value and type
• Variables and Constants used in processes, procedures and functions
• Constant: declared at the beginning of a architecture or process
– A value of a given type and cannot be changed during the simulation
– constant list_of_name_of_constant: type [ := initial value] ; constant RISE_FALL_TME:
time := 2 ns;
• Variable: single value which can be updated by assignment statement in architecture or process
– variable list_of_variable_names: type [ := initial value] ;
– variable VAR1: boolean :=FALSE; variable STS_BIT: bit_vector (7 downto 0); variable
SUM: integer range 0 to 256 :=16;
– updated using a variable assignment statement : Variable_name := expression;
• Signal: Signals are declared outside process using following statement:
– signal list_of_signal_names: type [ := initial value] ;
– signal SUM, CARRY: std_logic; signal DATA_BUS: bit_vector (0 to 7);
– Updated when their signal assignment statement : SUM <= (A xor B) after 2 ns; multiple
values : wavefrm <= „0‟, „1‟ after 5ns, „0‟ after 10ns, „1‟ after 20 ns;
• Variable changes instantaneously when variable assignment is executed
• Signal change a delay when assignment expression is evaluated, if no delay is specified, the
signal will change after a delta (a unit delay time) delay

Data types
• Each data object has type associated with it
• VHDL strongly typed - requires each object to be of a
certain type
• Four classes of data types: scalar, composite, access
and file types
• Scalar type includes integer, real, and enumerated
types of Boolean and Character

Standard package data types
Predefined types in the standard
package accessed using:
library std, work;

use std.standard.all;

Defined data types
• User type: Define new data types using declaration, which names the type and its value
range
– type identifier is type_definition;
– type my_word_length is range 31 downto 0;
– type cmos_level is range 0.0 to 3.3;
– type conductance is range 0 to 2E-9; units mho; end units conductance;
• Enumerated Types
– enumerated type consists of lists of character literals or identifiers
– type type_name is (identifier list or character literal);
signal SIG1: my_3values;

variable ALU_OP: pc_oper;
variable first_digit: hex_digit :=‟0‟;
signal STATE: state_type :=S2;

Defined data types
Composite Types: Array and Record – a collection of related data elements in the form of an array or record
Array Type - syntax type array_name is array (indexing scheme) of element_type;
type MY_WORD is array (15 downto 0) of std_logic;
type YOUR_WORD is array (0 to 15) of std_logic;
type YOUR_MATRIX4X2 is array (1 to 4, 1 to 2) of integer;
variable DATA_ARR: MY_MATRIX :=((0,2), (1,3), (4,6), (5,7));
Record Type – A record consists of multiple elements that may be

of different types. Syntax
type name is
record
identifier :subtype_indication;
:
identifier :subtype_indication;
end record;
Eg
type MY_MODULE is
record
RISE_TIME :time;
FALL_TIME : time;
SIZE : integer range 0 to 200;
DATA : bit_vector (15 downto 0);
end record;
signal A, B: MY_MODULE
A.RISE_TIME <= 5ns;
A.SIZE <= 120;

Type conversion
• Since VHDL is strongly typed language - To allow assigning data between objects of
different types, one needs to convert one type to the other
Syntax
type_name (expression);
entity QUAD_NAND2 is
port (A, B: in bit_vector(3 downto 0);
out4: out std_logic_vector (3 downto 0));
end QUAD_NAND2;
architecture behavioral_2 of QUAD_NAND2 is

begin
out4 <= to_StdLogicVector(A and B);
end behavioral_2;
Conversions supported by std_logic_1164 package

Conversion Function
std_ulogic to bit to_bit(expression)
std_logic_vector to bit_vector to_bitvector(expression)
std_ulogic_vector to bit_vector to_bitvector(expression)
bit to std_ulogic To_StdULogic(expression)
bit_vector to std_logic_vector To_StdLogicVector(expression)
bit_vector to std_ulogic_vector To_StdUlogicVector(expression)
std_ulogic to std_logic_vector To_StdLogicVector(expression)
std_logic to std_ulogic_vector To_StdUlogicVector(expression)

Attributes
• Used to return various types of information about signal, variable or type
• Consist of quote mark („) followed by attribute name
Signal attributes
Attribute Function
signal_name’event returns the Boolean value True if an event on the
Example signal attribute
signal occurred, otherwise gives a False if (CLOCK‟event and CLOCK=‟1‟) then …
signal_name’active returns the Boolean value True there has been a
transaction (assignment) on the signal, otherwise
gives a False Others:
signal_name’transaction returns a signal of the type “bit” that toggles (0 to 1
or 1 to 0) every time there is a transaction on the Scalar attributes
signal. Array attributes
signal_name’last_event returns the time interval since the last event on the
signal
signal_name’last_active returns the time interval since the last transaction on
the signal
signal_name’last_value gives the value of the signal before the last event
occurred on the signal
signal_name’delayed(T) gives a signal that is the delayed version (by time T)
of the original one. [T is optional, default T=0]
signal_name’stable(T) returns a Boolean value, True, if no event has
occurred on the signal during the interval T,
otherwise returns a False. [T is optional, default T=0]
signal_name’quiet(T) returns a Boolean value, True, if no transaction has

occurred on the signal during the interval T,
otherwise returns a False. [T is optional, default T=0]

Operators
VHDL supported operators that operate on signals, variables and constants
Class
lowest
1. Logical operators and or nand nor xor xnor
Operator precedence
2. Relational operators = /= < <= > >=
3. Shift operators sll srl sla sra rol ror
4.Addition operators + = &
5. Unary operators + -
6. Multiplying op. * / mod rem
7. Miscellaneous op. ** abs not
highest

Logic operators
• Operate on “bit”, “boolean”, “std_logic” and
“std_ulogic” types and their vectors
• Define Boolean logic expression or to perform bit-by-
bit operations on arrays of bits
• nand and nor operators are not associative
• X nand Y nand Z will give a syntax error and should
be written as (X nand Y) nand Z.

Shift operators
• Perform a bit-wise shift or rotate operation on a one-dimensional array of
elements of the type bit (or std_logic) or Boolean
Opera Description Operand Result variable A: bit_vector :=”101001”;

tor Type Type
sll Shift left logical (fill Left: Any one- Same as left
A sll 2 results in “100100”
right vacated bits dimensional array type A srl 2 results in “001010”
with the 0) type with elements of A sla 2 results in “100111”
type bit or Boolean; A sra 2 results in “111010”
Right: integer
A rol 2 results in “100110”
srl Shift right logical same as above Same as left A ror 2 results in “011010”
(fill left vacated bits type
with 0)
sla Shift left arithmetic same as above Same as left
(fill right vacated type
bits with rightmost
bit)
sra Shift right same as above Same as left
arithmetic (fill left type
vacated bits with
leftmost bit)
rol Rotate left (circular) same as above Same as left
type
ror Rotate right same as above Same as left
(circular) type

Addition operators
• Perform arithmetic operation (addition and subtraction) on operands of any
numeric type
• To use these operators specify the ieee.std_logic_unsigned.all or
std_logic_arith package package in addition to the ieee.std_logic_1164
package in VHDL code
Operator Description Left Operand Type Right Operand Type Result Type
+ Addition Numeric type Same as left operand Same type
- Subtraction Numeric type Same as left operand Same type
& Concatenation Array or element type Same as left operand Same array
type

Unary operators
• “+” and “-“ are used to specify the sign of a numeric type
Operator Description Operand Type Result Type

+ Identity Any numeric type Same type
- Negation Any numeric type Same type

Multiplying operators
• perform mathematical functions on integer or floating point
Operator Descriptio Left Operand Right Operand Result Type
n Type Type
Any integer or Same type Same type
* Multiplicatio floating point
n
Any physical type Integer or real type Same as left
Any integer or real Any physical type Same as right
type
/ Division Any integer or Any integer or Same type
floating point floating point
Any physical type Any integer or real t Same as left
ype
Any physical type Same type Integer
mod Modulus Any integer type Same type
rem Remainder Any integer type Same type
A rem B = A –(A/B)*B (in which A/B in an integer) 11 rem 4 results in 3

A mod B = A – B * N (in which N is an integer) (-11) rem 4 results in -3
9 mod 4 results in 1
7 mod (-4) results in –1 (7 – 4*2 = -1).

Miscellaneous operators
• Absolute value and exponentation operators that can be
applied to numeric types
Operator Description Left Right Result

Operand Operan Type
Type d Type
** Exponentiation Integer type Integer Same as left
type
Floating point Integer Same as left
type
abs Absolute value Any numeric type Same type
not Logical negation Any bit or Boolean type Same type

Relational operators
• Test the relative values of two scalar types and give as result a
Boolean output of “TRUE” or “FALSE”.
Operator Description Operand Types Result Type

= Equality any type Boolean
/= Inequality any type Boolean
< Smaller than scalar or discrete array types Boolean
<= Smaller than scalar or discrete array types Boolean
or equal
> Greater than scalar or discrete array types Boolean
>= Greater than scalar or discrete array types Boolean
or equal
variable STS : Boolean;

constant A : integer :=24;
constant B_COUNT : integer :=32;
constant C : integer :=14;
STS <= (A < B_COUNT) ; -- will assign the value “TRUE” to STS
STS <= ((A >= B_COUNT) or (A > C)); -- will result in “TRUE”
STS <= (std_logic („1‟, „0‟, „1‟) < std_logic(„0‟, „1‟,‟1‟));--makes STS “FALSE”

Behavioral Modeling: Sequential Statements
• Modeling levels in VHDL - behavioral and structural
• Behavioral modeling can be done with sequential statements using the process
construct or with concurrent statements
• Behavior of components and circuits with sequential statements/modeling using
process construct
• Particularly useful for sequential circuits such as state machines
• Process statement is the main construct in behavioral modeling allowing use of
sequential statements to describe behavior of system over time
[process_label:] process [ (sensitivity_list) ] [is] Any change in the value of the signals in
[ process_declarations] the sensitivity list will cause immediate
begin execution of the process – process
list of sequential statements such as: statement in itself is concurrent
signal assignments
variable assignments
case statement
exit statement
if statement Flow control statement as with
loop statement conventional programming
next statement languages eg C
null statement
procedure call
wait statement
end process [process_label];
process example – sequential circuit
• Positive edge-triggered D flip-flop
library ieee;
entity DFF_CLEAR is
port (CLK, CLEAR, D : in std_logic;
Q : out std_logic);
end DFF_CLEAR;
architecture BEHAV_DFF of DFF_CLEAR is

Process declaration within architecture
begin
is concurrent statement
DFF_PROCESS: process (CLK, CLEAR)
begin
if (CLEAR = „1‟) then Control flow statements
Q <= „0‟; inside a process are
elsif (CLK‟event and CLK = „1‟) then executed sequentially
Q <= D;
end if; Checks for a
end process; positive clock
end BEHAV_DFF; edge
Process reads and writes signals and values of input and output ports (CLK, CLEAR, D) to
communicate with the rest of the architecture

Combinational circuits with the process construct – full
adder example
library ieee;
entity FULL_ADDER is
port (A, B, Cin : in std_logic;
Sum, Cout : out std_logic);
end FULL_ADDER;
architecture BEHAV_FA of FULL_ADDER is

signal int1, int2, int3: std_logic;
begin Half adder
-- Process P1 for first half adder S_ha = (AÅB) and C_ha = AB
P1: process (A, B) For the Full Adder
begin Sum = (AÅB)ÅCin = S_ha ÅCin
int1<= A xor B; Cout = (AÅB)Cin + AB = S_ha.Cin + C_ha
int2<= A and B;
end process;
-- Process P2 for second half adder and OR ate
P2: process (int1, int2, Cin)
begin
Sum <= int1 xor Cin;
int3 <= int1 and Cin;
Cout <= int2 or int3;
end process;
end BEHAV_FA;

Sequential statements (control execution flow)
• IF Statement – conditional multi-optional execution

• CASE Statement – Decide what option to run based
on expression value
• FOR Loops – run a loop multiple number of time
based on an expression value
• WAIT Statement – wait for something to occur to
execute statements

if statement
• Executes a sequence of statements whose sequence depends on
one or more conditions
Example 4x1 Multiplexer

entity MUX_4_1a is
if condition then
port (S1, S0, A, B, C, D: in std_logic;
sequential statements
Z: out std_logic);
[elsif condition then
end MUX_4_1a;
sequential statements ]
architecture behav_MUX41a of MUX_4_1a is
[else
begin
sequential statements ] P1: process (S1, S0, A, B, C, D)
end if;
if S1=‟0‟ and S0=‟0‟ then
Z <= A;
condition is a Boolean expression elsif S1=‟0‟ and S0=‟1‟ then
Z <= B;
elsif S1=‟1‟ and S0=‟0‟ then
Z <= C;
elsif S1=‟1‟ and S0=‟1‟ then
Z <= D;
end if;

case statement
• Depending on value of a single expression case statement executes one of
several sequences of statements
case expression is Example 4x1 MUX

when choices =>
sequential statements entity MUX_4_1 is
when choices => port ( SEL: in std_logic_vector(2 downto 1);
sequential statements A, B, C, D: in std_logic;
-- branches are allowed Z: out std_logic);
end MUX_4_1;
[when others => sequential statements]
architecture behav_MUX41 of MUX_4_1 is
end case;
begin
PR_MUX: process (SEL, A, B, C, D)
begin
• Expression must evaluate to an integer, an case SEL is
when “00” => Z <= A;
enumerated type of a one-dimensional when “01” => Z <= B;
array, such as a bit_vector when “10” => Z <= C;
• No two choices can overlap when “11” => Z <= D;
• if the “when others" choice is not present, when others => Z <= „X‟;
all possible values of the expression must end case;
be covered by the set of choices. end process PR_MUX;
end behav_MUX41;

loop statements
• Repeatedly execute a sequence of sequential statements
• Three types of loops
[loop_label :]iteration_scheme loop
– basic loop sequential statements
– while … loop [next [label] [when condition];
– for … loop [exit [label] [when condition];
end loop [loop_label];
Basic loop to implement a counter that counts from 0 to 31
entity COUNT31 is
port ( CLK: in std_logic;
COUNT: out integer);
end COUNT31;
architecture behav_COUNT of COUNT31 is
begin
P_COUNT: process When COUNT
variable intern_value: integer :=0; reaches 31, it will
begin start over from 0
COUNT <= intern_value;
loop
wait until CLK=‟1‟;
intern_value:=(intern_value + 1) mod 32;
COUNT <= intern_value;
end loop;
end process P_COUNT;
end behav_COUNT;
while and for loop statements
• Evaluates a Boolean condition – if TRUE, the loop repeats, else
loop is skipped and the execution stops
[ loop_label :] while condition loop
[next [label] [when condition];
[exit [label] [when condition];
end loop[ loop_label ];
• For loop uses an integer iteration scheme that determines the

number of iterations
[ loop_label :] for identifier in range loop

[next [label] [when condition];
[exit [label] [when condition];
end loop[ loop_label ];
Where range in one of the following forms:

integer_expression to integer_expression
integer_expression downto integer_expression

wait and null statement
• Wait will halt a process until an event occurs
wait until signal = value;
wait until signal’event and signal = value;
wait until not signal’stable and signal = value;
Examples • Note that process that contains a

wait until CLK=‟1‟; wait statement can not have a
wait until CLK=‟0‟;
sensitivity list
wait until CLK‟event and CLK=‟1‟;
wait until not CLK‟stable and CLK=‟1‟;
• Null statement - no action will occur

• Useful in a case statement where all choices must be covered
P_WAIT: process (CNTL)
begin
Z <=A;
case CNTL is
when 3 | 15 =>
Z <= A xor B;
when others =>
null;
end case;
end process P_WAIT;
Behavioral description– dataflow/concurrent modeling
• Modeling using concurrent statements – the dataflow model
• Dataflow modeling describes a circuit in terms of its
function and the flow of data through circuit
• Dataflow model is DIFFERENT from the structural
modeling that describes a circuit in terms of the
interconnection of components
• Remember that concurrent signal assignments are event
triggered and executed as soon as an event on one of the
signals occurs

Simple Concurrent signal assignments
• Target_signal <= expression;
• As soon an event occurs on one of the signal
expression is evaluated and transferred to target
signal
• Target_signal has to be the same as the type of the
value of the expression
Sum <= (A xor B) xor Cin;
Carry <= (A and B);
Z <= (not X) or Y after 2 ns;

Conditional Signal assignments
A general scheme
Target_signal <= expression when Boolean_condition else

expression when Boolean_condition else
:
expression;
entity MUX_4_1_funcTab is
port (A, B, C, D: in std_logic;
SEL: in std_logic_vector (1 downto 0);
Z: out std_logic);
end MUX_4_1_ funcTab;
architecture concurr_MUX41 of MUX_4_1_ funcTab is
begin
Z <= A when SEL = ”00” else
B when SEL = ”01” else
C when SEL = “10” else
D;
end concurr_MUX41;

Selected Signal assignments
• Variant of conditional signal assignment
with choice_expression select
target_name <= expression when choices,
target_name <= expression when choices,
:
target_name <= expression when choices;
Example 4x1 MUX

entity MUX_4_1_Conc2 is
port (A, B, C, D: in std_logic;
SEL: in std_logic_vector(1 downto 0);
Z: out std_logic);
end MUX_4_1_Conc2;
architecture concurr_MUX41b of MUX_4_1_Conc2 is
begin
with SEL select
Z <= A when “00”,
B when “01”,
C when “10”,
D when “11”;
end concurr_MUX41b;

Structural Modeling
• Describes a circuit in terms of components and their interconnection
– kind of schematic description
• A component is assumed to defined earlier (e.g. in package) and
can be described as structural, a behavioral or dataflow model
• Lowest hierarchy in each component described as a behavioral
model, using the basic logic operators defined in VHDL
• Structural modeling good to describe complex digital systems,
through a set of components in a hierarchical fashion
• Structural description consists of
– Declaring components and signals within architecture body
– Declaring a list of components being used
– Declaring signals which define the nets that interconnect components
– Labeling multiple instances of the same component so that each
instance is uniquely defined

Structure description
• Component declaration has to be done either in the architecture body or in
the package declaration
• General syntax
architecture architecture_name of NAME_OF_ENTITY is
-- Declarations
component declarations
signal declarations
begin
-- Statements
component instantiation and connections
:
end architecture_name;
• Component name refers to either name of entity
defined in library or entity explicitly defined in the
• Component declaration VHDL file
component component_name [is] • Interface ports similar to entity declaration
[port (port_signal_names: mode type; • Use library and use clause for components
port_signal_names: mode type; declared in package library
:
port_signal_names: mode type);]
-- example fulladder
end component [component_name];
component FULLADDER
port(a, b, c: in std_logic;
end component;

Component Instantiation and interconnections
• A component instantiation statement references a

previously declared component
• Syntax
instance_name : component name
port map (port1=>signal1, port2=> signal2,… port3=>signaln);
or
• Should be in same
port map (signal1, signal2,…signaln);
order

a b
• Structural description of 4 bit adder
sum
FULLA c as hierarchical model with
carry DDER FULLADDER component
instantiations
• Behavioral description of full

adder in dataflow model
(concurrent statements) Defined
already
4 bit adder example

Further reading
• http://esd.cs.ucr.edu/labs/tutorial/
• http://www.vhdl-online.de/tutorial/
• http://www.seas.upenn.edu/~ese171/vhdl/vhd
l_primer.html
• A VHDL PRIMER By J BHASKAR, Pearson
India
• www.xilinx.com
• Digital design by Wakerly 4th ed, Pearson
India

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VHDL tutorial

EC-203 Digital electronics

Design abstraction levels in digital circuits

3 EC242, Dr. SanjeeV Manhas, E&CE IIT Roorkee

VHDL allows one to describe a digital

4 EC242, Dr. SanjeeV Manhas, E&CE IIT Roorkee

• Behavior model : functional description of the module is outlined at

5 EC242, Dr. SanjeeV Manhas, E&CE IIT Roorkee

• Design entry in behavioural and RTL is usually done by text editors

6 EC242, Dr. SanjeeV Manhas, E&CE IIT Roorkee

7 EC242, Dr. SanjeeV Manhas, E&CE IIT Roorkee

Structural or Gate level- list

8 EC242, Dr. SanjeeV Manhas, E&CE IIT Roorkee

9 EC242, Dr. SanjeeV Manhas, E&CE IIT Roorkee

eg XOR gate : S = AB

10 EC242, Dr. SanjeeV Manhas, E&CE IIT Roorkee

11 EC242, Dr. SanjeeV Manhas, E&CE IIT Roorkee

• In VHDL a digital system is an entity

12 EC242, Dr. SanjeeV Manhas, E&CE IIT Roorkee

• VHDL uses reserved keywords that cannot be

13 EC242, Dr. SanjeeV Manhas, E&CE IIT Roorkee

entity NAME_OF_ENTITY is [ generic generic declarations);]

14 EC242, Dr. SanjeeV Manhas, E&CE IIT Roorkee

15 EC242, Dr. SanjeeV Manhas, E&CE IIT Roorkee

• The type defines the set of values an object can have

16 EC242, Dr. SanjeeV Manhas, E&CE IIT Roorkee

17 EC242, Dr. SanjeeV Manhas, E&CE IIT Roorkee

-- An example of a two-input XNOR gate (entity + architecture)

architecture behavioral_xnor of XNOR2 is

Define single full adder

-- Example of a four bit adder

20 EC242, Dr. SanjeeV Manhas, E&CE IIT Roorkee

22 EC242, Dr. SanjeeV Manhas, E&CE IIT Roorkee

23 EC242, Dr. SanjeeV Manhas, E&CE IIT Roorkee

24 EC242, Dr. SanjeeV Manhas, E&CE IIT Roorkee

library std, work;

25 EC242, Dr. SanjeeV Manhas, E&CE IIT Roorkee

signal SIG1: my_3values;

26 EC242, Dr. SanjeeV Manhas, E&CE IIT Roorkee

Record Type – A record consists of multiple elements that may be

27 EC242, Dr. SanjeeV Manhas, E&CE IIT Roorkee

architecture behavioral_2 of QUAD_NAND2 is

Conversions supported by std_logic_1164 package

28 EC242, Dr. SanjeeV Manhas, E&CE IIT Roorkee

signal_name’quiet(T) returns a Boolean value, True, if no transaction has

29 EC242, Dr. SanjeeV Manhas, E&CE IIT Roorkee

30 EC242, Dr. SanjeeV Manhas, E&CE IIT Roorkee

31 EC242, Dr. SanjeeV Manhas, E&CE IIT Roorkee

Opera Description Operand Result variable A: bit_vector :=”101001”;

32 EC242, Dr. SanjeeV Manhas, E&CE IIT Roorkee

33 EC242, Dr. SanjeeV Manhas, E&CE IIT Roorkee

Operator Description Operand Type Result Type

34 EC242, Dr. SanjeeV Manhas, E&CE IIT Roorkee

A rem B = A –(A/B)*B (in which A/B in an integer) 11 rem 4 results in 3

35 EC242, Dr. SanjeeV Manhas, E&CE IIT Roorkee

Operator Description Left Right Result

36 EC242, Dr. SanjeeV Manhas, E&CE IIT Roorkee

Operator Description Operand Types Result Type

variable STS : Boolean;

37 EC242, Dr. SanjeeV Manhas, E&CE IIT Roorkee

architecture BEHAV_DFF of DFF_CLEAR is

39 EC242, Dr. SanjeeV Manhas, E&CE IIT Roorkee

architecture BEHAV_FA of FULL_ADDER is