Module-1

1. Discuss the economics of using ASICs in product.

2. What is ASIC library? What is need of Library?
3. What is testbench?
4. What is logic level optimization?
5. How full custom ASIC is different from Semi-custom ASIC?
6. Explain the different steps in ASIC design flow.
7. Write the features of EDA tools.
8. Explain Gate Array based ASICs. State types of Masked Gate Array ASICs.
9. What are optimization targets of logic synthesis.
10.Compare different ASIC technologies.
11.Write a VHDL code for a sequence detector, which detects the sequence '1011'
using Mealy machine.

Module-2

1. Explain timing driven floor planning and placement design flow.

2. Explain the final routing steps in ASIC design.
3. Discuss different CAD tool features.
4. Which method is most widely used in K L algorithm in system partition steps?
5. Explain the concept of Design Reuse.
6. Classify the placement algorithms. Explain the min-cut algorithm with Which
Sources the help of example.
7. What are goals and objectives for each ASIC physical design steps?
8. Which sources makes power dissipation in CMOS ASIC design?Why?
9. What are objectives of partioning for ASIC design?
10.How delay is minimize in content to time driven placement method?
11.What is parameter extraction pertaining to ASIC design?
12.Write a VHDL code for 8:1 Muultiplexer using Architecture.

Module-3

1. What is role of different capacitances in ASIC library design?

2. Explain different SI issues in ASIC design.
3. What are the challenges in Mixed mode design and simulation?
4. Consider the RC network given below :
a. Calculate the Elmore�s delay from In to Out 1 and from In to Out 2. Which
one is critical Path?
b. Assume R = 100? and C = 10 pF, Calculate the Elmore�s delay of the
critical path found in part 1.
5. Explain the concept of pre and post estimation delay in timing analysis?
6. What is fault path detection?
7. Explain the different timing parameters for static timing analysis.
8. Define channel density and elmore's delay.
9. Difference between static and dynamic sensitizable path.
10.Explain concept of transistors as resistors with example of CMOS inverter.
11.How delay calculation is done in static timing analysis?
12.Which design tool is more preferable to solve the SI problem?

Module-4

1. What is Partial Test?

2. Write short note on
i) JTAG
ii) BILBO
iii) Fault Models
3. What are practical aspects of mix analog digital design?
4. Explain the Synthesis process in detail.
5. Explain self test with example.
6. What are the different testing approaches for mixed signal Analog and Digital
Circuits?
7. Explain mixed signal ASIC design.
8. Draw and explain BIST architecture.
9. Explain terms w.r.t Scan test:
a. Test Compiler
b. LSSD
10. Explain the signal integrity effects in ASIC design.
11.Explain basic ATPG algorithm with an example.
12.What is need of multiple input signature analysis?