Aushapur (V), Ghatkesar (M), R. R.

Dist
Subject: VLSI Design MAKE UP TEST Date: 16-11-2019
Branch: IV B.Tech I SEM ECE (B) Max Marks: 75M
This question Paper contains two parts A and B.Part A is compulsory which carries 25
marks. Part B carries 50 marks and each question carries 10 marks.
PART-A
a) Define gm of MOS transistor. (3 marks)
b) What are the different MOS layers? (2 marks)
c) What are the two types of layout design rules? (2 marks)
d) Define IC fabrication process? (2 marks)
e) Define the Parasitic capacitance (2 marks)
f) What are Different delays in gate level? (3 marks)
g) What is super buffer? (3 marks)
h) Explain difference between stick diagram and layout diagram (3 marks)
i) Draw the 1 bit SRAM cell? (3 marks)
j) Implement 2:1 Mux using PAL? (2 marks)

PART-B
2). Draw the circuits CMOS Inverter and explain about their operation and compare them?
OR
3) Find gm and rds for an n channel transistor with Vgs =1.2V,Vtn =0.8V,(W/L)=10;
μnCox =92 μ A/V² and Vds =Veff +0.5V, the output impedance constant λ = 95.3 × 10−3/V −1.

4) Draw the stick diagram and layout for the logic shown Y= (A+B) (C+D).
OR
5) Draw the flow chart of VLSI Design flow and explain the operation of each step in detail.

6) Design a 2 input AND gate using Switch logic (pass transistor or Transmission gate)

OR
7) Derive the expressions for rise time and fall time of CMOS inverter.

8) Give the constructional difference between SRAM and DRAM?

OR
9) Compare different types of CMOS subsystem shifters.

10) Why the chip testing is needed? At what levels testing a chip can occur??
OR
11) what are the different type of PLD’s?

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