ABSTRACT

The adder is a digital circuit that can be perform addition of two numbers.
The half adder or full adder performs addition of single bit numbers, it increase the bit
size of a number we are using parallel adders which are build from cascaded of full
adders ,for example carry save adder (CSA),carry select adder (CSLA),carry skip adder
(CSKA) and etc.
In this paper, carry save adder (CSA) was designed that has a higher speed
compared with the conventional one. Carry save adder by using multiplexer logic has
taken as a conventional one and AND-OR-INVERTER logic as a proposed structure. In
addition, instead of utilizing multiplexer logic, the proposed structure makes use of AND-
OR-Invert (AOI) compound gates for the adder. In this paper Xilinx-ISE 12.3i tool is
used for simulation, logical verification, and further synthesizing and the HDL language
used for the paper is VERILOG.

TOOL USED: Xilinx ISE

LANGUAGE USED: VERILOG