ECE 274 - Digital Logic Digital Design

Lecture 4 Combinational Logic Design

„ Lecture 4
„ Combination Logic Design Process
„ Common Combinational Components
„ Decoders
„ Multiplexers

Counting the number of possible Boolean functions of two variables.

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Digital Design Digital Design

Combinational Logic Design: Multiple Output Circuits Combinational Logic Design: Combination Logic Design Process

The 16 possible Boolean functions of two variables.

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Digital Design Digital Design

Combinational Logic Design: Design Process Combinational Logic Design: Design Process

„ Number of 1’s counter „ Step 1: Capture the Function

„ We want to design a circuit that counts the number of 1s present
on 3 inputs a, b, c, and outputs that number in binary using 2
outputs, y and z.

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 Digital Design Digital Design
Combinational Logic Design: Design Process Combinational Logic Design: Design Process

„ Step 2: Convert to Equations „ Step 3: Implement as Gate Based Circuit

„ y = a’bc + ab’c + abc’ + abc a
b
„ a’bc + ab’c + ab(c’+c) -> a’bc + ab’c + ab a
c
„ z = a’b’c + a’bc’ + ab’c’ + abc b a
c
b
a c z
b y
a
c
b
a c
b a
b
c

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Digital Design Digital Design

Combinational Logic Design: Not Really a Quiz Combinational Logic Design: Examples

„ Use the Process Above: „ Example 1:

„ Create a 4-bit prime number detector. The circuit has four
inputs, N3, N2, N1, and N0 that correspond to a 4-bit
number (N3 is the most significant bit) and one output
labeled P that outputs a 1 when the input is a prime
number, 0 otherwise.
„ Create a 4-bit squared number detector. The circuit has
four inputs, N3, N2, N1, and N0 that correspond to a 4-bit
number (N3 is the most significant bit) and one output
labeled S that outputs a 1 when the input is the square of a
positive integer, 0 otherwise.

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Digital Design Digital Design

Combinational Logic Design: Examples Combinational Logic Design: Examples

„ Example 2:
„ Create a greater than 5 detector. The circuit has four
inputs, N3, N2, N1, and N0 that correspond to a 4-bit
number (N3 is the most significant bit) and one output
labeled G that outputs a 1 when the input is greater than 5,
0 otherwise.
„ Example 3:
„ A network router connects multiple computers together and allows them
to send messages to each other. If two or more computers send
messages simultaneously, they collide and the messages must be resent.
Using the combinational design process, create a collision detection circuit
for a router that connects 4 computers. The circuit has 4 inputs labeled
M0 through M3 that are 1 when the corresponding computer is sending a
message and 0 otherwise. The circuit has one output labeled C that is 1
when a collision is detected and 0 otherwise.

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 Digital Design Digital Design
Got Decoder? Decoder Properties

Decoder i1 i0 d3 d2 d1 d0
„ Need to activate only one product: „ d0
0 0 0 0 0 1
„ No data inputs i0 2x4 d1
„ 1: activated (product released) 0 1 0 0 1 0
„ n control bits i1 Decoder d2 1 0 0 1 0 0
„ 0: not activated 2n outputs 1 1 1 0 0 0
„ d3
„ Only one slot can be activated at a
time.
d0

d0 1 d0 0 d0 0 d0 0 d1
0 0 0 1
i0 d1 i0 d 1 1 i0 d 1 0 1 i0 d 1 0
0 0 1 d2
i1 d2 i1 d 2 0 0 i1 d 2 1 1 i1 d 2 0
d3 0 d3 0 d3 0 d3 1 d3

(a)

i1 i0 (b)

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Digital Design Digital Design

Decoder with Enable Combinational Logic Design

d0 0 d0 0 „ Using a 6x64 decoder to interface a microprocessor and a column of lights for a New
Year’s Eve display. The microprocessor sets e=1 when the last minute countdown
begins, and then counts down from 59 to 0 in binary on the pins i5..i0. Note that
1 i0 d1 0 1 i0 d1 0 the microprocessor should never output 60, 61, 62 or 63 on i5..i0, and thus those
outputs of the decoder go unused.
1 i1 d2 0 1 i1 d2 0 i0 d0
0 Happy
New Year!
Microprocessor

1 0 i1 d1 1
e d3 e d3 i2
i3
d2
d3
2
3
i4
i5
1 (a) (b) d58
0 e d59
d60
d61 58
59
6x64 d62
(a) e=1: normal decoding, (b) e=0: all outputs 0. dec. d63

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Digital Design Digital Design

Combinational Design: Common Component: Decoder Combinational Design: Common Component: Decoder
a d0
b
c

d0 zone 0 d1
a zone 1
Micro- b d1 d2
d2 2
processor c d3 3 4 d3
d4
decoder d5 5
NOT(RAIN) d6 d4
e d7 6
7 d5

d6

d7
NOT(RAIN) e
Sprinkler valve controller block diagram.
Sprinkler valve controller circuit (actually a 3x8 decoder with enable).

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 Digital Design Digital Design
Combinational Design: Common Component: Decoder Combinational Design: Common Component: Decoder
w0 w0 y0 y0
w1 w1 y1 y1
w0 w0 y0 y0 y2 y2
w1 w1 y1 y1 En y3 y3

y2 y2
w2 w0 y0 y4
En y3 y3
w1 y1 y5
y2 y6
w2 w0 y0 y3 y7
En
w3 w1 y1
En w0 y0 y4 y2
En En y3 w0 y0 y8
w1 y1 y5 w1 y1 y9
y2 y6 y2 y10
En y3 y11
En y3 y7

w0 y0 y12
w1 y1 y13
y2 y14
En y3 y15

A 4-to-16 decoder built using a decoder tree.

A 3-to-8 decoder using two 2-to-4 decoders.
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Digital Design Digital Design

Combinational Design: Common Component: Multiplexer Combinational Design: Common Component: Multiplexer

„ Multiplexor data inputs

...
„ 2 data inputs
i0 n

„ n control bits
control
mux
inputs
d „ 1 output
i1 d

i2
1 2 i0
0 3 2x1 2x1 2x1
i0 i0 i0 d
i3 control lever
i1 d i1 d i1 d i1
s0 s0 s0
0 1
s0
A multiplexer is like a railyard switch, determining which input track connects to the 2x1 multiplexer block symbol (left), connections for s0=0 and s0=1 (middle), and
single output track, according to the switch’s control lever. internal design (right).
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Digital Design Digital Design

Combinational Design: Common Component: Multiplexer Combinational Design: Common Component: Multiplexer

i0 Mayor’s switches
4x1 1 4x1 on/off
i0 i0
i1
i1 2
Proposal

d d i1
i2 d
i2 i2
3
i3 i3 Green/
s1 s0 i3 Red
4 s1 s0 LED

manager’s
s1 s0 switches
4x1 multiplexer block symbol (left) and internal design (right).
Mayor’s vote display system implemented using a 4x1 mux.

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 Digital Design Digital Design
Combinational Design: Common Component: Multiplexer Combinational Logic Design

„ 4-bit 2x1 mux: (a) internal design using four 2x1 muxes for selecting among 4-bit data
items A or B, and (b) block diagram of a 4-bit 2x1 mux component, (c) the block
diagram uses a common simplifying notation, using one thick wire with a slanted line
and the number 4 to represent 4 single wires.

a3 i0 2x1 Simplifying
b3 i1 s0d notation:
4
a2 i0 2x1 4 4-bit C
A I0 2x1
b2 i1 s0d D
4
C is short
4
B I1 for:
a1 i0 2x1 s0
b1 i1 s0d c3
s0 c2
a0 i0 2x1
b0 i1 s0d c1
s0 c0
(a) (b) (c)
Above-mirror display.

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Digital Design Digital Design

Combinational Logic Design Combinational Logic Design: Common Component: Multiplexer
s1
central computer

8
From the car’s

T I0 8-bit
mirror display
To the above-

s0
A 8 4x1 8
I1 D
I 8 I2 D w0 0
M 8 w1
I3 s1 s0 1

x y 0
f
1
We’ll des ign
this later w2 0
w3
button 1

Above-mirror display using an 8-bit 4x1 mux.

Using 2-to-1 multiplexers to build a 4-to-1 multiplexer.

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Digital Design
Combinational Logic Design: Common Component: Multiplexer

s0
s1

w0

w3

w4 s2
s3
w7

f
w8

w11

w12

w15

A 16-to-1 multiplexer.
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